max32660_pac/dma/ch/
src.rs

1#[doc = "Register `SRC` reader"]
2pub struct R(crate::R<SRC_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SRC_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SRC_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SRC_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SRC` writer"]
17pub struct W(crate::W<SRC_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SRC_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SRC_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SRC_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SRC` reader - "]
38pub struct SRC_R(crate::FieldReader<u32, u32>);
39impl SRC_R {
40    #[inline(always)]
41    pub(crate) fn new(bits: u32) -> Self {
42        SRC_R(crate::FieldReader::new(bits))
43    }
44}
45impl core::ops::Deref for SRC_R {
46    type Target = crate::FieldReader<u32, u32>;
47    #[inline(always)]
48    fn deref(&self) -> &Self::Target {
49        &self.0
50    }
51}
52#[doc = "Field `SRC` writer - "]
53pub struct SRC_W<'a> {
54    w: &'a mut W,
55}
56impl<'a> SRC_W<'a> {
57    #[doc = r"Writes raw bits to the field"]
58    #[inline(always)]
59    pub unsafe fn bits(self, value: u32) -> &'a mut W {
60        self.w.bits = value;
61        self.w
62    }
63}
64impl R {
65    #[doc = "Bits 0:31"]
66    #[inline(always)]
67    pub fn src(&self) -> SRC_R {
68        SRC_R::new(self.bits)
69    }
70}
71impl W {
72    #[doc = "Bits 0:31"]
73    #[inline(always)]
74    pub fn src(&mut self) -> SRC_W {
75        SRC_W { w: self }
76    }
77    #[doc = "Writes raw bits to the register."]
78    #[inline(always)]
79    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
80        self.0.bits(bits);
81        self
82    }
83}
84#[doc = "Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [src](index.html) module"]
85pub struct SRC_SPEC;
86impl crate::RegisterSpec for SRC_SPEC {
87    type Ux = u32;
88}
89#[doc = "`read()` method returns [src::R](R) reader structure"]
90impl crate::Readable for SRC_SPEC {
91    type Reader = R;
92}
93#[doc = "`write(|w| ..)` method takes [src::W](W) writer structure"]
94impl crate::Writable for SRC_SPEC {
95    type Writer = W;
96}
97#[doc = "`reset()` method sets SRC to value 0"]
98impl crate::Resettable for SRC_SPEC {
99    #[inline(always)]
100    fn reset_value() -> Self::Ux {
101        0
102    }
103}
max32660_pac/dma/ch/src.rs

max32660_pac/dma/ch/
src.rs
