Crate max32660

Crate max32660 

Source
Expand description

Peripheral access API for MAX32660 microcontrollers (generated using svd2rust v0.30.1 ( ))

You can find an overview of the generated API here.

API features to be included in the next svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.

Re-exports§

pub use self::i2c0 as i2c1;
pub use self::tmr0 as tmr1;
pub use self::tmr0 as tmr2;
pub use self::uart0 as uart1;

Modules§

dma
Direct Memory Access Controller.
fcr
Function Control.
flc
Flash Memory Control.
gcr
Global Control Registers.
generic
Common register and bit access and modify traits
gpio0
General Purpose I/O.
i2c0
Inter-Integrated Circuit 0.
icc
Instruction Cache Controller.
pwrseq
Power Sequencer.
rtc
Real Time Clock.
sir
System Initialization.
spi0
Serial Peripheral Interface 0.
spi1
Serial Peripheral Interface 1.
tmr0
Low-Power Configurable Timer 0.
uart0
Universal Asynchronous Receiver/Transmitter 0.
wdt0
Watchdog Timer 0.

Structs§

CBP
Cache and branch predictor maintenance operations
CPUID
CPUID
CorePeripherals
Core peripherals
DCB
Debug Control Block
DMA
Direct Memory Access Controller.
DWT
Data Watchpoint and Trace unit
FCR
Function Control.
FLC
Flash Memory Control.
FPB
Flash Patch and Breakpoint unit
FPU
Floating Point Unit
GCR
Global Control Registers.
GPIO0
General Purpose I/O.
I2C0
Inter-Integrated Circuit 0.
I2C1
Inter-Integrated Circuit 1.
ICC
Instruction Cache Controller.
ITM
Instrumentation Trace Macrocell
MPU
Memory Protection Unit
NVIC
Nested Vector Interrupt Controller
PWRSEQ
Power Sequencer.
Peripherals
All the peripherals.
RTC
Real Time Clock.
SCB
System Control Block
SIR
System Initialization.
SPI0
Serial Peripheral Interface 0.
SPI1
Serial Peripheral Interface 1.
SYST
SysTick: System Timer
TMR0
Low-Power Configurable Timer 0.
TMR1
Low-Power Configurable Timer 1.
TMR2
Low-Power Configurable Timer 2.
TPIU
Trace Port Interface Unit
UART0
Universal Asynchronous Receiver/Transmitter 0.
UART1
Universal Asynchronous Receiver/Transmitter 1.
WDT0
Watchdog Timer 0.

Enums§

Interrupt
Enumeration of all the interrupts.

Constants§

NVIC_PRIO_BITS
Number available in the NVIC for configuring priority