max3263x/clkman/
sys_clk_ctrl_8_uart.rs

1#[doc = "Register `SYS_CLK_CTRL_8_UART` reader"]
2pub struct R(crate::R<SYS_CLK_CTRL_8_UART_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SYS_CLK_CTRL_8_UART_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SYS_CLK_CTRL_8_UART_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SYS_CLK_CTRL_8_UART_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SYS_CLK_CTRL_8_UART` writer"]
17pub struct W(crate::W<SYS_CLK_CTRL_8_UART_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SYS_CLK_CTRL_8_UART_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SYS_CLK_CTRL_8_UART_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SYS_CLK_CTRL_8_UART_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `uart_clk_scale` reader - Control Settings for CLK8 - Source Clock for All UARTs"]
38pub type UART_CLK_SCALE_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `uart_clk_scale` writer - Control Settings for CLK8 - Source Clock for All UARTs"]
40pub type UART_CLK_SCALE_W<'a> = crate::FieldWriter<'a, u32, SYS_CLK_CTRL_8_UART_SPEC, u8, u8, 4, 0>;
41impl R {
42    #[doc = "Bits 0:3 - Control Settings for CLK8 - Source Clock for All UARTs"]
43    #[inline(always)]
44    pub fn uart_clk_scale(&self) -> UART_CLK_SCALE_R {
45        UART_CLK_SCALE_R::new((self.bits & 0x0f) as u8)
46    }
47}
48impl W {
49    #[doc = "Bits 0:3 - Control Settings for CLK8 - Source Clock for All UARTs"]
50    #[inline(always)]
51    pub fn uart_clk_scale(&mut self) -> UART_CLK_SCALE_W {
52        UART_CLK_SCALE_W::new(self)
53    }
54    #[doc = "Writes raw bits to the register."]
55    #[inline(always)]
56    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
57        self.0.bits(bits);
58        self
59    }
60}
61#[doc = "Control Settings for CLK8 - Source Clock for All UARTs\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sys_clk_ctrl_8_uart](index.html) module"]
62pub struct SYS_CLK_CTRL_8_UART_SPEC;
63impl crate::RegisterSpec for SYS_CLK_CTRL_8_UART_SPEC {
64    type Ux = u32;
65}
66#[doc = "`read()` method returns [sys_clk_ctrl_8_uart::R](R) reader structure"]
67impl crate::Readable for SYS_CLK_CTRL_8_UART_SPEC {
68    type Reader = R;
69}
70#[doc = "`write(|w| ..)` method takes [sys_clk_ctrl_8_uart::W](W) writer structure"]
71impl crate::Writable for SYS_CLK_CTRL_8_UART_SPEC {
72    type Writer = W;
73}
74#[doc = "`reset()` method sets SYS_CLK_CTRL_8_UART to value 0"]
75impl crate::Resettable for SYS_CLK_CTRL_8_UART_SPEC {
76    #[inline(always)]
77    fn reset_value() -> Self::Ux {
78        0
79    }
80}
max3263x/clkman/sys_clk_ctrl_8_uart.rs

max3263x/clkman/
sys_clk_ctrl_8_uart.rs
