1#[doc = "Register `CLK_GATE_CTRL1` reader"]
2pub struct R(crate::R<CLK_GATE_CTRL1_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CLK_GATE_CTRL1_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CLK_GATE_CTRL1_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CLK_GATE_CTRL1_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CLK_GATE_CTRL1` writer"]
17pub struct W(crate::W<CLK_GATE_CTRL1_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CLK_GATE_CTRL1_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CLK_GATE_CTRL1_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CLK_GATE_CTRL1_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `watchdog1_clk_gater` reader - Clock Gating Control for Watchdog Timer 1"]
38pub type WATCHDOG1_CLK_GATER_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `watchdog1_clk_gater` writer - Clock Gating Control for Watchdog Timer 1"]
40pub type WATCHDOG1_CLK_GATER_W<'a> = crate::FieldWriter<'a, u32, CLK_GATE_CTRL1_SPEC, u8, u8, 2, 0>;
41#[doc = "Field `gpio_clk_gater` reader - Clock Gating Control for GPIO Ports"]
42pub type GPIO_CLK_GATER_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `gpio_clk_gater` writer - Clock Gating Control for GPIO Ports"]
44pub type GPIO_CLK_GATER_W<'a> = crate::FieldWriter<'a, u32, CLK_GATE_CTRL1_SPEC, u8, u8, 2, 2>;
45#[doc = "Field `timer0_clk_gater` reader - Clock Gating Control for Timer/Counter Module 0"]
46pub type TIMER0_CLK_GATER_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `timer0_clk_gater` writer - Clock Gating Control for Timer/Counter Module 0"]
48pub type TIMER0_CLK_GATER_W<'a> = crate::FieldWriter<'a, u32, CLK_GATE_CTRL1_SPEC, u8, u8, 2, 4>;
49#[doc = "Field `timer1_clk_gater` reader - Clock Gating Control for Timer/Counter Module 1"]
50pub type TIMER1_CLK_GATER_R = crate::FieldReader<u8, u8>;
51#[doc = "Field `timer1_clk_gater` writer - Clock Gating Control for Timer/Counter Module 1"]
52pub type TIMER1_CLK_GATER_W<'a> = crate::FieldWriter<'a, u32, CLK_GATE_CTRL1_SPEC, u8, u8, 2, 6>;
53#[doc = "Field `timer2_clk_gater` reader - Clock Gating Control for Timer/Counter Module 2"]
54pub type TIMER2_CLK_GATER_R = crate::FieldReader<u8, u8>;
55#[doc = "Field `timer2_clk_gater` writer - Clock Gating Control for Timer/Counter Module 2"]
56pub type TIMER2_CLK_GATER_W<'a> = crate::FieldWriter<'a, u32, CLK_GATE_CTRL1_SPEC, u8, u8, 2, 8>;
57#[doc = "Field `timer3_clk_gater` reader - Clock Gating Control for Timer/Counter Module 3"]
58pub type TIMER3_CLK_GATER_R = crate::FieldReader<u8, u8>;
59#[doc = "Field `timer3_clk_gater` writer - Clock Gating Control for Timer/Counter Module 3"]
60pub type TIMER3_CLK_GATER_W<'a> = crate::FieldWriter<'a, u32, CLK_GATE_CTRL1_SPEC, u8, u8, 2, 10>;
61#[doc = "Field `timer4_clk_gater` reader - Clock Gating Control for Timer/Counter Module 4"]
62pub type TIMER4_CLK_GATER_R = crate::FieldReader<u8, u8>;
63#[doc = "Field `timer4_clk_gater` writer - Clock Gating Control for Timer/Counter Module 4"]
64pub type TIMER4_CLK_GATER_W<'a> = crate::FieldWriter<'a, u32, CLK_GATE_CTRL1_SPEC, u8, u8, 2, 12>;
65#[doc = "Field `timer5_clk_gater` reader - Clock Gating Control for Timer/Counter Module 5"]
66pub type TIMER5_CLK_GATER_R = crate::FieldReader<u8, u8>;
67#[doc = "Field `timer5_clk_gater` writer - Clock Gating Control for Timer/Counter Module 5"]
68pub type TIMER5_CLK_GATER_W<'a> = crate::FieldWriter<'a, u32, CLK_GATE_CTRL1_SPEC, u8, u8, 2, 14>;
69#[doc = "Field `pulsetrain_clk_gater` reader - Clock Gating Control for Pulse Train Generators"]
70pub type PULSETRAIN_CLK_GATER_R = crate::FieldReader<u8, u8>;
71#[doc = "Field `pulsetrain_clk_gater` writer - Clock Gating Control for Pulse Train Generators"]
72pub type PULSETRAIN_CLK_GATER_W<'a> =
73 crate::FieldWriter<'a, u32, CLK_GATE_CTRL1_SPEC, u8, u8, 2, 16>;
74#[doc = "Field `uart0_clk_gater` reader - Clock Gating Control for UART 0"]
75pub type UART0_CLK_GATER_R = crate::FieldReader<u8, u8>;
76#[doc = "Field `uart0_clk_gater` writer - Clock Gating Control for UART 0"]
77pub type UART0_CLK_GATER_W<'a> = crate::FieldWriter<'a, u32, CLK_GATE_CTRL1_SPEC, u8, u8, 2, 18>;
78#[doc = "Field `uart1_clk_gater` reader - Clock Gating Control for UART 1"]
79pub type UART1_CLK_GATER_R = crate::FieldReader<u8, u8>;
80#[doc = "Field `uart1_clk_gater` writer - Clock Gating Control for UART 1"]
81pub type UART1_CLK_GATER_W<'a> = crate::FieldWriter<'a, u32, CLK_GATE_CTRL1_SPEC, u8, u8, 2, 20>;
82#[doc = "Field `uart2_clk_gater` reader - Clock Gating Control for UART 2"]
83pub type UART2_CLK_GATER_R = crate::FieldReader<u8, u8>;
84#[doc = "Field `uart2_clk_gater` writer - Clock Gating Control for UART 2"]
85pub type UART2_CLK_GATER_W<'a> = crate::FieldWriter<'a, u32, CLK_GATE_CTRL1_SPEC, u8, u8, 2, 22>;
86#[doc = "Field `uart3_clk_gater` reader - Clock Gating Control for UART 3"]
87pub type UART3_CLK_GATER_R = crate::FieldReader<u8, u8>;
88#[doc = "Field `uart3_clk_gater` writer - Clock Gating Control for UART 3"]
89pub type UART3_CLK_GATER_W<'a> = crate::FieldWriter<'a, u32, CLK_GATE_CTRL1_SPEC, u8, u8, 2, 24>;
90#[doc = "Field `i2cm0_clk_gater` reader - Clock Gating Control for I2C Master 0"]
91pub type I2CM0_CLK_GATER_R = crate::FieldReader<u8, u8>;
92#[doc = "Field `i2cm0_clk_gater` writer - Clock Gating Control for I2C Master 0"]
93pub type I2CM0_CLK_GATER_W<'a> = crate::FieldWriter<'a, u32, CLK_GATE_CTRL1_SPEC, u8, u8, 2, 26>;
94#[doc = "Field `i2cm1_clk_gater` reader - Clock Gating Control for I2C Master 1"]
95pub type I2CM1_CLK_GATER_R = crate::FieldReader<u8, u8>;
96#[doc = "Field `i2cm1_clk_gater` writer - Clock Gating Control for I2C Master 1"]
97pub type I2CM1_CLK_GATER_W<'a> = crate::FieldWriter<'a, u32, CLK_GATE_CTRL1_SPEC, u8, u8, 2, 28>;
98#[doc = "Field `i2cm2_clk_gater` reader - Clock Gating Control for I2C Master 2"]
99pub type I2CM2_CLK_GATER_R = crate::FieldReader<u8, u8>;
100#[doc = "Field `i2cm2_clk_gater` writer - Clock Gating Control for I2C Master 2"]
101pub type I2CM2_CLK_GATER_W<'a> = crate::FieldWriter<'a, u32, CLK_GATE_CTRL1_SPEC, u8, u8, 2, 30>;
102impl R {
103 #[doc = "Bits 0:1 - Clock Gating Control for Watchdog Timer 1"]
104 #[inline(always)]
105 pub fn watchdog1_clk_gater(&self) -> WATCHDOG1_CLK_GATER_R {
106 WATCHDOG1_CLK_GATER_R::new((self.bits & 3) as u8)
107 }
108 #[doc = "Bits 2:3 - Clock Gating Control for GPIO Ports"]
109 #[inline(always)]
110 pub fn gpio_clk_gater(&self) -> GPIO_CLK_GATER_R {
111 GPIO_CLK_GATER_R::new(((self.bits >> 2) & 3) as u8)
112 }
113 #[doc = "Bits 4:5 - Clock Gating Control for Timer/Counter Module 0"]
114 #[inline(always)]
115 pub fn timer0_clk_gater(&self) -> TIMER0_CLK_GATER_R {
116 TIMER0_CLK_GATER_R::new(((self.bits >> 4) & 3) as u8)
117 }
118 #[doc = "Bits 6:7 - Clock Gating Control for Timer/Counter Module 1"]
119 #[inline(always)]
120 pub fn timer1_clk_gater(&self) -> TIMER1_CLK_GATER_R {
121 TIMER1_CLK_GATER_R::new(((self.bits >> 6) & 3) as u8)
122 }
123 #[doc = "Bits 8:9 - Clock Gating Control for Timer/Counter Module 2"]
124 #[inline(always)]
125 pub fn timer2_clk_gater(&self) -> TIMER2_CLK_GATER_R {
126 TIMER2_CLK_GATER_R::new(((self.bits >> 8) & 3) as u8)
127 }
128 #[doc = "Bits 10:11 - Clock Gating Control for Timer/Counter Module 3"]
129 #[inline(always)]
130 pub fn timer3_clk_gater(&self) -> TIMER3_CLK_GATER_R {
131 TIMER3_CLK_GATER_R::new(((self.bits >> 10) & 3) as u8)
132 }
133 #[doc = "Bits 12:13 - Clock Gating Control for Timer/Counter Module 4"]
134 #[inline(always)]
135 pub fn timer4_clk_gater(&self) -> TIMER4_CLK_GATER_R {
136 TIMER4_CLK_GATER_R::new(((self.bits >> 12) & 3) as u8)
137 }
138 #[doc = "Bits 14:15 - Clock Gating Control for Timer/Counter Module 5"]
139 #[inline(always)]
140 pub fn timer5_clk_gater(&self) -> TIMER5_CLK_GATER_R {
141 TIMER5_CLK_GATER_R::new(((self.bits >> 14) & 3) as u8)
142 }
143 #[doc = "Bits 16:17 - Clock Gating Control for Pulse Train Generators"]
144 #[inline(always)]
145 pub fn pulsetrain_clk_gater(&self) -> PULSETRAIN_CLK_GATER_R {
146 PULSETRAIN_CLK_GATER_R::new(((self.bits >> 16) & 3) as u8)
147 }
148 #[doc = "Bits 18:19 - Clock Gating Control for UART 0"]
149 #[inline(always)]
150 pub fn uart0_clk_gater(&self) -> UART0_CLK_GATER_R {
151 UART0_CLK_GATER_R::new(((self.bits >> 18) & 3) as u8)
152 }
153 #[doc = "Bits 20:21 - Clock Gating Control for UART 1"]
154 #[inline(always)]
155 pub fn uart1_clk_gater(&self) -> UART1_CLK_GATER_R {
156 UART1_CLK_GATER_R::new(((self.bits >> 20) & 3) as u8)
157 }
158 #[doc = "Bits 22:23 - Clock Gating Control for UART 2"]
159 #[inline(always)]
160 pub fn uart2_clk_gater(&self) -> UART2_CLK_GATER_R {
161 UART2_CLK_GATER_R::new(((self.bits >> 22) & 3) as u8)
162 }
163 #[doc = "Bits 24:25 - Clock Gating Control for UART 3"]
164 #[inline(always)]
165 pub fn uart3_clk_gater(&self) -> UART3_CLK_GATER_R {
166 UART3_CLK_GATER_R::new(((self.bits >> 24) & 3) as u8)
167 }
168 #[doc = "Bits 26:27 - Clock Gating Control for I2C Master 0"]
169 #[inline(always)]
170 pub fn i2cm0_clk_gater(&self) -> I2CM0_CLK_GATER_R {
171 I2CM0_CLK_GATER_R::new(((self.bits >> 26) & 3) as u8)
172 }
173 #[doc = "Bits 28:29 - Clock Gating Control for I2C Master 1"]
174 #[inline(always)]
175 pub fn i2cm1_clk_gater(&self) -> I2CM1_CLK_GATER_R {
176 I2CM1_CLK_GATER_R::new(((self.bits >> 28) & 3) as u8)
177 }
178 #[doc = "Bits 30:31 - Clock Gating Control for I2C Master 2"]
179 #[inline(always)]
180 pub fn i2cm2_clk_gater(&self) -> I2CM2_CLK_GATER_R {
181 I2CM2_CLK_GATER_R::new(((self.bits >> 30) & 3) as u8)
182 }
183}
184impl W {
185 #[doc = "Bits 0:1 - Clock Gating Control for Watchdog Timer 1"]
186 #[inline(always)]
187 pub fn watchdog1_clk_gater(&mut self) -> WATCHDOG1_CLK_GATER_W {
188 WATCHDOG1_CLK_GATER_W::new(self)
189 }
190 #[doc = "Bits 2:3 - Clock Gating Control for GPIO Ports"]
191 #[inline(always)]
192 pub fn gpio_clk_gater(&mut self) -> GPIO_CLK_GATER_W {
193 GPIO_CLK_GATER_W::new(self)
194 }
195 #[doc = "Bits 4:5 - Clock Gating Control for Timer/Counter Module 0"]
196 #[inline(always)]
197 pub fn timer0_clk_gater(&mut self) -> TIMER0_CLK_GATER_W {
198 TIMER0_CLK_GATER_W::new(self)
199 }
200 #[doc = "Bits 6:7 - Clock Gating Control for Timer/Counter Module 1"]
201 #[inline(always)]
202 pub fn timer1_clk_gater(&mut self) -> TIMER1_CLK_GATER_W {
203 TIMER1_CLK_GATER_W::new(self)
204 }
205 #[doc = "Bits 8:9 - Clock Gating Control for Timer/Counter Module 2"]
206 #[inline(always)]
207 pub fn timer2_clk_gater(&mut self) -> TIMER2_CLK_GATER_W {
208 TIMER2_CLK_GATER_W::new(self)
209 }
210 #[doc = "Bits 10:11 - Clock Gating Control for Timer/Counter Module 3"]
211 #[inline(always)]
212 pub fn timer3_clk_gater(&mut self) -> TIMER3_CLK_GATER_W {
213 TIMER3_CLK_GATER_W::new(self)
214 }
215 #[doc = "Bits 12:13 - Clock Gating Control for Timer/Counter Module 4"]
216 #[inline(always)]
217 pub fn timer4_clk_gater(&mut self) -> TIMER4_CLK_GATER_W {
218 TIMER4_CLK_GATER_W::new(self)
219 }
220 #[doc = "Bits 14:15 - Clock Gating Control for Timer/Counter Module 5"]
221 #[inline(always)]
222 pub fn timer5_clk_gater(&mut self) -> TIMER5_CLK_GATER_W {
223 TIMER5_CLK_GATER_W::new(self)
224 }
225 #[doc = "Bits 16:17 - Clock Gating Control for Pulse Train Generators"]
226 #[inline(always)]
227 pub fn pulsetrain_clk_gater(&mut self) -> PULSETRAIN_CLK_GATER_W {
228 PULSETRAIN_CLK_GATER_W::new(self)
229 }
230 #[doc = "Bits 18:19 - Clock Gating Control for UART 0"]
231 #[inline(always)]
232 pub fn uart0_clk_gater(&mut self) -> UART0_CLK_GATER_W {
233 UART0_CLK_GATER_W::new(self)
234 }
235 #[doc = "Bits 20:21 - Clock Gating Control for UART 1"]
236 #[inline(always)]
237 pub fn uart1_clk_gater(&mut self) -> UART1_CLK_GATER_W {
238 UART1_CLK_GATER_W::new(self)
239 }
240 #[doc = "Bits 22:23 - Clock Gating Control for UART 2"]
241 #[inline(always)]
242 pub fn uart2_clk_gater(&mut self) -> UART2_CLK_GATER_W {
243 UART2_CLK_GATER_W::new(self)
244 }
245 #[doc = "Bits 24:25 - Clock Gating Control for UART 3"]
246 #[inline(always)]
247 pub fn uart3_clk_gater(&mut self) -> UART3_CLK_GATER_W {
248 UART3_CLK_GATER_W::new(self)
249 }
250 #[doc = "Bits 26:27 - Clock Gating Control for I2C Master 0"]
251 #[inline(always)]
252 pub fn i2cm0_clk_gater(&mut self) -> I2CM0_CLK_GATER_W {
253 I2CM0_CLK_GATER_W::new(self)
254 }
255 #[doc = "Bits 28:29 - Clock Gating Control for I2C Master 1"]
256 #[inline(always)]
257 pub fn i2cm1_clk_gater(&mut self) -> I2CM1_CLK_GATER_W {
258 I2CM1_CLK_GATER_W::new(self)
259 }
260 #[doc = "Bits 30:31 - Clock Gating Control for I2C Master 2"]
261 #[inline(always)]
262 pub fn i2cm2_clk_gater(&mut self) -> I2CM2_CLK_GATER_W {
263 I2CM2_CLK_GATER_W::new(self)
264 }
265 #[doc = "Writes raw bits to the register."]
266 #[inline(always)]
267 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
268 self.0.bits(bits);
269 self
270 }
271}
272#[doc = "Dynamic Clock Gating Control Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_gate_ctrl1](index.html) module"]
273pub struct CLK_GATE_CTRL1_SPEC;
274impl crate::RegisterSpec for CLK_GATE_CTRL1_SPEC {
275 type Ux = u32;
276}
277#[doc = "`read()` method returns [clk_gate_ctrl1::R](R) reader structure"]
278impl crate::Readable for CLK_GATE_CTRL1_SPEC {
279 type Reader = R;
280}
281#[doc = "`write(|w| ..)` method takes [clk_gate_ctrl1::W](W) writer structure"]
282impl crate::Writable for CLK_GATE_CTRL1_SPEC {
283 type Writer = W;
284}
285#[doc = "`reset()` method sets CLK_GATE_CTRL1 to value 0"]
286impl crate::Resettable for CLK_GATE_CTRL1_SPEC {
287 #[inline(always)]
288 fn reset_value() -> Self::Ux {
289 0
290 }
291}