Expand description
Peripheral access API for MAX3263X microcontrollers (generated using svd2rust v0.20.0 ( ))
You can find an overview of the generated API here.
API features to be included in the next
svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.
Re-exports
pub use pmu0 as pmu1;pub use pmu0 as pmu2;pub use pmu0 as pmu3;pub use pmu0 as pmu4;pub use pmu0 as pmu5;pub use wdt0 as wdt1;pub use tmr0 as tmr1;pub use tmr0 as tmr2;pub use tmr0 as tmr3;pub use tmr0 as tmr4;pub use tmr0 as tmr5;pub use uart0 as uart1;pub use uart0 as uart2;pub use uart0 as uart3;pub use pt0 as pt1;pub use pt0 as pt2;pub use pt0 as pt3;pub use pt0 as pt4;pub use pt0 as pt5;pub use pt0 as pt6;pub use pt0 as pt7;pub use pt0 as pt8;pub use pt0 as pt9;pub use pt0 as pt10;pub use pt0 as pt11;pub use pt0 as pt12;pub use pt0 as pt13;pub use pt0 as pt14;pub use pt0 as pt15;pub use i2cm0 as i2cm1;pub use i2cm0 as i2cm2;pub use spim0 as spim1;pub use spim0 as spim2;Modules
10-bit Analog to Digital Converter
AES Cryptographic Engine
System Clock Manager
CRC-16/CRC-32 Engine
Flash Controller
Common register and bit access and modify traits
General Purpose I/O Ports (GPIO)
I2C Master 0 Interface
I2C Slave Interface
Instruction Cache Controller
System I/O Manager
MAA Cryptographic Engine
1-Wire Master Interface
Peripheral Management Unit
Pulse Train Generation
Pulse Train Generation
System Power Manager
Power Sequencer
RTC Configuration Register
Real Time Clock
SPI Master Interface
SPI Slave Interface
SPI XIP Interface
16/32 bit Timer/Counters
Trust Protection Unit (TPU)
Trust Protection Unit (TPU)
UART / Serial Port Interface
USB Device Controller
Watchdog Timers
Structs
10-bit Analog to Digital Converter
AES Cryptographic Engine
Cache and branch predictor maintenance operations
System Clock Manager
CPUID
CRC-16/CRC-32 Engine
Core peripherals
Debug Control Block
Data Watchpoint and Trace unit
Flash Controller
Flash Patch and Breakpoint unit
Floating Point Unit
General Purpose I/O Ports (GPIO)
I2C Master 0 Interface
I2C Master 0 Interface
I2C Master 0 Interface
I2C Slave Interface
Instruction Cache Controller
System I/O Manager
Instrumentation Trace Macrocell
MAA Cryptographic Engine
Memory Protection Unit
Nested Vector Interrupt Controller
1-Wire Master Interface
Peripheral Management Unit
Peripheral Management Unit
Peripheral Management Unit
Peripheral Management Unit
Peripheral Management Unit
Peripheral Management Unit
Pulse Train Generation
Pulse Train Generation
Pulse Train Generation
Pulse Train Generation
Pulse Train Generation
Pulse Train Generation
Pulse Train Generation
Pulse Train Generation
Pulse Train Generation
Pulse Train Generation
Pulse Train Generation
Pulse Train Generation
Pulse Train Generation
Pulse Train Generation
Pulse Train Generation
Pulse Train Generation
Pulse Train Generation
System Power Manager
Power Sequencer
All the peripherals
RTC Configuration Register
Real Time Clock
System Control Block
SPI Master Interface
SPI Master Interface
SPI Master Interface
SPI Slave Interface
SPI XIP Interface
SysTick: System Timer
16/32 bit Timer/Counters
16/32 bit Timer/Counters
16/32 bit Timer/Counters
16/32 bit Timer/Counters
16/32 bit Timer/Counters
16/32 bit Timer/Counters
Trace Port Interface Unit
Trust Protection Unit (TPU)
Trust Protection Unit (TPU)
UART / Serial Port Interface
UART / Serial Port Interface
UART / Serial Port Interface
UART / Serial Port Interface
USB Device Controller
Watchdog Timers
Watchdog Timers
Enums
Enumeration of all the interrupts.
Constants
Number available in the NVIC for configuring priority