Crate max3263x

Crate max3263x 

Source
Expand description

Peripheral access API for MAX3263X microcontrollers (generated using svd2rust v0.24.0 ( ))

You can find an overview of the generated API here.

API features to be included in the next svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.

Re-exports§

pub use pmu0 as pmu1;
pub use pmu0 as pmu2;
pub use pmu0 as pmu3;
pub use pmu0 as pmu4;
pub use pmu0 as pmu5;
pub use wdt0 as wdt1;
pub use tmr0 as tmr1;
pub use tmr0 as tmr2;
pub use tmr0 as tmr3;
pub use tmr0 as tmr4;
pub use tmr0 as tmr5;
pub use uart0 as uart1;
pub use uart0 as uart2;
pub use uart0 as uart3;
pub use pt0 as pt1;
pub use pt0 as pt2;
pub use pt0 as pt3;
pub use pt0 as pt4;
pub use pt0 as pt5;
pub use pt0 as pt6;
pub use pt0 as pt7;
pub use pt0 as pt8;
pub use pt0 as pt9;
pub use pt0 as pt10;
pub use pt0 as pt11;
pub use pt0 as pt12;
pub use pt0 as pt13;
pub use pt0 as pt14;
pub use pt0 as pt15;
pub use i2cm0 as i2cm1;
pub use i2cm0 as i2cm2;
pub use spim0 as spim1;
pub use spim0 as spim2;

Modules§

adc
10-bit Analog to Digital Converter
aes
AES Cryptographic Engine
clkman
System Clock Manager
crc
CRC-16/CRC-32 Engine
flc
Flash Controller
generic
Common register and bit access and modify traits
gpio
General Purpose I/O Ports (GPIO)
i2cm0
I2C Master 0 Interface
i2cs
I2C Slave Interface
icc
Instruction Cache Controller
ioman
System I/O Manager
maa
MAA Cryptographic Engine
owm
1-Wire Master Interface
pmu0
Peripheral Management Unit
pt0
Pulse Train Generation
ptg
Pulse Train Generation
pwrman
System Power Manager
pwrseq
Power Sequencer
rtccfg
RTC Configuration Register
rtctmr
Real Time Clock
spim0
SPI Master Interface
spis
SPI Slave Interface
spix
SPI XIP Interface
tmr0
16/32 bit Timer/Counters
tpu
Trust Protection Unit (TPU)
tpu_tsr
Trust Protection Unit (TPU)
uart0
UART / Serial Port Interface
usb
USB Device Controller
wdt0
Watchdog Timers

Structs§

ADC
10-bit Analog to Digital Converter
AES
AES Cryptographic Engine
CBP
Cache and branch predictor maintenance operations
CLKMAN
System Clock Manager
CPUID
CPUID
CRC
CRC-16/CRC-32 Engine
CorePeripherals
Core peripherals
DCB
Debug Control Block
DWT
Data Watchpoint and Trace unit
FLC
Flash Controller
FPB
Flash Patch and Breakpoint unit
FPU
Floating Point Unit
GPIO
General Purpose I/O Ports (GPIO)
I2CM0
I2C Master 0 Interface
I2CM1
I2C Master 0 Interface
I2CM2
I2C Master 0 Interface
I2CS
I2C Slave Interface
ICC
Instruction Cache Controller
IOMAN
System I/O Manager
ITM
Instrumentation Trace Macrocell
MAA
MAA Cryptographic Engine
MPU
Memory Protection Unit
NVIC
Nested Vector Interrupt Controller
OWM
1-Wire Master Interface
PMU0
Peripheral Management Unit
PMU1
Peripheral Management Unit
PMU2
Peripheral Management Unit
PMU3
Peripheral Management Unit
PMU4
Peripheral Management Unit
PMU5
Peripheral Management Unit
PT0
Pulse Train Generation
PT1
Pulse Train Generation
PT2
Pulse Train Generation
PT3
Pulse Train Generation
PT4
Pulse Train Generation
PT5
Pulse Train Generation
PT6
Pulse Train Generation
PT7
Pulse Train Generation
PT8
Pulse Train Generation
PT9
Pulse Train Generation
PT10
Pulse Train Generation
PT11
Pulse Train Generation
PT12
Pulse Train Generation
PT13
Pulse Train Generation
PT14
Pulse Train Generation
PT15
Pulse Train Generation
PTG
Pulse Train Generation
PWRMAN
System Power Manager
PWRSEQ
Power Sequencer
Peripherals
All the peripherals
RTCCFG
RTC Configuration Register
RTCTMR
Real Time Clock
SCB
System Control Block
SPIM0
SPI Master Interface
SPIM1
SPI Master Interface
SPIM2
SPI Master Interface
SPIS
SPI Slave Interface
SPIX
SPI XIP Interface
SYST
SysTick: System Timer
TMR0
16/32 bit Timer/Counters
TMR1
16/32 bit Timer/Counters
TMR2
16/32 bit Timer/Counters
TMR3
16/32 bit Timer/Counters
TMR4
16/32 bit Timer/Counters
TMR5
16/32 bit Timer/Counters
TPIU
Trace Port Interface Unit
TPU
Trust Protection Unit (TPU)
TPU_TSR
Trust Protection Unit (TPU)
UART0
UART / Serial Port Interface
UART1
UART / Serial Port Interface
UART2
UART / Serial Port Interface
UART3
UART / Serial Port Interface
USB
USB Device Controller
WDT0
Watchdog Timers
WDT1
Watchdog Timers

Enums§

Interrupt
Enumeration of all the interrupts.

Constants§

NVIC_PRIO_BITS
Number available in the NVIC for configuring priority