macroassembler::assembler

Module x86assembler

Source
Expand description

X86_64 Assembler implementation.

Structs§

SingleInstructionBufferWriter
X86Assembler
X86InstructionFormatter

Enums§

Condition
PackedCompareCondition
RoundingType
VexImpliedBytes
VexPrefix
VexW

Constants§

ESCAPE_D9_FSTP_singleReal
ESCAPE_DD_FSTP_doubleReal
GROUP1A_OP_POP
GROUP1_OP_ADC
GROUP1_OP_ADD
GROUP1_OP_AND
GROUP1_OP_CMP
GROUP1_OP_OR
GROUP1_OP_SUB
GROUP1_OP_XOR
GROUP2_OP_RCL
GROUP2_OP_RCR
GROUP2_OP_ROL
GROUP2_OP_ROR
GROUP2_OP_SAR
GROUP2_OP_SHL
GROUP2_OP_SHR
GROUP3_OP_DIV
GROUP3_OP_IDIV
GROUP3_OP_NEG
GROUP3_OP_NOT
GROUP3_OP_TEST
GROUP5_OP_CALLN
GROUP5_OP_JMPN
GROUP5_OP_PUSH
GROUP11_MOV
GROUP14_OP_PSLLD
GROUP14_OP_PSLLQ
GROUP14_OP_PSRAQ
GROUP14_OP_PSRLQ
GROUP_BT_OP_BT
INVALID_FPR
INVALID_GPR
INVALID_SP
MOD_RM_MEM_DISP8
MOD_RM_MEM_DISP32
MOD_RM_MEM_NO_DISP
MOD_RM_REG
OP2_3BYTE_ESCAPE_3A
OP2_3BYTE_ESCAPE_38
OP2_3BYTE_ESCAPE_AE
OP2_ADDPD_VpdWpd
OP2_ADDPS_VpsWps
OP2_ADDSD_VsdWsd
OP2_ANDNPD_VpdWpd
OP2_ANDNPS_VpsWps
OP2_ANDPD_VpdWpd
OP2_ANDPS_VpsWps
OP2_BSF
OP2_BSR
OP2_BSWAP
OP2_BTR
OP2_BT_EvEv
OP2_CMOVCC
OP2_CMPPD_VpdWpdIb
OP2_CMPPS_VpsWpsIb
OP2_CMPXCHG
OP2_CMPXCHGb
OP2_CPUID
OP2_CVTDPD2DQ_VdqWdq
OP2_CVTDQ2PD_VdqWdq
OP2_CVTDQ2PS_VsdWsd
OP2_CVTPD2PS_VsdWsd
OP2_CVTPS2PD_VsdWsd
OP2_CVTSD2SS_VsdWsd
OP2_CVTSI2SD_VsdEd
OP2_CVTSI2SS_VssEs
OP2_CVTSS2SD_VsdWsd
OP2_CVTTSD2SI_GdWsd
OP2_CVTTSS2SI_GdWsd
OP2_DIVPD_VpdWpd
OP2_DIVPS_VpsWps
OP2_DIVSD_VsdWsd
OP2_DIVSS_VpsWps
OP2_GROUP_BT_EvIb
OP2_IMUL_GvEv
OP2_JCC_rel32
OP2_LZCNT
OP2_MAXPD_VpdWpd
OP2_MAXPS_VpsWps
OP2_MINPD_VpdWpd
OP2_MINPS_VpsWps
OP2_MOVAPD_VpdWpd
OP2_MOVAPS_VpsWps
OP2_MOVAPS_WpsVps
OP2_MOVDDUP_VqWq
OP2_MOVDQA_VdqWdq
OP2_MOVD_EdVd
OP2_MOVD_VdEd
OP2_MOVHLPS_VqUq
OP2_MOVMSKPD_EqWpd
OP2_MOVMSKPD_VdEd
OP2_MOVMSKPS_EqWps
OP2_MOVQ_PqQq
OP2_MOVQ_QqPq
OP2_MOVSD_VsdWsd
OP2_MOVSD_WsdVsd
OP2_MOVSHDUP_VqWq
OP2_MOVSLDUP_VqWq
OP2_MOVSS_VsdWsd
OP2_MOVSS_WsdVsd
OP2_MOVSX_GvEb
OP2_MOVSX_GvEw
OP2_MOVUPS_VsdWsd
OP2_MOVUPS_WsdVsd
OP2_MOVZX_GvEb
OP2_MOVZX_GvEw
OP2_MULPD_VpdWpd
OP2_MULPS_VpsWps
OP2_MULSD_VsdWsd
OP2_ORPD_VpdWpd
OP2_ORPS_VpsWps
OP2_PACKSSDW_VdqWdq
OP2_PACKSSWB_VdqWdq
OP2_PACKUSWB_VdqWdq
OP2_PADDB_VdqWdq
OP2_PADDD_VdqWdq
OP2_PADDQ_VdqWdq
OP2_PADDSB_VdqWdq
OP2_PADDSW_VdqWdq
OP2_PADDUSB_VdqWdq
OP2_PADDUSW_VdqWdq
OP2_PADDW_VdqWdq
OP2_PAVGB_VdqWdq
OP2_PAVGW_VdqWdq
OP2_PCMPEQB_VdqWdq
OP2_PCMPEQD_VdqWdq
OP2_PCMPEQW_VdqWdq
OP2_PCMPGTB_VdqWdq
OP2_PCMPGTD_VdqWdq
OP2_PCMPGTW_VdqWdq
OP2_PEXTRW_GdUdIb
OP2_PINSRW_VdqRdqp
OP2_PMADDWD_VdqWdq
OP2_PMAXSW_VdqWdq
OP2_PMAXUB_VdqWdq
OP2_PMINSW_VdqWdq
OP2_PMINUB_VdqWdq
OP2_PMOVMSKB_EqWdq
OP2_PMOVMSKB_GdqpUdq
OP2_PMULLW_VdqWdq
OP2_POPCNT
OP2_POR_VdqWdq
OP2_PSHUFD_VdqWdqIb
OP2_PSHUFHW_VdqWdqIb
OP2_PSHUFLW_VdqWdqIb
OP2_PSLLD_UdqIb
OP2_PSLLD_VdqWdq
OP2_PSLLQ_UdqIb
OP2_PSLLQ_VdqWdq
OP2_PSLLW_UdqIb
OP2_PSLLW_VdqWdq
OP2_PSRAD_UdqIb
OP2_PSRAD_VdqWdq
OP2_PSRAW_UdqIb
OP2_PSRAW_VdqWdq
OP2_PSRLD_UdqIb
OP2_PSRLD_VdqWdq
OP2_PSRLQ_UdqIb
OP2_PSRLQ_VdqWdq
OP2_PSRLW_UdqIb
OP2_PSRLW_VdqWdq
OP2_PSUBB_VdqWdq
OP2_PSUBD_VdqWdq
OP2_PSUBQ_VdqWdq
OP2_PSUBSB_VdqWdq
OP2_PSUBSW_VdqWdq
OP2_PSUBUSB_VdqWdq
OP2_PSUBUSW_VdqWdq
OP2_PSUBW_VdqWdq
OP2_PUNPCKHBW_VdqWdq
OP2_PUNPCKLBW_VdqWdq
OP2_PUNPCKLQDQ_VdqWdq
OP2_PXOR_VdqWdq
OP2_RDTSC
OP2_SHUFPD_VpdWpdIb
OP2_SHUFPS_VpdWpdIb
OP2_SQRTPD_VpdWpd
OP2_SQRTPS_VpsWps
OP2_SQRTSD_VsdWsd
OP2_SQRTSS_VssWss
OP2_SUBPD_VpdWpd
OP2_SUBPS_VpsWps
OP2_SUBSD_VsdWsd
OP2_TZCNT
OP2_UCOMISD_VsdWsd
OP2_UCOMISS_VssWss
OP2_UD2
OP2_UNPCKHPD_VpdWpd
OP2_UNPCKLPD_VpdWpd
OP2_VPAND_VxHxWx
OP2_VPSLLD_VxHxWx
OP2_VZEROUPPER
OP2_XADD
OP2_XADDb
OP2_XORPD_VpdWpd
OP2_XORPS_VpsWps
OP3_BLENDVPD_VpdWpdXMM0
OP3_EXTRACTPS_EdVdqIb
OP3_INSERTPS_VpsUpsIb
OP3_LFENCE
OP3_MFENCE
OP3_PABSB_VdqWdq
OP3_PABSD_VdqWdq
OP3_PABSW_VdqWdq
OP3_PCMPEQQ_VdqWdq
OP3_PCMPGTQ_VdqWdq
OP3_PEXTRB_MbVdqIb
OP3_PEXTRD_EyVdqIb
OP3_PEXTRQ_EyVdqIb
OP3_PEXTRW_MwVdqIb
OP3_PINSRB_VdqRdqpIb
OP3_PINSRD_VdqEdIb
OP3_PINSRQ_VdqEqbIb
OP3_PMADDUBSW_VpdWpd
OP3_PMAXSB_VdqWdq
OP3_PMAXSD_VdqWdq
OP3_PMAXUD_VdqWdq
OP3_PMAXUW_VdqWdq
OP3_PMINSB_VdqWdq
OP3_PMINSD_VdqWdq
OP3_PMINUD_VdqWdq
OP3_PMINUW_VdqWdq
OP3_PMULLD_VdqWdq
OP3_PSHUFB_VdqWdq
OP3_PTEST_VdqWdq
OP3_ROUNDPD_MbVdqIb
OP3_ROUNDPD_VpdWpdIb
OP3_ROUNDPS_VpsWpsIb
OP3_ROUNDSD_VsdWsdIb
OP3_ROUNDSS_VssWssIb
OP3_SFENCE
OP3_VBROADCASTSS_VxWd
OP3_VPACKUSDW_VxHxWx
OP3_VPBLENDW_VxHxWxIb
OP3_VPMOVSXBW_VxUx
OP3_VPMOVSXDQ_VxUx
OP3_VPMOVSXWD_VxUx
OP3_VPMOVZXBW_VxUx
OP3_VPMOVZXDQ_VxUx
OP3_VPMOVZXWD_VxUx
OP_2BYTE_ESCAPE
OP_ADD_EAXIv
OP_ADD_EbGb
OP_ADD_EvGv
OP_ADD_GvEv
OP_AND_EvGb
OP_AND_EvGv
OP_AND_GvEv
OP_CALL_rel32
OP_CDQ
OP_CMP_EAXIv
OP_CMP_EvGv
OP_CMP_GvEv
OP_ESCAPE_D9
OP_ESCAPE_DD
OP_GROUP1A_Ev
OP_GROUP1_EbIb
OP_GROUP1_EvIb
OP_GROUP1_EvIz
OP_GROUP2_Ev1
OP_GROUP2_EvCL
OP_GROUP2_EvIb
OP_GROUP3_Eb
OP_GROUP3_EbIb
OP_GROUP3_Ev
OP_GROUP3_EvIz
OP_GROUP5_Ev
OP_GROUP11_EvIb
OP_GROUP11_EvIz
OP_HLT
OP_IMUL_GvEvIz
OP_INT3
OP_JMP_rel32
OP_LEA
OP_MOVSXD_GvEv
OP_MOV_EAXIv
OP_MOV_EAXOv
OP_MOV_EbGb
OP_MOV_EvGv
OP_MOV_GvEv
OP_MOV_OvEAX
OP_NOP
OP_OR_EAXIv
OP_OR_EvGb
OP_OR_EvGv
OP_OR_GvEv
OP_PAUSE
OP_POP_EAX
OP_PUSH_EAX
OP_PUSH_Iz
OP_RET
OP_SETCC
OP_SUB_EAXIv
OP_SUB_EvGb
OP_SUB_EvGv
OP_SUB_GvEv
OP_TEST_ALIb
OP_TEST_EAXIv
OP_TEST_EbGb
OP_TEST_EvGv
OP_XCHG_EAX
OP_XCHG_EvGb
OP_XCHG_EvGv
OP_XOR_EAXIv
OP_XOR_EvGb
OP_XOR_EvGv
OP_XOR_GvEv
PRE_GS
PRE_LOCK
PRE_OPERAND_SIZE
PRE_PREDICT_BRANCH_NOT_TAKEN
PRE_REX
PRE_SSE_00
PRE_SSE_66
PRE_SSE_F2
PRE_SSE_F3
eax
ebp
ebx
ecx
edi
edx
eflags
eip
esi
esp
r8
r9
r10
r11
r12
r13
r14
r15
xmm0
xmm1
xmm2
xmm3
xmm4
xmm5
xmm6
xmm7
xmm8
xmm9
xmm10
xmm11
xmm12
xmm13
xmm14
xmm15

Functions§

cmovcc
jcc_rel32
setcc_opcode
vex_encoded_simd_prefix