luaur_code_gen/methods/
assembly_builder_x_64_vroundps.rs

1use crate::enums::rounding_mode_x_64::RoundingModeX64;
2use crate::records::assembly_builder_x_64::AssemblyBuilderX64;
3use crate::records::operand_x_64::OperandX64;
4
5impl AssemblyBuilderX64 {
6    pub fn vroundps(&mut self, dst: OperandX64, src: OperandX64, rounding_mode: RoundingModeX64) {
7        // 'placeAvx' wrapper doesn't have an overload for this archetype (opcode r/m, reg, imm8)
8        if self.log_text {
9            // C++: log("vroundps", dst, src, uint8_t(roundingMode) | kRoundingPrecisionInexact)
10            self.log_c_char_operand_x_64_operand_x_64_operand_x_64(
11                b"vroundps\0".as_ptr() as *const core::ffi::c_char,
12                dst,
13                src,
14                OperandX64::from((rounding_mode as u8 | 0x08) as i32),
15            );
16        }
17
18        // C++: placeVex(dst, noreg, src, false, AVX_0F3A, AVX_66); place(0x08);
19        //      placeRegAndModRegMem(dst, src, 1);
20        //      placeImm8(roundingMode | kRoundingPrecisionInexact);
21        // mode is AVX_0F3A (0x3A -> 0b00011), and the imm8 precision flag is
22        // kRoundingPrecisionInexact (0b1000 = 0x08), not 0x04.
23        self.place_vex(
24            dst,
25            OperandX64::reg(crate::records::register_x_64::RegisterX64::noreg),
26            src,
27            false,
28            0x3A,
29            0x66,
30        );
31        self.place(0x08);
32        self.place_reg_and_mod_reg_mem(dst, src, 1);
33        self.place_imm_8((rounding_mode as u8 | 0x08) as i32);
34
35        self.commit();
36    }
37}
luaur_code_gen/methods/assembly_builder_x_64_vroundps.rs

luaur_code_gen/methods/
assembly_builder_x_64_vroundps.rs
