luaur_code_gen/methods/
assembly_builder_x_64_mov.rs

1use crate::enums::category_x_64::CategoryX64;
2use crate::enums::size_x_64::SizeX64;
3use crate::macros::op_plus_reg::OP_PLUS_REG;
4use crate::records::assembly_builder_x_64::AssemblyBuilderX64;
5use crate::records::operand_x_64::OperandX64;
6use crate::records::register_x_64::RegisterX64;
7
8impl AssemblyBuilderX64 {
9    pub fn mov(&mut self, lhs: OperandX64, rhs: OperandX64) {
10        if self.log_text {
11            self.log_c_char_operand_x_64_operand_x_64(c"mov".as_ptr(), lhs, rhs);
12        }
13
14        if lhs.cat == CategoryX64::reg && rhs.cat == CategoryX64::imm {
15            let size = lhs.base.size();
16
17            self.place_rex_register_x_64(lhs.base);
18
19            if size == SizeX64::byte {
20                self.place(OP_PLUS_REG(0xb0, lhs.base.index()));
21                self.place_imm_8(rhs.imm);
22            } else if size == SizeX64::word {
23                self.place(0x66);
24                self.place(OP_PLUS_REG(0xb8, lhs.base.index()));
25                self.place_imm_16(rhs.imm as i16);
26            } else if size == SizeX64::dword {
27                self.place(OP_PLUS_REG(0xb8, lhs.base.index()));
28                self.place_imm_32(rhs.imm);
29            } else {
30                // qword
31                self.place(OP_PLUS_REG(0xb8, lhs.base.index()));
32                self.place_imm_64(rhs.imm as i64);
33            }
34        } else if lhs.cat == CategoryX64::mem && rhs.cat == CategoryX64::imm {
35            let size = lhs.memSize;
36
37            self.place_rex_operand_x_64(lhs);
38
39            if size == SizeX64::byte {
40                self.place(0xc6);
41                self.place_mod_reg_mem(lhs, 0, 1);
42                self.place_imm_8(rhs.imm);
43            } else if size == SizeX64::word {
44                self.place(0x66);
45                self.place(0xc7);
46                self.place_mod_reg_mem(lhs, 0, 2);
47                self.place_imm_16(rhs.imm as i16);
48            } else {
49                // dword or qword: both encoded with imm32 in this routine
50                self.place(0xc7);
51                self.place_mod_reg_mem(lhs, 0, 4);
52                self.place_imm_32(rhs.imm);
53            }
54        } else if lhs.cat == CategoryX64::reg
55            && (rhs.cat == CategoryX64::reg || rhs.cat == CategoryX64::mem)
56        {
57            self.place_binary_reg_and_reg_mem(lhs, rhs, 0x8a, 0x8b);
58        } else if lhs.cat == CategoryX64::mem && rhs.cat == CategoryX64::reg {
59            self.place_binary_reg_mem_and_reg(lhs, rhs, 0x88, 0x89);
60        } else {
61            luaur_common::LUAU_DEBUGBREAK!();
62        }
63
64        self.commit();
65    }
66}
luaur_code_gen/methods/assembly_builder_x_64_mov.rs

luaur_code_gen/methods/
assembly_builder_x_64_mov.rs
