luaur_code_gen/functions/
emit_builtin_math_frexp.rs

1use crate::enums::size_x_64::SizeX64;
2use crate::functions::luau_reg_tag::luau_reg_tag;
3use crate::functions::luau_reg_value::luau_reg_value;
4use crate::records::assembly_builder_x_64::AssemblyBuilderX64;
5use crate::records::ir_call_wrapper_x_64::IrCallWrapperX64;
6use crate::records::ir_data::k_invalid_inst_idx;
7use crate::records::ir_op::IrOp;
8use crate::records::ir_reg_alloc_x_64::IrRegAllocX64;
9use crate::records::native_context::NativeContext;
10use crate::records::operand_x_64::OperandX64;
11use crate::records::register_x_64::RegisterX64;
12use luaur_vm::enums::lua_type::lua_Type;
13
14const fn reg(index: u8, size: SizeX64) -> RegisterX64 {
15    RegisterX64 {
16        bits: (index << RegisterX64::INDEX_SHIFT) | size as u8,
17    }
18}
19
20const R_NATIVE_CONTEXT: RegisterX64 = reg(13, SizeX64::qword);
21const XMM0: RegisterX64 = reg(0, SizeX64::xmmword);
22
23fn s_temporary_slot() -> OperandX64 {
24    OperandX64::mem(SizeX64::qword, RegisterX64::noreg, 1, RegisterX64::rsp, 0)
25}
26
27pub fn emit_builtin_math_frexp(
28    regs: &mut IrRegAllocX64,
29    build: &mut AssemblyBuilderX64,
30    ra: i32,
31    arg: i32,
32    nresults: i32,
33) {
34    let mut call_wrap = IrCallWrapperX64::ir_call_wrapper_x_64_ir_call_wrapper_x_64(
35        regs,
36        build,
37        k_invalid_inst_idx,
38    );
39    call_wrap.add_argument_size_x_64_operand_x_64_ir_op(
40        SizeX64::xmmword,
41        luau_reg_value(arg),
42        IrOp::ir_op(),
43    );
44    call_wrap.add_argument_size_x_64_operand_x_64_ir_op(
45        SizeX64::qword,
46        s_temporary_slot(),
47        IrOp::ir_op(),
48    );
49    call_wrap.call(&OperandX64::mem(
50        SizeX64::qword,
51        RegisterX64::noreg,
52        1,
53        R_NATIVE_CONTEXT,
54        core::mem::offset_of!(NativeContext, libm_frexp) as i32,
55    ));
56
57    build.vmovsd_operand_x_64_operand_x_64(luau_reg_value(ra), OperandX64::reg(XMM0));
58    build.mov(
59        luau_reg_tag(ra),
60        OperandX64::imm(lua_Type::LUA_TNUMBER as i32),
61    );
62
63    if nresults > 1 {
64        build.vcvtsi2sd(
65            OperandX64::reg(XMM0),
66            OperandX64::reg(XMM0),
67            OperandX64::mem(SizeX64::dword, RegisterX64::noreg, 1, RegisterX64::rsp, 0),
68        );
69        build.vmovsd_operand_x_64_operand_x_64(luau_reg_value(ra + 1), OperandX64::reg(XMM0));
70        build.mov(
71            luau_reg_tag(ra + 1),
72            OperandX64::imm(lua_Type::LUA_TNUMBER as i32),
73        );
74    }
75}
luaur_code_gen/functions/emit_builtin_math_frexp.rs

luaur_code_gen/functions/
emit_builtin_math_frexp.rs
