lps22hh_rs/register/
main.rs

1use super::super::{
2    BusOperation, Error, Lps22hh, RegisterOperation, SensorOperation, bisync, register::OnState,
3};
4
5use bitfield_struct::bitfield;
6use derive_more::TryFrom;
7
8use st_mem_bank_macro::register;
9
10/// Register addresses for LPS22HH sensor
11///
12/// This enum represents the 8-bit register addresses embedded in the device.
13/// Registers marked as Reserved must not be changed to avoid permanent damage.
14/// The content of registers loaded at boot contains factory calibration values and should not be changed.
15#[repr(u8)]
16#[derive(Clone, Copy)]
17pub enum Reg {
18    /// Interrupt configuration register
19    InterruptCfg = 0x0B,
20    /// Pressure threshold low register (least significant bits)
21    ThsPL = 0x0C,
22    /// Pressure threshold high register (most significant bits)
23    ThsPH = 0x0D,
24    /// Interface control register
25    IfCtrl = 0x0E,
26    /// Device identification register
27    WhoAmI = 0x0F,
28    /// Control register 1
29    CtrlReg1 = 0x10,
30    /// Control register 2
31    CtrlReg2 = 0x11,
32    /// Control register 3
33    CtrlReg3 = 0x12,
34    /// FIFO control register
35    FifoCtrl = 0x13,
36    /// FIFO watermark level register
37    FifoWtm = 0x14,
38    /// Reference pressure low register
39    RefPL = 0x15,
40    /// Reference pressure high register
41    RefPH = 0x16,
42    /// Pressure offset low register
43    RpdsL = 0x18,
44    /// Pressure offset high register
45    RpdsH = 0x19,
46    /// Interrupt source register
47    IntSource = 0x24,
48    /// FIFO status register 1
49    FifoStatus1 = 0x25,
50    /// FIFO status register 2
51    FifoStatus2 = 0x26,
52    /// Status register
53    Status = 0x27,
54    /// Pressure output least significant byte
55    PressOutXl = 0x28,
56    /// Pressure output middle byte
57    PressOutL = 0x29,
58    /// Pressure output most significant byte
59    PressOutH = 0x2A,
60    /// Temperature output least significant byte
61    TempOutL = 0x2B,
62    /// Temperature output most significant byte
63    TempOutH = 0x2C,
64    /// FIFO pressure output least significant byte
65    FifoDataOutPressXl = 0x78,
66    /// FIFO pressure output middle byte
67    FifoDataOutPressL = 0x79,
68    /// FIFO pressure output most significant byte
69    FifoDataOutPressH = 0x7A,
70    /// FIFO temperature output least significant byte
71    FifoDataOutTempL = 0x7B,
72    /// FIFO temperature output most significant byte
73    FifoDataOutTempH = 0x7C,
74}
75
76/// INTERRUPT_CFG (0x0B)
77///
78/// Interrupt configuration register (R/W)
79///
80/// Configures interrupt generation based on pressure threshold events,
81/// autozero and autoreference reset and enable functions, and interrupt latching.
82#[register(address = Reg::InterruptCfg, access_type = "Lps22hh<B, OnState>")]
83#[cfg_attr(feature = "bit_order_msb", bitfield(u8, order = Msb))]
84#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u8, order = Lsb))]
85pub struct InterruptCfg {
86    /// Pressure event interrupt enable (2 bits)
87    /// 00: No threshold (interrupt disabled)
88    /// 01: Positive threshold event enabled
89    /// 10: Negative threshold event enabled
90    /// 11: Both positive and negative threshold events enabled
91    #[bits(2)]
92    pub pe: u8,
93    /// Latch interrupt request to INT_SOURCE register (1 bit)
94    /// 0: Interrupt request not latched (pulsed)
95    /// 1: Interrupt request latched
96    #[bits(1)]
97    pub lir: u8,
98    /// Differential pressure interrupt enable (1 bit)
99    /// 0: Interrupt generation disabled
100    /// 1: Interrupt generation enabled
101    #[bits(1)]
102    pub diff_en: u8,
103    /// Reset Autozero function (1 bit)
104    /// Writing 1 resets AUTOZERO and REF_P registers to 0
105    #[bits(1)]
106    pub reset_az: u8,
107    /// Enable Autozero function (1 bit)
108    /// When set, measured pressure is used as reference and stored in REF_P
109    /// AUTOZERO bit auto-clears after first conversion
110    #[bits(1)]
111    pub autozero: u8,
112    /// Reset AutoRefP function (1 bit)
113    /// Writing 1 resets AUTOREFP function
114    #[bits(1)]
115    pub reset_arp: u8,
116    /// Enable AutoRefP function (1 bit)
117    /// When set, differential pressure is used for interrupt generation without changing PRESS_OUT registers
118    #[bits(1)]
119    pub autorefp: u8,
120}
121
122/// THS_P_L - THS_P_H (0x0C - 0x0D)
123///
124/// User-defined threshold value for pressure interrupt event (R/W)
125///
126/// Contains the 15-bit threshold pressure value used for interrupt generation.
127/// Threshold value = Desired interrupt threshold (hPa) × 16
128#[register(address = Reg::ThsPL, access_type = "Lps22hh<B, OnState>")]
129#[cfg_attr(feature = "bit_order_msb", bitfield(u16, order = Msb))]
130#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u16, order = Lsb))]
131pub struct ThsP {
132    /// Threshold pressure low bits [7:0] (8 bits)
133    #[bits(15)]
134    pub ths: u16,
135    #[bits(1, access = RO)]
136    pub not_used_01: u8,
137}
138
139/// IF_CTRL (0x0E)
140///
141/// Interface control register (R/W)
142///
143/// Controls enabling/disabling of I2C and MIPI I3C interfaces, pull-up and pull-down resistors,
144/// and interrupt pin configuration.
145#[register(address = Reg::IfCtrl, access_type = "Lps22hh<B, OnState>")]
146#[cfg_attr(feature = "bit_order_msb", bitfield(u8, order = Msb))]
147#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u8, order = Lsb))]
148pub struct IfCtrl {
149    /// I2C interface disable (1 bit)
150    /// - 0: I2C enabled
151    /// - 1: I2C disabled
152    #[bits(1)]
153    pub i2c_disable: u8,
154    /// MIPI I3C interface disable (1 bit)
155    /// - 0: MIPI I3C enabled
156    /// - 1: MIPI I3C disabled
157    #[bits(1)]
158    pub i3c_disable: u8,
159    /// Pull-down disable on INT1 pin (1 bit)
160    /// - 0: INT1 pin with pull-down enabled
161    /// - 1: INT1 pin pull-down disabled
162    #[bits(1)]
163    pub pd_dis_int1: u8,
164    /// SDO pull-up enable (1 bit)
165    /// - 0: Pull-up disconnected
166    /// - 1: Pull-up connected
167    #[bits(1)]
168    pub sdo_pu_en: u8,
169    /// SDA pull-up enable (1 bit)
170    /// - 0: Pull-up disconnected
171    /// - 1: Pull-up connected
172    #[bits(1)]
173    pub sda_pu_en: u8,
174    #[bits(2, access = RO)]
175    pub not_used_01: u8,
176    /// Interrupt enable on INT1 pin for MIPI I3C (1 bit)
177    /// - 0: INT1 disabled with MIPI I3C
178    /// - 1: INT1 enabled with MIPI I3C
179    #[bits(1)]
180    pub int_en_i3c: u8,
181}
182
183/// WHO_AM_I (0x0F)
184///
185/// The identification register is used to identity the device (R)
186#[register(address = Reg::WhoAmI, access_type = "Lps22hh<B, OnState>")]
187#[cfg_attr(feature = "bit_order_msb", bitfield(u8, order = Msb))]
188#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u8, order = Lsb))]
189pub struct WhoAmI {
190    #[bits(8, access = RO)]
191    pub who_am_i: u8,
192}
193
194/// CTRL_REG1 (0x10)
195///
196/// Control register 1 (R/W)
197///
198/// Controls output data rate, low-pass filter, block data update, and SPI interface mode.
199#[register(address = Reg::CtrlReg1, access_type = "Lps22hh<B, OnState>")]
200#[cfg_attr(feature = "bit_order_msb", bitfield(u8, order = Msb))]
201#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u8, order = Lsb))]
202pub struct CtrlReg1 {
203    /// SPI Serial Interface Mode selection (1 bit)
204    /// - 0: 4-wire SPI interface
205    /// - 1: 3-wire SPI interface
206    #[bits(1)]
207    pub sim: u8,
208    /// Block Data Update (1 bit)
209    /// - 0: Continuous update of output registers
210    /// - 1: Output registers not updated until MSB and LSB are read
211    #[bits(1)]
212    pub bdu: u8,
213    /// Low-pass filter configuration (2 bits)
214    /// - 00: Disabled (bandwidth = ODR/2)
215    /// - 01: Enabled (bandwidth = ODR/9)
216    /// - 10: Enabled (bandwidth = ODR/20)
217    #[bits(2)]
218    pub lpfp_cfg: u8,
219    /// Output data rate selection (3 bits)
220    /// - 000: Power-down mode
221    /// - 001: 3 Hz
222    /// - 010: 10 Hz
223    /// - 011: 25 Hz
224    /// - 100: 50 Hz
225    /// - 101: 75 Hz
226    /// - 110: 100 Hz (low-noise mode disabled automatically)
227    /// - 111: 200 Hz (low-noise mode disabled automatically)
228    #[bits(3)]
229    pub odr: u8,
230    #[bits(1, access = RO)]
231    pub not_used_01: u8,
232}
233/// CTRL_REG2 (0x11)
234///
235/// Control register 2 (R/W)
236///
237/// Controls one-shot mode, low noise mode, software reset, address auto-increment,
238/// interrupt pin configuration, and reboot memory content.
239#[register(address = Reg::CtrlReg2, access_type = "Lps22hh<B, OnState>")]
240#[cfg_attr(feature = "bit_order_msb", bitfield(u8, order = Msb))]
241#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u8, order = Lsb))]
242pub struct CtrlReg2 {
243    /// One-shot mode enable (1 bit)
244    /// - 0: Idle mode
245    /// - 1: Triggers a single acquisition when device is in power-down mode
246    #[bits(1)]
247    pub one_shot: u8,
248    /// Low noise enable (1 bit)
249    /// - 0: Low current mode
250    /// - 1: Low noise mode (only valid if ODR < 100 Hz)
251    #[bits(1)]
252    pub low_noise_en: u8,
253    /// Software reset (1 bit)
254    /// Writing 1 resets volatile registers to default values; bit self-clears after reset
255    #[bits(1)]
256    pub swreset: u8,
257    #[bits(1, access = RO)]
258    pub not_used_01: u8,
259    /// Register address auto-increment (1 bit)
260    /// - 0: Disabled
261    /// - 1: Enabled (default)
262    #[bits(1)]
263    pub if_add_inc: u8,
264    /// Push-pull/open-drain selection on interrupt pads (1 bit)
265    /// - 0: Push-pull
266    /// - 1: Open-drain
267    #[bits(1)]
268    pub pp_od: u8,
269    /// Interrupt active level (1 bit)
270    /// - 0: Active high
271    /// - 1: Active low
272    #[bits(1)]
273    pub int_h_l: u8,
274    /// Reboot memory content (1 bit)
275    /// Writing 1 reloads calibration parameters from internal flash; bit auto-clears
276    #[bits(1)]
277    pub boot: u8,
278}
279
280/// CTRL_REG3 (0x12)
281///
282/// Control register 3 - INT_DRDY pin control register (R/W)
283///
284/// Controls interrupt signals routed to the INT_DRDY pin.
285#[register(address = Reg::CtrlReg3, access_type = "Lps22hh<B, OnState>")]
286#[cfg_attr(feature = "bit_order_msb", bitfield(u8, order = Msb))]
287#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u8, order = Lsb))]
288pub struct CtrlReg3 {
289    /// Data signal on INT_DRDY pin control bits (2 bits)
290    /// - 00: Data signal (priority: DRDY or FIFO watermark or FIFO overrun or FIFO full)
291    /// - 01: Pressure high event
292    /// - 10: Pressure low event
293    /// - 11: Pressure low OR high event
294    #[bits(2)]
295    pub int_s: u8,
296    /// Data-ready signal on INT_DRDY pin (1 bit)
297    /// - 0: Disabled
298    /// - 1: Enabled
299    #[bits(1)]
300    pub drdy: u8,
301    /// FIFO overrun interrupt on INT_DRDY pin (1 bit)
302    /// - 0: Disabled
303    /// - 1: Enabled
304    #[bits(1)]
305    pub int_f_ovr: u8,
306    /// FIFO watermark status on INT_DRDY pin (1 bit)
307    /// - 0: Disabled
308    /// - 1: Enabled
309    #[bits(1)]
310    pub int_f_wtm: u8,
311    /// FIFO full flag on INT_DRDY pin (1 bit)
312    /// - 0: Disabled
313    /// - 1: Enabled
314    #[bits(1)]
315    pub int_f_full: u8,
316    #[bits(2, access = RO)]
317    pub not_used_01: u8,
318}
319
320/// FIFO_CTRL (0x13)
321///
322/// FIFO control register (R/W)
323///
324/// Controls FIFO mode selection and watermark stop behavior.
325#[register(address = Reg::FifoCtrl, access_type = "Lps22hh<B, OnState>")]
326#[cfg_attr(feature = "bit_order_msb", bitfield(u8, order = Msb))]
327#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u8, order = Lsb))]
328pub struct FifoCtrl {
329    /// FIFO mode selection (3 bits)
330    /// - 000: Bypass mode
331    /// - 001: FIFO mode
332    /// - 01x: Continuous (Dynamic-Stream) mode
333    /// - 101: Bypass-to-FIFO mode
334    /// - 110: Bypass-to-Continuous (Dynamic-Stream) mode
335    /// - 111: Continuous (Dynamic-Stream)-to-FIFO mode
336    #[bits(3)]
337    pub f_mode: u8,
338    /// Stop on FIFO watermark (1 bit)
339    /// - 0: Disabled
340    /// - 1: Enabled (FIFO depth limited to watermark level)
341    #[bits(1)]
342    pub stop_on_wtm: u8,
343    #[bits(4, access = RO)]
344    pub not_used_01: u8,
345}
346
347/// FIFO_WTM (0x14)
348///
349/// FIFO watermark setting register (R/W)
350///
351/// Sets the FIFO watermark level for interrupt generation.
352#[register(address = Reg::FifoWtm, access_type = "Lps22hh<B, OnState>")]
353#[cfg_attr(feature = "bit_order_msb", bitfield(u8, order = Msb))]
354#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u8, order = Lsb))]
355pub struct FifoWtm {
356    /// FIFO watermark level (7 bits)
357    #[bits(7)]
358    pub wtm: u8,
359    #[bits(1, access = RO)]
360    pub not_used_01: u8,
361}
362
363/// REF_P_L - REF_P_H (0x15 - 0x16)
364///
365/// Reference pressure registers (R/W)
366///
367/// Contains the 16-bit (expressed in 2's complement) reference pressure value used in AUTOZERO or AUTOREFP modes.
368#[register(address = Reg::RefPL, access_type = "Lps22hh<B, OnState>")]
369#[cfg_attr(feature = "bit_order_msb", bitfield(u16, order = Msb))]
370#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u16, order = Lsb))]
371pub struct RefP {
372    /// Reference pressure
373    #[bits(16)]
374    pub ref_p: i16,
375}
376
377/// RPDS_L - RPDS_H (0x18 - 0x19)
378///
379/// Pressure offset low and high register (R/W)
380///
381/// Contains the 16-bit (2's complement) pressure offset value used for one-point calibration (OPC).
382#[register(address = Reg::RpdsL, access_type = "Lps22hh<B, OnState>")]
383#[cfg_attr(feature = "bit_order_msb", bitfield(u16, order = Msb))]
384#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u16, order = Lsb))]
385pub struct Rpds {
386    /// Pressure offset (16 bits)
387    #[bits(16)]
388    pub rpds: i16,
389}
390
391/// INT_SOURCE (0x24)
392///
393/// Interrupt source register (R)
394#[register(address = Reg::IntSource, access_type = "Lps22hh<B, OnState>")]
395#[cfg_attr(feature = "bit_order_msb", bitfield(u8, order = Msb))]
396#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u8, order = Lsb))]
397pub struct IntSource {
398    /// Differential pressure high event flag (1 bit)
399    #[bits(1)]
400    pub ph: u8,
401    /// Differential pressure low event flag (1 bit)
402    #[bits(1)]
403    pub pl: u8,
404    /// Interrupt active flag (1 bit)
405    #[bits(1)]
406    pub ia: u8,
407    #[bits(4, access = RO)]
408    pub not_used_01: u8,
409    /// Boot phase indicator (1 bit)
410    #[bits(1)]
411    pub boot_on: u8,
412}
413
414/// FIFO_STATUS1 - FIFO_STATUS2 (0x25 - 0x26)
415///
416/// FIFO status register 1 (R)
417#[register(address = Reg::FifoStatus1, access_type = "Lps22hh<B, OnState>")]
418#[cfg_attr(feature = "bit_order_msb", bitfield(u16, order = Msb))]
419#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u16, order = Lsb))]
420pub struct FifoStatusReg {
421    /// FIFO stored data level, number of unread samples stored in FIFO (8 bits)
422    #[bits(8)]
423    pub fss: u8,
424    #[bits(5, access = RO)]
425    pub not_used_01: u8,
426    /// FIFO full interrupt active flag (1 bit)
427    #[bits(1)]
428    pub fifo_full_ia: u8,
429    /// FIFO overrun interrupt active flag (1 bit)
430    #[bits(1)]
431    pub fifo_ovr_ia: u8,
432    /// FIFO watermark interrupt active flag (1 bit)
433    #[bits(1)]
434    pub fifo_wtm_ia: u8,
435}
436
437impl From<FifoStatusReg> for FifoStatus1 {
438    fn from(value: FifoStatusReg) -> Self {
439        let bytes = value.into_bits().to_le_bytes();
440        Self::from_bits(bytes[0])
441    }
442}
443
444impl From<FifoStatusReg> for FifoStatus2 {
445    fn from(value: FifoStatusReg) -> Self {
446        let bytes = value.into_bits().to_le_bytes();
447        Self::from_bits(bytes[1])
448    }
449}
450
451/// FIFO_STATUS1 (0x25)
452///
453/// FIFO status register 1 (R)
454#[cfg_attr(feature = "bit_order_msb", bitfield(u8, order = Msb))]
455#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u8, order = Lsb))]
456pub struct FifoStatus1 {
457    /// FIFO stored data level, number of unread samples stored in FIFO (8 bits)
458    #[bits(8)]
459    pub fss: u8,
460}
461
462/// FIFO_STATUS2 (0x26)
463///
464/// FIFO status register 2 (R)
465#[cfg_attr(feature = "bit_order_msb", bitfield(u8, order = Msb))]
466#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u8, order = Lsb))]
467pub struct FifoStatus2 {
468    #[bits(5, access = RO)]
469    pub not_used_01: u8,
470    /// FIFO full interrupt active flag (1 bit)
471    #[bits(1)]
472    pub fifo_full_ia: u8,
473    /// FIFO overrun interrupt active flag (1 bit)
474    #[bits(1)]
475    pub fifo_ovr_ia: u8,
476    /// FIFO watermark interrupt active flag (1 bit)
477    #[bits(1)]
478    pub fifo_wtm_ia: u8,
479}
480
481/// STATUS (0x27)
482///
483/// Status register (R)
484#[register(address = Reg::Status, access_type = "Lps22hh<B, OnState>")]
485#[cfg_attr(feature = "bit_order_msb", bitfield(u8, order = Msb))]
486#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u8, order = Lsb))]
487pub struct Status {
488    /// Pressure data available flag (1 bit)
489    #[bits(1)]
490    pub p_da: u8,
491    /// Temperature data available flag (1 bit)
492    #[bits(1)]
493    pub t_da: u8,
494    #[bits(2, access = RO)]
495    pub not_used_01: u8,
496    /// Pressure data overrun flag (1 bit)
497    #[bits(1)]
498    pub p_or: u8,
499    /// Temperature data overrun flag (1 bit)
500    #[bits(1)]
501    pub t_or: u8,
502    #[bits(2, access = RO)]
503    pub not_used_02: u8,
504}
505
506/// PRESS_OUT_XL - PRESS_OUT_L - PRESS_OUT_H (0x28 - 0x2A)
507///
508/// Pressure output value (R)
509#[register(address = Reg::PressOutXl, access_type = "Lps22hh<B, OnState>")]
510#[cfg_attr(feature = "bit_order_msb", bitfield(u32, order = Msb))]
511#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u32, order = Lsb))]
512pub struct PressOut {
513    #[offset_before(8)]
514    /// Pressure output (3 byte)
515    #[bits(32)]
516    pub pressure: u32,
517}
518
519/// TempOut (0x2B - 0x2C)
520///
521/// Temperature register of the sensor in 2's complement format
522#[register(address = Reg::TempOutL, access_type = "Lps22hh<B, OnState>")]
523#[cfg_attr(feature = "bit_order_msb", bitfield(u16, order = Msb))]
524#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u16, order = Lsb))]
525pub struct TempOut {
526    /// Temperature output
527    #[bits(16)]
528    pub temperature: i16,
529}
530
531/// FIFO_DATA_OUT_PRESS_XL - FIFO_DATA_OUT_PRESS_L - FIFO_DATA_OUT_PRESS_H (0x78 - 0x7A)
532///
533/// FIFO pressure output (3 byte) (R)
534#[register(address = Reg::FifoDataOutPressXl, access_type = "Lps22hh<B, OnState>")]
535#[cfg_attr(feature = "bit_order_msb", bitfield(u32, order = Msb))]
536#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u32, order = Lsb))]
537pub struct FifoDataOutPress {
538    #[offset_before(8)]
539    /// FIFO pressure output (24 bits)
540    #[bits(32)]
541    pub pressure: u32,
542}
543
544/// FIFO_DATA_OUT_TEMP_L - FIFO_DATA_OUT_TEMP_H (0x7B - 0x7C)
545///
546/// FIFO temperature output two's complement 16 bit format(R)
547#[register(address = Reg::FifoDataOutTempL, access_type = "Lps22hh<B, OnState>")]
548#[cfg_attr(feature = "bit_order_msb", bitfield(u16, order = Msb))]
549#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u16, order = Lsb))]
550pub struct FifoDataOutTemp {
551    /// FIFO temperature output (16 bits)
552    #[bits(16)]
553    pub temperature: i16,
554}
555
556/// Output data rate (ODR) settings for LPS22HH sensor
557///
558/// Controls the frequency of pressure and temperature data acquisition.
559/// When set to '000', device is in Power-down mode.
560/// Other values correspond to continuous acquisition at specified Hz.
561///
562/// The device is in Power-down mode when ODR bits are set to '000'.
563/// Continuous mode acquires data at frequencies from 1 Hz to 200 Hz.
564/// Low-noise mode is enabled only if ODR < 100 Hz and LOW_NOISE_EN bit is set.
565/// ODR 100 Hz and 200 Hz disable low-noise mode automatically.
566#[repr(u8)]
567#[derive(Clone, Copy, Default, TryFrom)]
568#[try_from(repr)]
569pub enum Odr {
570    /// Power-down mode, no continuous data acquisition.
571    #[default]
572    PowerDown = 0x00,
573    /// One-shot mode triggers a single acquisition.
574    OneShoot = 0x08,
575    /// 1 Hz output data rate.
576    _1hz = 0x01,
577    /// 10 Hz output data rate.
578    _10hz = 0x02,
579    /// 25 Hz output data rate.
580    _25hz = 0x03,
581    /// 50 Hz output data rate.
582    _50hz = 0x04,
583    /// 75 Hz output data rate.
584    _75hz = 0x05,
585    /// 1 Hz output data rate with low-noise mode enabled.
586    _1hzLowNoise = 0x11,
587    /// 10 Hz output data rate with low-noise mode enabled.
588    _10hzLowNoise = 0x12,
589    /// 25 Hz output data rate with low-noise mode enabled.
590    _25hzLowNoise = 0x13,
591    /// 50 Hz output data rate with low-noise mode enabled.
592    _50hzLowNoise = 0x14,
593    /// 75 Hz output data rate with low-noise mode enabled.
594    _75hzLowNoise = 0x15,
595    /// 100 Hz output data rate (low-noise mode disabled automatically).
596    _100hz = 0x06,
597    /// 200 Hz output data rate (low-noise mode disabled automatically).
598    _200hz = 0x07,
599}
600
601/// Low-pass filter configurations for LPS22HH sensor
602///
603/// Controls additional low-pass filter status and device bandwidth.
604/// - 0: Disabled, bandwidth = ODR/2
605/// - 1: Enabled, bandwidth = ODR/9
606/// - 2: Enabled, bandwidth = ODR/20
607#[repr(u8)]
608#[derive(Clone, Copy, Default, TryFrom)]
609#[try_from(repr)]
610pub enum LpfpCfg {
611    /// Low-pass filter disabled; device bandwidth = ODR/2
612    #[default]
613    OdrDiv2 = 0,
614    /// Low-pass filter enabled; device bandwidth = ODR/9
615    OdrDiv9 = 1,
616    /// Low-pass filter enabled; device bandwidth = ODR/20
617    OdrDiv20 = 2,
618}
619
620/// I2C interface enable/disable for LPS22HH sensor
621///
622/// Controls whether the I2C interface is enabled or disabled.
623/// - 0: I2C enabled
624/// - 1: I2C disabled
625#[repr(u8)]
626#[derive(Clone, Copy, Default, TryFrom)]
627#[try_from(repr)]
628pub enum I2cMode {
629    /// I2C interface enabled
630    #[default]
631    Enable = 0,
632    /// I2C interface disabled
633    Disable = 1,
634}
635
636/// MIPI I3C interface enable/disable for LPS22HH sensor
637///
638/// Controls MIPI I3C communication protocol and interrupt pin.
639/// - 0x00: I3C enabled, interrupt pin disabled
640/// - 0x10: I3C enabled, interrupt pin enabled
641/// - 0x11: I3C disabled
642#[repr(u8)]
643#[derive(Clone, Copy, Default, TryFrom)]
644#[try_from(repr)]
645pub enum I3cMode {
646    /// I3C enabled, interrupt pin disabled
647    #[default]
648    Enable = 0x00,
649    /// I3C enabled, interrupt pin enabled
650    EnableIntPinEnable = 0x10,
651    /// I3C disabled
652    Disable = 0x11,
653}
654
655/// Pull-up enable for SDO or SDA pins on LPS22HH sensor
656///
657/// Controls connection of internal pull-up resistors.
658/// - 0: Pull-up disconnected
659/// - 1: Pull-up connected
660#[repr(u8)]
661#[derive(Clone, Copy, Default, TryFrom)]
662#[try_from(repr)]
663pub enum PullUp {
664    /// Pull-up disconnected
665    #[default]
666    Disconnect = 0,
667    /// Pull-up connected
668    Connect = 1,
669}
670
671/// SPI interface mode selection for LPS22HH sensor
672///
673/// Selects between 4-wire and 3-wire SPI interface modes.
674/// - 0: 4-wire SPI interface
675/// - 1: 3-wire SPI interface
676#[repr(u8)]
677#[derive(Clone, Copy, Default, TryFrom)]
678#[try_from(repr)]
679pub enum Sim {
680    /// 4-wire SPI interface mode
681    #[default]
682    Spi4Wire = 0,
683    /// 3-wire SPI interface mode
684    Spi3Wire = 1,
685}
686
687/// Interrupt request latch mode for LPS22HH sensor
688///
689/// Controls whether interrupt requests are pulsed or latched.
690/// - 0: Interrupt request not latched (pulsed)
691/// - 1: Interrupt request latched
692#[repr(u8)]
693#[derive(Clone, Copy, Default, TryFrom)]
694#[try_from(repr)]
695pub enum Lir {
696    /// Interrupt request pulsed
697    #[default]
698    Pulsed = 0,
699    /// Interrupt request latched
700    Latched = 1,
701}
702
703/// Interrupt pin output mode for LPS22HH sensor
704///
705/// Controls push-pull or open-drain configuration on interrupt pads.
706/// - 0: Push-pull
707/// - 1: Open-drain
708#[repr(u8)]
709#[derive(Clone, Copy, Default, TryFrom)]
710#[try_from(repr)]
711pub enum PpOd {
712    /// Push-pull output mode
713    #[default]
714    PushPull = 0,
715    /// Open-drain output mode
716    OpenDrain = 1,
717}
718
719/// Interrupt active level for LPS22HH sensor
720///
721/// Controls whether interrupt is active-high or active-low.
722/// - 0: Active high
723/// - 1: Active low
724#[repr(u8)]
725#[derive(Clone, Copy, Default, TryFrom)]
726#[try_from(repr)]
727pub enum IntHL {
728    /// Interrupt active high
729    #[default]
730    ActiveHigh = 0,
731    /// Interrupt active low
732    ActiveLow = 1,
733}
734
735/// Pressure event interrupt enable for LPS22HH sensor
736///
737/// Controls interrupt generation on pressure threshold events.
738/// - 0: No threshold (interrupt disabled)
739/// - 1: Positive threshold event enabled
740/// - 2: Negative threshold event enabled
741/// - 3: Both positive and negative threshold events enabled
742#[repr(u8)]
743#[derive(Clone, Copy, Default, TryFrom)]
744#[try_from(repr)]
745pub enum Pe {
746    /// No threshold interrupt (interrupt disabled)
747    #[default]
748    NoThreshold = 0,
749    /// Interrupt on positive pressure threshold event
750    Positive = 1,
751    /// Interrupt on negative pressure threshold event
752    Negative = 2,
753    /// Interrupt on both positive and negative pressure threshold events
754    Both = 3,
755}
756
757/// FIFO mode selection for LPS22HH sensor FIFO buffer operation
758///
759/// The FIFO buffer can work according to six different modes:
760/// - 0: Bypass mode (FIFO not operational, remains empty)
761/// - 1: FIFO mode (data stored until FIFO full)
762/// - 2,3: Continuous (Dynamic-Stream) mode (streaming data)
763/// - 5: Bypass-to-FIFO mode (switches on interrupt)
764/// - 6: Bypass-to-Continuous (Dynamic-Stream) mode (switches on interrupt)
765/// - 7: Continuous (Dynamic-Stream)-to-FIFO mode (switches on interrupt)
766#[repr(u8)]
767#[derive(Clone, Copy, Default, TryFrom)]
768#[try_from(repr)]
769pub enum FMode {
770    /// Bypass mode: FIFO is not operational and remains empty.
771    #[default]
772    BypassMode = 0,
773    /// FIFO mode: Data stored in FIFO until full.
774    FifoMode = 1,
775    /// Continuous (Dynamic-Stream) mode: FIFO behaves as a stream buffer.
776    StreamMode = 2,
777    /// Continuous (Dynamic-Stream) mode: alternate encoding.
778    DynamicStreamMode = 3,
779    /// Bypass-to-FIFO mode: FIFO switches from Bypass to FIFO mode on interrupt.
780    BypassToFifoMode = 5,
781    /// Bypass-to-Continuous (Dynamic-Stream) mode: FIFO switches from Bypass to Continuous mode on interrupt.
782    BypassToStreamMode = 6,
783    /// Continuous (Dynamic-Stream)-to-FIFO mode: FIFO switches from Continuous to FIFO mode on interrupt.
784    StreamToFifoMode = 7,
785}
786
787#[derive(Default)]
788pub struct PinIntRoute {
789    pub drdy_pres: bool,
790    pub fifo_th: bool,
791    pub fifo_ovr: bool,
792    pub fifo_full: bool,
793}
lps22hh_rs/register/main.rs

lps22hh_rs/register/
main.rs
