1use super::{
2 BusOperation, I2c, RegisterOperation, SensorOperation, SevenBitAddress, SpiDevice, bisync, i2c,
3 prelude::*, spi,
4};
5
6use core::fmt::Debug;
7use core::marker::PhantomData;
8
9#[bisync]
16pub struct Lps22hh<B, S>
17where
18 B: BusOperation,
19 S: SensorState,
20{
21 bus: B,
23 _state: PhantomData<S>,
24}
25
26#[derive(Debug)]
28#[bisync]
29pub enum Error<B> {
30 Bus(B), UnexpectedValue, }
33
34#[bisync]
35impl<P> Lps22hh<i2c::I2cBus<P>, OnState>
36where
37 P: I2c,
38{
39 pub fn new_i2c(i2c: P, address: I2CAddress) -> Self {
41 let bus = i2c::I2cBus::new(i2c, address as SevenBitAddress);
43 Self {
44 bus,
45 _state: PhantomData,
46 }
47 }
48}
49
50#[bisync]
51impl<P> Lps22hh<spi::SpiBus<P>, OnState>
52where
53 P: SpiDevice,
54{
55 pub fn new_spi(spi: P) -> Self {
57 let bus = spi::SpiBus::new(spi);
59 Self {
60 bus,
61 _state: PhantomData,
62 }
63 }
64}
65
66#[bisync]
67impl<B, S> Lps22hh<B, S>
68where
69 B: BusOperation,
70 S: SensorState,
71{
72 pub fn from_bus(bus: B) -> Self {
74 Self {
75 bus,
76 _state: PhantomData,
77 }
78 }
79}
80
81#[bisync]
82impl<B: BusOperation, S: SensorState> SensorOperation for Lps22hh<B, S> {
83 type Error = Error<B::Error>;
84
85 async fn read_from_register(&mut self, reg: u8, buf: &mut [u8]) -> Result<(), Error<B::Error>> {
89 self.bus
90 .read_from_register(reg, buf)
91 .await
92 .map_err(Error::Bus)
93 }
94
95 async fn write_to_register(&mut self, reg: u8, buf: &[u8]) -> Result<(), Error<B::Error>> {
99 self.bus
100 .write_to_register(reg, buf)
101 .await
102 .map_err(Error::Bus)
103 }
104}
105
106#[bisync]
107impl<B: BusOperation> Lps22hh<B, OnState> {
108 pub async fn autozero_rst_set(&mut self, val: u8) -> Result<(), Error<B::Error>> {
112 let mut reg = InterruptCfg::read(self).await?;
113 reg.set_reset_az(val);
114 reg.write(self).await?;
115
116 Ok(())
117 }
118 pub async fn autozero_rst_get(&mut self) -> Result<u8, Error<B::Error>> {
122 let val: u8 = InterruptCfg::read(self).await.map(|reg| reg.reset_az())?;
123
124 Ok(val)
125 }
126 pub async fn autozero_set(&mut self, val: u8) -> Result<(), Error<B::Error>> {
130 let mut reg = InterruptCfg::read(self).await?;
131 reg.set_autozero(val);
132 reg.write(self).await?;
133
134 Ok(())
135 }
136 pub async fn autozero_get(&mut self) -> Result<u8, Error<B::Error>> {
140 let val: u8 = InterruptCfg::read(self).await.map(|reg| reg.autozero())?;
141
142 Ok(val)
143 }
144 pub async fn pressure_snap_rst_set(&mut self, val: u8) -> Result<(), Error<B::Error>> {
148 let mut reg = InterruptCfg::read(self).await?;
149 reg.set_reset_arp(val);
150 reg.write(self).await?;
151
152 Ok(())
153 }
154 pub async fn pressure_snap_rst_get(&mut self) -> Result<u8, Error<B::Error>> {
158 let val: u8 = InterruptCfg::read(self).await.map(|reg| reg.reset_arp())?;
159
160 Ok(val)
161 }
162 pub async fn pressure_snap_set(&mut self, val: u8) -> Result<(), Error<B::Error>> {
167 let mut reg = InterruptCfg::read(self).await?;
168 reg.set_autorefp(val);
169 reg.write(self).await?;
170
171 Ok(())
172 }
173 pub async fn pressure_snap_get(&mut self) -> Result<u8, Error<B::Error>> {
177 let val: u8 = InterruptCfg::read(self).await.map(|reg| reg.autorefp())?;
178
179 Ok(val)
180 }
181 pub async fn block_data_update_set(&mut self, val: u8) -> Result<(), Error<B::Error>> {
186 let mut reg = CtrlReg1::read(self).await?;
187 reg.set_bdu(val);
188 reg.write(self).await?;
189
190 Ok(())
191 }
192 pub async fn block_data_update_get(&mut self) -> Result<u8, Error<B::Error>> {
196 let val: u8 = CtrlReg1::read(self).await.map(|reg| reg.bdu())?;
197
198 Ok(val)
199 }
200 pub async fn data_rate_set(&mut self, val: Odr) -> Result<(), Error<B::Error>> {
205 let mut ctrl_reg1 = CtrlReg1::read(self).await?;
207 let mut ctrl_reg2 = CtrlReg2::read(self).await?;
208
209 ctrl_reg1.set_odr((val as u8) & 0x07);
211 ctrl_reg1.write(self).await?;
212
213 ctrl_reg2.set_low_noise_en((val as u8 & 0x10) >> 4);
216 ctrl_reg2.set_one_shot((val as u8 & 0x08) >> 3);
217 ctrl_reg2.write(self).await?;
218
219 Ok(())
220 }
221 pub async fn data_rate_get(&mut self) -> Result<Odr, Error<B::Error>> {
225 let ctrl_reg1 = CtrlReg1::read(self).await?;
226 let ctrl_reg2 = CtrlReg2::read(self).await?;
227
228 let combined_value =
229 (ctrl_reg2.low_noise_en() << 4) + (ctrl_reg2.one_shot() << 3) + ctrl_reg1.odr();
230
231 let val = Odr::try_from(combined_value).unwrap_or_default();
232
233 Ok(val)
234 }
235 pub async fn pressure_ref_set(&mut self, val: i16) -> Result<(), Error<B::Error>> {
240 let ref_p = RefP::new().with_ref_p(val);
241 ref_p.write(self).await
242 }
243 pub async fn pressure_ref_get(&mut self) -> Result<i16, Error<B::Error>> {
248 Ok(RefP::read(self).await?.ref_p())
249 }
250 pub async fn pressure_offset_set(&mut self, val: i16) -> Result<(), Error<B::Error>> {
255 Rpds::new().with_rpds(val).write(self).await
256 }
257 pub async fn pressure_offset_get(&mut self) -> Result<i16, Error<B::Error>> {
261 Rpds::read(self).await.map(|reg| reg.rpds())
262 }
263 pub async fn all_sources_get(
267 &mut self,
268 ) -> Result<(IntSource, FifoStatus2, Status), Error<B::Error>> {
269 Ok((
270 IntSource::read(self).await?,
271 FifoStatusReg::read(self).await?.into(),
272 Status::read(self).await?,
273 ))
274 }
275 pub async fn status_reg_get(&mut self) -> Result<Status, Error<B::Error>> {
279 Status::read(self).await
280 }
281 pub async fn press_flag_data_ready_get(&mut self) -> Result<u8, Error<B::Error>> {
285 let val: u8 = Status::read(self).await.map(|reg| reg.p_da())?;
286
287 Ok(val)
288 }
289 pub async fn temp_flag_data_ready_get(&mut self) -> Result<u8, Error<B::Error>> {
293 let val: u8 = Status::read(self).await.map(|reg| reg.t_da())?;
294
295 Ok(val)
296 }
297 pub async fn pressure_raw_get(&mut self) -> Result<u32, Error<B::Error>> {
301 let reg = PressOut::read(self).await?;
302 Ok(reg.pressure())
303 }
304 pub async fn temperature_raw_get(&mut self) -> Result<i16, Error<B::Error>> {
308 let val = TempOut::read(self).await?;
309 Ok(val.temperature())
310 }
311 pub async fn fifo_pressure_raw_get(&mut self) -> Result<u32, Error<B::Error>> {
315 let reg = FifoDataOutPress::read(self).await?;
316 Ok(reg.pressure())
317 }
318 pub async fn fifo_temperature_raw_get(&mut self) -> Result<i16, Error<B::Error>> {
322 let fifo_temp = FifoDataOutTemp::read(self).await?;
323 Ok(fifo_temp.temperature())
324 }
325 pub async fn device_id_get(&mut self) -> Result<u8, Error<B::Error>> {
329 WhoAmI::read(self).await.map(|reg| reg.who_am_i())
330 }
331 pub async fn reset_set(&mut self, val: u8) -> Result<(), Error<B::Error>> {
335 let mut reg = CtrlReg2::read(self).await?;
336 reg.set_swreset(val);
337 reg.write(self).await
338 }
339 pub async fn reset_get(&mut self) -> Result<u8, Error<B::Error>> {
343 let val: u8 = CtrlReg2::read(self).await?.swreset();
344
345 Ok(val)
346 }
347 pub async fn auto_increment_set(&mut self, val: u8) -> Result<(), Error<B::Error>> {
351 let mut reg = CtrlReg2::read(self).await?;
352 reg.set_if_add_inc(val);
353 reg.write(self).await
354 }
355 pub async fn auto_increment_get(&mut self) -> Result<u8, Error<B::Error>> {
359 let val: u8 = CtrlReg2::read(self).await?.if_add_inc();
360
361 Ok(val)
362 }
363 pub async fn boot_set(&mut self, val: u8) -> Result<(), Error<B::Error>> {
367 let mut reg = CtrlReg2::read(self).await?;
368 reg.set_boot(val);
369 reg.write(self).await
370 }
371 pub async fn boot_get(&mut self) -> Result<u8, Error<B::Error>> {
375 let val: u8 = CtrlReg2::read(self).await?.boot();
376
377 Ok(val)
378 }
379 pub async fn lp_bandwidth_set(&mut self, val: LpfpCfg) -> Result<(), Error<B::Error>> {
383 let mut reg = CtrlReg1::read(self).await?;
384 reg.set_lpfp_cfg(val as u8);
385 reg.write(self).await
386 }
387 pub async fn lp_bandwidth_get(&mut self) -> Result<LpfpCfg, Error<B::Error>> {
391 let reg = CtrlReg1::read(self).await?;
392
393 let val = LpfpCfg::try_from(reg.lpfp_cfg()).unwrap_or_default();
394
395 Ok(val)
396 }
397 pub async fn i2c_interface_set(&mut self, val: I2cMode) -> Result<(), Error<B::Error>> {
401 let mut reg = IfCtrl::read(self).await?;
402 reg.set_i2c_disable(val as u8);
403 reg.write(self).await
404 }
405 pub async fn i2c_interface_get(&mut self) -> Result<I2cMode, Error<B::Error>> {
409 let reg = IfCtrl::read(self).await?;
410
411 let val = I2cMode::try_from(reg.i2c_disable()).unwrap_or_default();
412 Ok(val)
413 }
414 pub async fn i3c_interface_set(&mut self, val: I3cMode) -> Result<(), Error<B::Error>> {
418 let mut reg = IfCtrl::read(self).await?;
419 reg.set_i3c_disable((val as u8) & 0x01);
420 reg.set_int_en_i3c(((val as u8) & 0x10) >> 4);
421 reg.write(self).await
422 }
423 pub async fn i3c_interface_get(&mut self) -> Result<I3cMode, Error<B::Error>> {
427 let reg = IfCtrl::read(self).await?;
428 let reg_int_en_i3c = reg.int_en_i3c();
429 let reg_i3c_disable = reg.i3c_disable();
430 let val = (reg_int_en_i3c << 4) + reg_i3c_disable;
431 let val = I3cMode::try_from(val).unwrap_or_default();
432
433 Ok(val)
434 }
435 pub async fn sdo_sa0_mode_set(&mut self, val: PullUp) -> Result<(), Error<B::Error>> {
439 let mut reg = IfCtrl::read(self).await?;
440 reg.set_sdo_pu_en(val as u8);
441 reg.write(self).await
442 }
443 pub async fn sdo_sa0_mode_get(&mut self) -> Result<PullUp, Error<B::Error>> {
447 let tmp: u8 = IfCtrl::read(self).await?.sdo_pu_en();
448 let val = PullUp::try_from(tmp).unwrap_or_default();
449 Ok(val)
450 }
451 pub async fn sda_mode_set(&mut self, val: PullUp) -> Result<(), Error<B::Error>> {
455 let mut reg = IfCtrl::read(self).await?;
456 reg.set_sda_pu_en(val as u8);
457 reg.write(self).await?;
458
459 Ok(())
460 }
461 pub async fn sda_mode_get(&mut self) -> Result<PullUp, Error<B::Error>> {
465 let reg = IfCtrl::read(self).await?;
466
467 let val = PullUp::try_from(reg.sda_pu_en()).unwrap_or_default();
468 Ok(val)
469 }
470 pub async fn spi_mode_set(&mut self, val: Sim) -> Result<(), Error<B::Error>> {
474 let mut reg = CtrlReg1::read(self).await?;
475 reg.set_sim(val as u8);
476 reg.write(self).await?;
477
478 Ok(())
479 }
480 pub async fn spi_mode_get(&mut self) -> Result<Sim, Error<B::Error>> {
484 let reg = CtrlReg1::read(self).await?;
485
486 let val = Sim::try_from(reg.sim()).unwrap_or_default();
487 Ok(val)
488 }
489 pub async fn int_notification_set(&mut self, val: Lir) -> Result<(), Error<B::Error>> {
493 let mut reg = InterruptCfg::read(self).await?;
494 reg.set_lir(val as u8);
495 reg.write(self).await?;
496
497 Ok(())
498 }
499 pub async fn int_notification_get(&mut self) -> Result<Lir, Error<B::Error>> {
503 let reg = InterruptCfg::read(self).await?;
504
505 let val = Lir::try_from(reg.lir()).unwrap_or_default();
506 Ok(val)
507 }
508 pub async fn pin_mode_set(&mut self, val: PpOd) -> Result<(), Error<B::Error>> {
512 let mut reg = CtrlReg2::read(self).await?;
513 reg.set_pp_od(val as u8);
514 reg.write(self).await?;
515
516 Ok(())
517 }
518 pub async fn pin_mode_get(&mut self) -> Result<PpOd, Error<B::Error>> {
522 let reg = CtrlReg2::read(self).await?;
523
524 let val = PpOd::try_from(reg.pp_od()).unwrap_or_default();
525 Ok(val)
526 }
527 pub async fn pin_polarity_set(&mut self, val: IntHL) -> Result<(), Error<B::Error>> {
531 let mut reg = CtrlReg2::read(self).await?;
532 reg.set_int_h_l(val as u8);
533 reg.write(self).await?;
534
535 Ok(())
536 }
537 pub async fn pin_polarity_get(&mut self) -> Result<IntHL, Error<B::Error>> {
541 let reg = CtrlReg2::read(self).await?;
542
543 let val = IntHL::try_from(reg.int_h_l()).unwrap_or_default();
544
545 Ok(val)
546 }
547 pub async fn pin_int_route_set(&mut self, val: PinIntRoute) -> Result<(), Error<B::Error>> {
552 let mut ctrl_reg3 = CtrlReg3::read(self).await?;
553
554 ctrl_reg3.set_drdy(val.drdy_pres as u8);
555 ctrl_reg3.set_int_f_wtm(val.fifo_th as u8);
556 ctrl_reg3.set_int_f_ovr(val.fifo_ovr as u8);
557 ctrl_reg3.set_int_f_full(val.fifo_full as u8);
558
559 ctrl_reg3.write(self).await?;
560
561 Ok(())
562 }
563 pub async fn pin_int_route_get(&mut self) -> Result<PinIntRoute, Error<B::Error>> {
567 let ctrl_reg3 = CtrlReg3::read(self).await?;
568
569 let val = PinIntRoute {
570 drdy_pres: ctrl_reg3.drdy() != 0,
571 fifo_th: ctrl_reg3.int_f_wtm() != 0,
572 fifo_ovr: ctrl_reg3.int_f_ovr() != 0,
573 fifo_full: ctrl_reg3.int_f_full() != 0,
574 };
575
576 Ok(val)
577 }
578 pub async fn int_on_threshold_set(&mut self, val: Pe) -> Result<(), Error<B::Error>> {
583 let mut reg = InterruptCfg::read(self).await?;
584 reg.set_pe(val as u8);
585
586 if (val as u8) == (Pe::NoThreshold as u8) {
587 reg.set_diff_en(0_u8);
588 } else {
589 reg.set_diff_en(1_u8);
590 }
591
592 reg.write(self).await?;
593
594 Ok(())
595 }
596 pub async fn int_on_threshold_get(&mut self) -> Result<Pe, Error<B::Error>> {
600 let reg = InterruptCfg::read(self).await?;
601
602 let val = Pe::try_from(reg.pe()).unwrap_or_default();
603 Ok(val)
604 }
605 pub async fn int_threshold_set(&mut self, buff: u16) -> Result<(), Error<B::Error>> {
610 ThsP::from_bits(buff).write(self).await
611 }
612 pub async fn int_threshold_get(&mut self) -> Result<u16, Error<B::Error>> {
616 let val = ThsP::read(self).await?;
617 Ok(val.ths())
618 }
619 pub async fn fifo_mode_set(&mut self, val: FMode) -> Result<(), Error<B::Error>> {
623 let mut reg = FifoCtrl::read(self).await?;
624 reg.set_f_mode(val as u8);
625 reg.write(self).await
626 }
627 pub async fn fifo_mode_get(&mut self) -> Result<FMode, Error<B::Error>> {
631 let reg = FifoCtrl::read(self).await?;
632 let val = FMode::try_from(reg.f_mode()).unwrap_or_default();
633
634 Ok(val)
635 }
636 pub async fn fifo_stop_on_wtm_set(&mut self, val: u8) -> Result<(), Error<B::Error>> {
640 let mut reg = FifoCtrl::read(self).await?;
641 reg.set_stop_on_wtm(val);
642 reg.write(self).await?;
643
644 Ok(())
645 }
646 pub async fn fifo_stop_on_wtm_get(&mut self) -> Result<u8, Error<B::Error>> {
650 let val: u8 = FifoCtrl::read(self).await.map(|reg| reg.stop_on_wtm())?;
651
652 Ok(val)
653 }
654 pub async fn fifo_watermark_set(&mut self, val: u8) -> Result<(), Error<B::Error>> {
658 let mut reg = FifoWtm::read(self).await?;
659 reg.set_wtm(val);
660 reg.write(self).await?;
661
662 Ok(())
663 }
664 pub async fn fifo_watermark_get(&mut self) -> Result<u8, Error<B::Error>> {
668 let val: u8 = FifoWtm::read(self).await.map(|reg| reg.wtm())?;
669
670 Ok(val)
671 }
672 pub async fn fifo_data_level_get(&mut self) -> Result<u8, Error<B::Error>> {
676 let val = FifoStatusReg::read(self).await?.into_bits();
677 Ok(val.to_le_bytes()[0])
678 }
679 pub async fn fifo_src_get(&mut self) -> Result<FifoStatus2, Error<B::Error>> {
683 let val = FifoStatusReg::read(self).await?;
684 Ok(val.into())
685 }
686 pub async fn fifo_full_flag_get(&mut self) -> Result<u8, Error<B::Error>> {
690 let val: u8 = FifoStatusReg::read(self)
691 .await
692 .map(|reg| reg.fifo_full_ia())?;
693
694 Ok(val)
695 }
696 pub async fn fifo_ovr_flag_get(&mut self) -> Result<u8, Error<B::Error>> {
700 let val: u8 = FifoStatusReg::read(self)
701 .await
702 .map(|reg| reg.fifo_ovr_ia())?;
703
704 Ok(val)
705 }
706 pub async fn fifo_wtm_flag_get(&mut self) -> Result<u8, Error<B::Error>> {
710 let val: u8 = FifoStatusReg::read(self)
711 .await
712 .map(|reg| reg.fifo_wtm_ia())?;
713
714 Ok(val)
715 }
716}
717
718#[bisync]
719pub fn from_lsb_to_celsius(lsb: i16) -> f32 {
720 (lsb as f32) / 100.0
721}
722
723#[bisync]
724pub fn from_lsb_to_hpa(lsb: u32) -> f32 {
725 (lsb as f32) / 4096.0
726}
727
728#[repr(u8)]
734#[bisync]
735pub enum I2CAddress {
736 AddressH = 0x5D,
737 AddressL = 0x5C,
738}
739
740#[bisync]
742pub const ID: u8 = 0xB3;