lps22hb/interrupt.rs
1//! Various functions related to interrupts
2//!
3
4use super::*;
5
6/// Interrupt pin settings
7#[derive(Debug)]
8pub struct InterruptConfig {
9 /// configure interrupt pin as active high or active low
10 pub active_high_or_low: bool,
11 /// configure interrupt pin as push-pull or open drain
12 pub pushpull_or_opendrain: bool,
13 /// configure data signal on the interrupt pin
14 pub data_signal_config: INT_DRDY,
15 /// enable FIFO full flag on interrupt pin
16 pub enable_fifo_full: bool,
17 /// enable FIFO watermark flag on interrupt pin
18 pub enable_fifo_fth: bool,
19 /// enable FIFO overrun flag on interrupt pin
20 pub enable_fifo_overrun: bool,
21 /// enable data ready signal on interrupt pin
22 pub enable_data_ready: bool,
23 /// enable latching interrupt request to INT_SOURCE register
24 pub enable_latch_interrupt: bool,
25 /// enable low pressure event on interrupt pin
26 pub enable_low_event: bool,
27 /// enable hihg pressure event on interrupt pin
28 pub enable_high_event: bool,
29}
30
31impl Default for InterruptConfig {
32 fn default() -> Self {
33 InterruptConfig {
34 active_high_or_low: false, // active high (CTRL_REG3)
35 pushpull_or_opendrain: false, // push-pull (CTRL_REG3)
36 data_signal_config: INT_DRDY::DataSignal, // data signal on INT_DRDY pin (CTRL_REG3)
37 enable_fifo_full: false, // disabled (CTRL_REG3)
38 enable_fifo_fth: false, // disabled (CTRL_REG3)
39 enable_fifo_overrun: false, // disabled (CTRL_REG3)
40 enable_data_ready: false, // disabled (CTRL_REG3)
41 enable_latch_interrupt: false, // inferrupt request not latched (INTERRUPT_CFG)
42 enable_low_event: false, // disable interrupt request on low pressure event (INTERRUPT_CFG)
43 enable_high_event: false, // disable interrupt request on low pressure event (INTERRUPT_CFG)
44 }
45 }
46}
47
48impl InterruptConfig {
49 /// Returns values to be written to CTRL_REG3, CTRL_REG4 and INTERRUPT_CFG:
50 fn int_ctrl_reg3(&self) -> u8 {
51 let mut data = 0u8;
52 if self.active_high_or_low {
53 data |= 1 << 7;
54 }
55 if self.pushpull_or_opendrain {
56 data |= 1 << 6;
57 }
58 if self.enable_fifo_full {
59 data |= 1 << 5;
60 }
61 if self.enable_fifo_fth {
62 data |= 1 << 4;
63 }
64 if self.enable_fifo_overrun {
65 data |= 1 << 3;
66 }
67 if self.enable_data_ready {
68 data |= 1 << 2;
69 }
70 data |= self.data_signal_config.value();
71 data
72 }
73 fn int_interrupt_cfg(&self) -> u8 {
74
75 let mut data = 0u8;
76
77 if self.enable_latch_interrupt {
78 data |= 1 << 2;
79 }
80 if self.enable_low_event {
81 data |= 1 << 1;
82 }
83 if self.enable_high_event {
84 data |= 1;
85 }
86 data // this must be OR'ed with the content of the INTERRUPT_CFG
87 }
88}
89
90#[derive(Debug)]
91/// Contents of the INT_SOURCE register (interrupt active and differential pressure events flags)
92pub struct IntSource {
93 pub interrupt_active: bool,
94 pub diff_press_low: bool,
95 pub diff_press_high: bool,
96}
97
98impl<T, E> LPS22HB<T>
99where
100 T: Interface<Error = E>,
101{
102 /// Enable interrupts and configure the interrupt pin
103 pub fn enable_interrupts(&mut self, flag: bool, config: InterruptConfig,) -> Result<(), T::Error> {
104 match flag {
105 true => self.set_register_bit_flag(Registers::INTERRUPT_CFG, Bitmasks::DIFF_EN),
106 false => self.clear_register_bit_flag(Registers::INTERRUPT_CFG, Bitmasks::DIFF_EN),
107 }?;
108 self.interface
109 .write(Registers::CTRL_REG3.addr(), config.int_ctrl_reg3())?;
110
111 let mut buffer = [0u8;1];
112 self.read_register(Registers::INTERRUPT_CFG)?;
113 let mut interrupt_cfg = 0u8;
114 interrupt_cfg |= config.int_interrupt_cfg();
115
116 self.interface
117 .write(Registers::INTERRUPT_CFG.addr(), interrupt_cfg)?;
118 Ok(())
119 }
120
121 // --- THE FOLLOWING SECTION COULD BE REMOVED ---
122
123 /*
124
125
126 /// Configuration of the interrupt generation (enabled/disable)
127 pub fn int_generation_enable(&mut self, flag: bool) -> Result<(), T::Error> {
128 match flag {
129 true => self.set_register_bit_flag(Registers::INTERRUPT_CFG, Bitmasks::DIFF_EN),
130 false => self.clear_register_bit_flag(Registers::INTERRUPT_CFG, Bitmasks::DIFF_EN),
131 }
132 }
133
134 /// Interrupt request latching to INT_SOURCE
135 pub fn int_latch_enable(&mut self, flag: bool) -> Result<(), T::Error> {
136 match flag {
137 true => self.set_register_bit_flag(Registers::INTERRUPT_CFG, Bitmasks::LIR),
138 false => self.clear_register_bit_flag(Registers::INTERRUPT_CFG, Bitmasks::LIR),
139 }
140 }
141
142 /// Data-ready signal on INT_DRDY pin
143 pub fn data_signal_drdy_enable(&mut self, flag: bool) -> Result<(), T::Error> {
144 match flag {
145 true => self.set_register_bit_flag(Registers::CTRL_REG3, Bitmasks::DRDY),
146 false => self.clear_register_bit_flag(Registers::CTRL_REG3, Bitmasks::DRDY),
147 }
148 }
149
150 /// Interrupt active high/low (default active high)
151 pub fn interrupt_pin_active(&mut self, setting: INT_ACTIVE) -> Result<(), T::Error> {
152 match setting {
153 INT_ACTIVE::High => {
154 self.clear_register_bit_flag(Registers::CTRL_REG3, Bitmasks::INT_H_L)
155 }
156 INT_ACTIVE::Low => self.set_register_bit_flag(Registers::CTRL_REG3, Bitmasks::INT_H_L),
157 }
158 }
159
160 /// Interrupt pin configuration: push-pull (default) or open drain
161 pub fn interrupt_pin_config(&mut self, setting: INT_PIN) -> Result<(), T::Error> {
162 match setting {
163 INT_PIN::PushPull => {
164 self.clear_register_bit_flag(Registers::CTRL_REG3, Bitmasks::PP_OD)
165 }
166 INT_PIN::OpenDrain => self.set_register_bit_flag(Registers::CTRL_REG3, Bitmasks::PP_OD),
167 }
168 }
169
170 /// Configure INT_DRDY pin
171 pub fn int_drdy_config(&mut self, config: INT_DRDY) -> Result<(), T::Error> {
172 let mut reg_data = [0u8];
173 self.interface
174 .read(Registers::CTRL_REG3.addr(), &mut reg_data)?;
175 let mut payload = reg_data[0];
176 payload &= !Bitmasks::INT_S_MASK;
177 payload |= config.value();
178 self.interface.write(Registers::CTRL_REG3.addr(), payload)?;
179 Ok(())
180 }
181
182 */
183
184 /// Get all the flags from the INT_SOURCE register (NOTE: INT_SOURCE register is cleared by reading it)
185 pub fn get_int_status(&mut self) -> Result<IntSource, T::Error> {
186 let status = IntSource {
187 /// Has any interrupt event been generated? (self clearing)
188 interrupt_active: self.is_register_bit_flag_high(Registers::INT_SOURCE, Bitmasks::IA)?,
189 /// Has low differential pressure event been generated? (self clearing)
190 diff_press_low: self.is_register_bit_flag_high(Registers::INT_SOURCE, Bitmasks::PL)?,
191 /// Has high differential pressure event been generated? (self clearing)
192 diff_press_high: self.is_register_bit_flag_high(Registers::INT_SOURCE, Bitmasks::PH)?,
193 };
194 Ok(status)
195 }
196
197 // --- THESE FUNCTIONS COULD BE REMOVED ---
198
199 /*
200
201 /// Has any interrupt event been generated? (self clearing)
202 pub fn interrupt_active(&mut self) -> Result<bool, T::Error> {
203 self.is_register_bit_flag_high(Registers::INT_SOURCE, Bitmasks::IA)
204 }
205
206 /// Has low differential pressure event been generated? (self clearing)
207 pub fn low_pressure_event_occurred(&mut self) -> Result<bool, T::Error> {
208 self.is_register_bit_flag_high(Registers::INT_SOURCE, Bitmasks::PL)
209 }
210
211 /// Has high differential pressure event been generated? (self clearing)
212 pub fn high_pressure_event_occurred(&mut self) -> Result<bool, T::Error> {
213 self.is_register_bit_flag_high(Registers::INT_SOURCE, Bitmasks::PH)
214 }
215
216 /// Enable interrupt on differential pressure high event
217 pub fn diff_press_high_enable(&mut self, flag: bool) -> Result<(), T::Error> {
218 match flag {
219 true => self.set_register_bit_flag(Registers::INTERRUPT_CFG, Bitmasks::PHE),
220 false => self.clear_register_bit_flag(Registers::INTERRUPT_CFG, Bitmasks::PHE),
221 }
222 }
223
224 */
225}