lps22df_rs/register/
main.rs

1use super::super::{
2    BusOperation, DelayNs, Error, Lps22df, RegisterOperation, SensorOperation, bisync,
3    register::OnState,
4};
5
6use bitfield_struct::bitfield;
7use derive_more::TryFrom;
8
9use st_mem_bank_macro::register;
10
11/// Register addresses for LPS22DF device.
12#[repr(u8)]
13#[derive(Clone, Copy, PartialEq)]
14pub enum Reg {
15    InterruptCfg = 0x0B,
16    ThsPL = 0x0C,
17    ThsPH = 0x0D,
18    IfCtrl = 0x0E,
19    WhoAmI = 0x0F,
20    CtrlReg1 = 0x10,
21    CtrlReg2 = 0x11,
22    CtrlReg3 = 0x12,
23    CtrlReg4 = 0x13,
24    FifoCtrl = 0x14,
25    FifoWtm = 0x15,
26    RefPL = 0x16,
27    RefPH = 0x17,
28    I3cIfCtrl = 0x19,
29    RpdsL = 0x1A,
30    RpdsH = 0x1B,
31    IntSource = 0x24,
32    FifoStatus1 = 0x25,
33    FifoStatus2 = 0x26,
34    Status = 0x27,
35    PressOutXl = 0x28,
36    PressOutL = 0x29,
37    PressOutH = 0x2A,
38    TempOutL = 0x2B,
39    TempOutH = 0x2C,
40    FifoDataOutPressXl = 0x78,
41    FifoDataOutPressL = 0x79,
42    FifoDataOutPressH = 0x7A,
43}
44
45/// INTERRUPT_CFG (0x0B)
46///
47/// Interrupt mode for pressure acquisition configuration (R/W)
48#[register(address = Reg::InterruptCfg, access_type = "Lps22df<B, T, OnState>")]
49#[cfg_attr(feature = "bit_order_msb", bitfield(u8, order = Msb))]
50#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u8, order = Lsb))]
51pub struct InterruptCfg {
52    /// Enable interrupt generation on pressure high event (1 bit)
53    /// (0: disable interrupt request; 1: enable interrupt request on pressure value higher than preset threshold)
54    #[bits(1)]
55    pub phe: u8,
56    /// Enable interrupt generation on pressure low event (1 bit)
57    /// (0: disable interrupt request; 1: enable interrupt request on pressure value lower than preset threshold)
58    #[bits(1)]
59    pub ple: u8,
60    /// Latch interrupt request to the INT_SOURCE register (1 bit)
61    /// (0: interrupt request not latched; 1: interrupt request latched)
62    #[bits(1)]
63    pub lir: u8,
64    #[bits(1, access = RO)]
65    pub not_used_01: u8,
66    /// Reset AUTOZERO function (1 bit)
67    /// (0: normal mode; 1: reset AUTOZERO function)
68    #[bits(1)]
69    pub reset_az: u8,
70    /// Enable AUTOZERO function (1 bit)
71    /// (0: normal mode; 1: AUTOZERO enabled)
72    #[bits(1)]
73    pub autozero: u8,
74    /// Reset AUTOREFP function (1 bit)
75    /// (0: normal mode; 1: reset AUTOREFP function)
76    #[bits(1)]
77    pub reset_arp: u8,
78    /// Enable AUTOREFP function (1 bit)
79    /// (0: normal mode; 1: AUTOREFP enabled)
80    #[bits(1)]
81    pub autorefp: u8,
82}
83
84/// THS_P_L - THS_P_H (0x0C - 0x0D)
85///
86/// User-defined threshold value for pressure interrupt event  (R/W)
87/// This register contains the 15-bit threshold value used for pressure interrupt generation.
88/// The threshold value is expressed as: THS_P (15-bit unsigned) = Desired interrupt threshold (hPa) × 16.
89#[register(address = Reg::ThsPL, access_type = "Lps22df<B, T, OnState>", override_type = u16)]
90#[cfg_attr(feature = "bit_order_msb", bitfield(u16, order = Msb))]
91#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u16, order = Lsb))]
92pub struct ThsP {
93    #[bits(15)]
94    pub ths: u16,
95    #[bits(1, access = RO)]
96    pub not_used_01: u8,
97}
98
99/// IF_CTRL (0x0E)
100///
101/// Interface control register (R/W)
102#[register(address = Reg::IfCtrl, access_type = "Lps22df<B, T, OnState>")]
103#[cfg_attr(feature = "bit_order_msb", bitfield(u8, order = Msb))]
104#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u8, order = Lsb))]
105pub struct IfCtrl {
106    #[bits(1, access = RO)]
107    pub not_used_01: u8,
108    /// Disable pull-up on the CS pin (1 bit)
109    /// (0: CS pin with pull-up; 1: CS pin pull-up disconnected)
110    #[bits(1)]
111    pub cs_pu_dis: u8,
112    /// Disable pull-down on the INT pin (1 bit)
113    /// (0: INT pin with pull-down; 1: INT pin pull-down disconnected)
114    #[bits(1)]
115    pub int_pd_dis: u8,
116    /// Enable pull-up on the SDO pin (1 bit)
117    /// (0: SDO pin pull-up disconnected; 1: SDO pin with pull-up)
118    #[bits(1)]
119    pub sdo_pu_en: u8,
120    /// Enable pull-up on the SDA pin (1 bit)
121    /// (0: SDA pin pull-up disconnected; 1: SDA pin with pull-up)
122    #[bits(1)]
123    pub sda_pu_en: u8,
124    /// SPI serial interface mode selection (1 bit)
125    /// (0: 4-wire interface; 1: 3-wire interface)
126    #[bits(1)]
127    pub sim: u8,
128    /// Disable I²C and I3C digital interfaces (1 bit)
129    /// (0: enable I²C and I3C digital interfaces; 1: disable I²C and I3C digital interfaces)
130    #[bits(1)]
131    pub i2c_i3c_dis: u8,
132    /// Enable INT pin with MIPI I3C (1 bit)
133    /// (0: INT disabled with MIPI I3C; 1: INT enabled with MIPI I3C)
134    #[bits(1)]
135    pub int_en_i3c: u8,
136}
137
138/// WHO_AM_I (0x0F)
139///
140/// WHO_AM_I register (R), read-only, fixed value 0xB4.
141#[register(address = Reg::WhoAmI, access_type = "Lps22df<B, T, OnState>")]
142#[cfg_attr(feature = "bit_order_msb", bitfield(u8, order = Msb))]
143#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u8, order = Lsb))]
144pub struct WhoAmI {
145    /// Device identification value.
146    #[bits(8)]
147    pub id: u8,
148}
149
150/// CTRL_REG1 (0x10)
151///
152/// Control register 1 (R/W)
153#[register(address = Reg::CtrlReg1, access_type = "Lps22df<B, T, OnState>")]
154#[cfg_attr(feature = "bit_order_msb", bitfield(u8, order = Msb))]
155#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u8, order = Lsb))]
156pub struct CtrlReg1 {
157    /// Averaging selection for pressure and temperature (3 bits)
158    /// Configures resolution and power consumption (see datasheet Table 18)
159    #[bits(3)]
160    pub avg: u8,
161    /// Output data rate selection (4 bits)
162    /// Controls frequency of pressure and temperature data updates (see datasheet Table 17)
163    #[bits(4)]
164    pub odr: u8,
165    #[bits(1, access = RO)]
166    pub not_used_01: u8,
167}
168
169/// CTRL_REG2 (0x11)
170///
171/// Control register 2 (R/W)
172#[register(address = Reg::CtrlReg2, access_type = "Lps22df<B, T, OnState>")]
173#[cfg_attr(feature = "bit_order_msb", bitfield(u8, order = Msb))]
174#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u8, order = Lsb))]
175pub struct CtrlReg2 {
176    /// Enable one-shot mode (1 bit)
177    /// (0: idle mode; 1: a new dataset is acquired)
178    #[bits(1)]
179    pub oneshot: u8,
180    #[bits(1, access = RO)]
181    pub not_used_01: u8,
182    /// Software reset (1 bit)
183    /// (0: normal mode; 1: software reset, self-clears when reset is completed)
184    #[bits(1)]
185    pub swreset: u8,
186    /// Block data update (1 bit)
187    /// (0: continuous update; 1: output registers not updated until MSB and LSB have been read)
188    #[bits(1)]
189    pub bdu: u8,
190    /// Enable low-pass filter on pressure data (1 bit)
191    /// (0: disable; 1: enable)
192    #[bits(1)]
193    pub en_lpfp: u8,
194    /// Low-pass filter configuration (1 bit)
195    /// (0: ODR/4; 1: ODR/9)
196    #[bits(1)]
197    pub lfpf_cfg: u8,
198    #[bits(1, access = RO)]
199    pub not_used_02: u8,
200    /// Reboot memory content (1 bit)
201    /// (0: normal mode; 1: reboot memory content, self-clears after boot)
202    #[bits(1)]
203    pub boot: u8,
204}
205
206/// CTRL_REG3 (0x12)
207///
208/// Control register 3 (R/W)
209#[register(address = Reg::CtrlReg3, access_type = "Lps22df<B, T, OnState>")]
210#[cfg_attr(feature = "bit_order_msb", bitfield(u8, order = Msb))]
211#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u8, order = Lsb))]
212pub struct CtrlReg3 {
213    /// Register address automatically incremented during multiple byte access (1 bit)
214    /// (0: disable; 1: enable)
215    #[bits(1)]
216    pub if_add_inc: u8,
217    /// Push-pull/open-drain selection on interrupt pin (1 bit)
218    /// (0: push-pull; 1: open-drain)
219    #[bits(1)]
220    pub pp_od: u8,
221    #[bits(1, access = RO)]
222    pub not_used_02: u8,
223    /// Select interrupt active-high or active-low (1 bit)
224    /// (0: active-high; 1: active-low)
225    #[bits(1)]
226    pub int_h_l: u8,
227    #[bits(4, access = RO)]
228    pub not_used_01: u8,
229}
230
231/// CTRL_REG4 (0x13)
232///
233/// Control register 4 (R/W)
234#[register(address = Reg::CtrlReg4, access_type = "Lps22df<B, T, OnState>")]
235#[cfg_attr(feature = "bit_order_msb", bitfield(u8, order = Msb))]
236#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u8, order = Lsb))]
237pub struct CtrlReg4 {
238    /// Data-ready pulsed on INT pin (1 bit)
239    /// (0: disable; 1: enable data-ready pulse on INT pin, pulse width ~5 μs)
240    #[bits(1)]
241    pub int_f_ovr: u8,
242    /// Interrupt signal on INT pin (1 bit)
243    /// (0: disable; 1: enable)
244    #[bits(1)]
245    pub int_f_wtm: u8,
246    /// FIFO full flag on INT pin (1 bit)
247    /// (0: FIFO empty; 1: FIFO full with 128 unread samples)
248    #[bits(1)]
249    pub int_f_full: u8,
250    #[bits(1, access = RO)]
251    pub not_used_02: u8,
252    /// Interrupt enable on INT pin (1 bit)
253    /// (0: disable; 1: enable)
254    #[bits(1)]
255    pub int_en: u8,
256    /// Data-ready signal on INT pin (1 bit)
257    /// (0: disable; 1: enable)
258    #[bits(1)]
259    pub drdy: u8,
260    /// Data-ready pulse on INT pin (1 bit)
261    /// (0: disable; 1: enable)
262    #[bits(1)]
263    pub drdy_pls: u8,
264    #[bits(1, access = RO)]
265    pub not_used_01: u8,
266}
267
268/// FIFO_CTRL (0x14)
269///
270/// FIFO control register (R/W)
271#[register(address = Reg::FifoCtrl, access_type = "Lps22df<B, T, OnState>")]
272#[cfg_attr(feature = "bit_order_msb", bitfield(u8, order = Msb))]
273#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u8, order = Lsb))]
274pub struct FifoCtrl {
275    /// FIFO mode selection (2 bits)
276    /// Selects FIFO operating mode (see datasheet Table 21)
277    #[bits(2)]
278    pub f_mode: u8,
279    /// Enables triggered FIFO modes (1 bit)
280    #[bits(1)]
281    pub trig_modes: u8,
282    /// Stop-on-FIFO watermark (1 bit)
283    /// Enables FIFO watermark level use
284    #[bits(1)]
285    pub stop_on_wtm: u8,
286    #[bits(4, access = RO)]
287    pub not_used_01: u8,
288}
289
290/// FIFO_WTM (0x15)
291///
292/// FIFO threshold setting register (R/W)
293#[register(address = Reg::FifoWtm, access_type = "Lps22df<B, T, OnState>")]
294#[cfg_attr(feature = "bit_order_msb", bitfield(u8, order = Msb))]
295#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u8, order = Lsb))]
296pub struct FifoWtm {
297    /// FIFO threshold watermark level (7 bits)
298    #[bits(7)]
299    pub wtm: u8,
300    #[bits(1, access = RO)]
301    pub not_used_01: u8,
302}
303
304/// REF_P_L - REF_P_H (0x16 - 0x17)
305///
306/// Reference pressure LSB data (R)
307/// Contains reference pressure value used for AUTOZERO or AUTOREFP functions.
308/// The value is expressed as two's complement and stored in REF_P_H and REF_P_L registers.
309#[register(address = Reg::RefPL, access_type = "Lps22df<B, T, OnState>")]
310#[cfg_attr(feature = "bit_order_msb", bitfield(u16, order = Msb))]
311#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u16, order = Lsb))]
312pub struct RefP {
313    #[bits(16)]
314    pub refp: i16,
315}
316
317/// I3C_IF_CTRL_ADD (0x19)
318///
319/// Interface configuration register (R/W)
320#[register(address = Reg::I3cIfCtrl, access_type = "Lps22df<B, T, OnState>")]
321#[cfg_attr(feature = "bit_order_msb", bitfield(u8, order = Msb))]
322#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u8, order = Lsb))]
323pub struct I3cIfCtrl {
324    /// I3C bus available time selection (2 bits)
325    /// Selects bus available time when I3C IBI is used
326    #[bits(2)]
327    pub i3c_bus_avb_sel: u8,
328    #[bits(3, access = RO)]
329    pub not_used_02: u8,
330    /// Enables antispike filters (1 bit)
331    /// (0: antispike filters managed by protocol; 1: antispike filters always enabled)
332    #[bits(1)]
333    pub asf_on: u8,
334    #[bits(2, access = RO)]
335    pub not_used_01: u8,
336}
337
338/// RPDS_L - RPDS_H (0x1A - 0x1B)
339///
340/// Pressure offset (R/W)
341#[register(address = Reg::RpdsL, access_type = "Lps22df<B, T, OnState>", override_type = u16)]
342#[cfg_attr(feature = "bit_order_msb", bitfield(u16, order = Msb))]
343#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u16, order = Lsb))]
344pub struct Rpds {
345    #[bits(16)]
346    pub offset: i16,
347}
348
349/// INT_SOURCE (0x24)
350///
351/// Interrupt source register (read only)
352#[register(address = Reg::IntSource, access_type = "Lps22df<B, T, OnState>")]
353#[cfg_attr(feature = "bit_order_msb", bitfield(u8, order = Msb))]
354#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u8, order = Lsb))]
355pub struct IntSource {
356    /// Differential pressure high event (1 bit)
357    /// (0: no interrupt; 1: high differential pressure event occurred)
358    #[bits(1)]
359    pub ph: u8,
360    /// Differential pressure low event (1 bit)
361    /// (0: no interrupt; 1: low differential pressure event occurred)
362    #[bits(1)]
363    pub pl: u8,
364    /// Interrupt active (1 bit)
365    /// (0: no interrupt generated; 1: one or more interrupt events generated)
366    #[bits(1)]
367    pub ia: u8,
368    #[bits(4, access = RO)]
369    pub not_used_01: u8,
370    /// Boot phase indication (1 bit)
371    /// (0: boot phase not running; 1: boot phase running)
372    #[bits(1)]
373    pub boot_on: u8,
374}
375
376/// FIFO_STATUS1 (0x25)
377///
378/// FIFO status register (read only)
379/// Contains the number of unread samples stored in the FIFO buffer.
380/// Value 0x00 means FIFO empty; 0x80 means FIFO full with 128 unread samples.
381#[register(address = Reg::FifoStatus1, access_type = "Lps22df<B, T, OnState>")]
382#[cfg_attr(feature = "bit_order_msb", bitfield(u8, order = Msb))]
383#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u8, order = Lsb))]
384pub struct FifoStatus1 {
385    #[bits(8)]
386    pub fss: u8,
387}
388
389/// FIFO_STATUS2 (0x26)
390///
391/// FIFO status register (read only)
392#[register(address = Reg::FifoStatus2, access_type = "Lps22df<B, T, OnState>")]
393#[cfg_attr(feature = "bit_order_msb", bitfield(u8, order = Msb))]
394#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u8, order = Lsb))]
395pub struct FifoStatus2 {
396    #[bits(5, access = RO)]
397    pub not_used_01: u8,
398    /// FIFO full interrupt active (1 bit)
399    /// (0: FIFO not full; 1: FIFO full)
400    #[bits(1)]
401    pub fifo_full_ia: u8,
402    /// FIFO overrun interrupt active (1 bit)
403    /// (0: no overrun; 1: FIFO slot overwritten)
404    #[bits(1)]
405    pub fifo_ovr_ia: u8,
406    /// FIFO watermark interrupt active (1 bit)
407    /// (0: FIFO below watermark; 1: FIFO equal or above watermark)
408    #[bits(1)]
409    pub fifo_wtm_ia: u8,
410}
411
412/// STATUS (0x27)
413///
414/// Status register (read only)
415#[register(address = Reg::Status, access_type = "Lps22df<B, T, OnState>")]
416#[cfg_attr(feature = "bit_order_msb", bitfield(u8, order = Msb))]
417#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u8, order = Lsb))]
418pub struct Status {
419    /// Pressure data available (1 bit)
420    /// (0: new data not available; 1: new pressure data generated)
421    #[bits(1)]
422    pub p_da: u8,
423    /// Temperature data available (1 bit)
424    /// (0: new data not available; 1: new temperature data generated)
425    #[bits(1)]
426    pub t_da: u8,
427    #[bits(2, access = RO)]
428    pub not_used_01: u8,
429    /// Pressure data overrun (1 bit)
430    /// (0: no overrun; 1: new data overwritten previous data)
431    #[bits(1)]
432    pub p_or: u8,
433    /// Temperature data overrun (1 bit)
434    /// (0: no overrun; 1: new data overwritten previous data)
435    #[bits(1)]
436    pub t_or: u8,
437    #[bits(2, access = RO)]
438    pub not_used_02: u8,
439}
440
441/// PRESS_OUT_XL - PRESS_OUT_L - PRESS_OUT_H (0x28 - 0x2A)
442///
443/// The pressure output value is a 24-bit data that contains the measured pressure. It is composed of
444/// PRESS_OUT_H (2Ah), PRESS_OUT_L (29h) and PRESS_OUT_XL (28h). The value is expressed as two's
445/// complement.
446/// The output pressure register PRESS_OUT is provided as the difference between the measured pressure and the
447/// content of the register RPDS (1Ah, 1Bh).
448#[register(address = Reg::PressOutXl, access_type = "Lps22df<B, T, OnState>")]
449#[cfg_attr(feature = "bit_order_msb", bitfield(u32, order = Msb))]
450#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u32, order = Lsb))]
451pub struct PressOut {
452    #[offset_before(8)]
453    #[bits(32)]
454    pub pressure: i32,
455}
456
457/// TEMP_OUT_L - TEMP_OUT_H (0x2B - 0x2C)
458///
459/// The temperature output value is 16-bit data that contains the measured temperature.
460/// The value is expressed as two’s complement.
461/// This register contains the temperature value and the resolution is: 1LSB = 0.01°C
462#[register(address = Reg::TempOutL, access_type = "Lps22df<B, T, OnState>", override_type = u16)]
463#[cfg_attr(feature = "bit_order_msb", bitfield(u16, order = Msb))]
464#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u16, order = Lsb))]
465pub struct TempOut {
466    #[bits(16)]
467    pub temp_c: i16,
468}
469
470/// FIFO_DATA_OUT_PRESS_XL - FIFO_DATA_OUT_PRESS_L - FIFO_DATA_OUT_PRESS_H (0x78 - 0x7A)
471///
472/// The temperature output value is 16-bit data that contains the measured temperature.
473/// The value is expressed as two’s complement.
474/// This register contains the temperature value and the resolution is: 1LSB = 0.01°C
475#[register(address = Reg::FifoDataOutPressXl, access_type = "Lps22df<B, T, OnState>")]
476#[cfg_attr(feature = "bit_order_msb", bitfield(u32, order = Msb))]
477#[cfg_attr(not(feature = "bit_order_msb"), bitfield(u32, order = Lsb))]
478pub struct FifoDataOutPress {
479    #[offset_before(8)]
480    #[bits(32)]
481    pub pressure: i32,
482}
483
484/// Interface selection options for the device communication interface.
485#[repr(u8)]
486#[derive(Clone, Copy, PartialEq, Default, TryFrom)]
487#[try_from(repr)]
488pub enum Interface {
489    /// Hardware selects interface (default)
490    #[default]
491    SelByHw = 0x00,
492    /// SPI 4-wire interface
493    Spi4w = 0x02,
494    /// SPI 3-wire interface
495    Spi3w = 0x03,
496    /// Interrupt pin enabled on MIPI I3C interface
497    IntPinOnI3c = 0x04,
498}
499
500/// Filter configuration for antispike filters on I3C bus.
501#[repr(u8)]
502#[derive(Clone, Copy, PartialEq, Default, TryFrom)]
503#[try_from(repr)]
504pub enum Filter {
505    /// Antispike filter managed automatically by protocol (default)
506    #[default]
507    FilterAuto = 0x00,
508    /// Antispike filter always enabled
509    FilterAlwaysOn = 0x01,
510}
511
512/// I3C In-Band Interrupt (IBI) bus available time selection.
513#[repr(u8)]
514#[derive(Clone, Copy, PartialEq, Default, TryFrom)]
515#[try_from(repr)]
516pub enum I3cIbiTime {
517    /// Bus available time 50 μs (default)
518    #[default]
519    Ibi50us = 0x0,
520    /// Bus available time 2 μs
521    Ibi2us = 0x1,
522    /// Bus available time 1 ms
523    Ibi1ms = 0x2,
524    /// Bus available time 25 ms
525    Ibi25ms = 0x3,
526}
527
528/// Device initialization states.
529#[repr(u8)]
530#[derive(Clone, Copy, PartialEq, TryFrom)]
531#[try_from(repr)]
532pub enum Init {
533    /// Driver ready state
534    DrvRdy = 0x00,
535    /// Boot phase running
536    Boot = 0x01,
537    /// Reset state
538    Reset = 0x02,
539}
540
541/// Output Data Rate (ODR) settings for pressure and temperature data.
542#[repr(u8)]
543#[derive(Clone, Copy, PartialEq, Default, TryFrom)]
544#[try_from(repr)]
545pub enum Odr {
546    /// One-shot mode (default)
547    #[default]
548    OneShot = 0x00,
549    /// 1 Hz output data rate
550    _1hz = 0x01,
551    /// 4 Hz output data rate
552    _4hz = 0x02,
553    /// 10 Hz output data rate
554    _10hz = 0x03,
555    /// 25 Hz output data rate
556    _25hz = 0x04,
557    /// 50 Hz output data rate
558    _50hz = 0x05,
559    /// 75 Hz output data rate
560    _75hz = 0x06,
561    /// 100 Hz output data rate
562    _100hz = 0x07,
563    /// 200 Hz output data rate
564    _200hz = 0x08,
565}
566
567/// Averaging settings for pressure and temperature measurements.
568#[repr(u8)]
569#[derive(Clone, Copy, PartialEq, Default, TryFrom)]
570#[try_from(repr)]
571pub enum Avg {
572    /// Average over 4 samples (default)
573    #[default]
574    _4 = 0,
575    /// Average over 8 samples
576    _8 = 1,
577    /// Average over 16 samples
578    _16 = 2,
579    /// Average over 32 samples
580    _32 = 3,
581    /// Average over 64 samples
582    _64 = 4,
583    /// Average over 128 samples
584    _128 = 5,
585    /// Average over 256 samples
586    _256 = 6,
587    /// Average over 512 samples
588    _512 = 7,
589}
590
591/// Low-pass filter configuration options.
592#[repr(u8)]
593#[derive(Clone, Copy, PartialEq, Default, TryFrom)]
594#[try_from(repr)]
595pub enum LowPassFilter {
596    /// Low-pass filter disabled (default)
597    #[default]
598    Disable = 0,
599    /// Low-pass filter cutoff frequency at ODR/4
600    OdrDiv4 = 1,
601    /// Low-pass filter cutoff frequency at ODR/9
602    OdrDiv9 = 3,
603}
604
605/// FIFO operating modes.
606#[repr(u8)]
607#[derive(Clone, Copy, PartialEq, Default, TryFrom)]
608#[try_from(repr)]
609pub enum Operation {
610    /// Bypass mode (FIFO disabled)
611    #[default]
612    Bypass = 0,
613    /// FIFO mode (store data until full)
614    Fifo = 1,
615    /// Continuous (dynamic-stream) mode
616    Stream = 2,
617    /// Continuous (dynamic-stream) to FIFO mode
618    StreamToFifo = 7,
619    /// Bypass to continuous (dynamic-stream) mode
620    BypassToStream = 6,
621    /// Bypass to FIFO mode
622    BypassToFifo = 5,
623}
624
625/// Reference application modes for pressure offset and interrupt generation.
626#[repr(u8)]
627#[derive(Clone, Copy, PartialEq, TryFrom)]
628#[try_from(repr)]
629pub enum ApplyRef {
630    /// Apply reference to output and interrupt generation
631    OutAndInterrupt = 0,
632    /// Apply reference only to interrupt generation
633    OnlyInterrupt = 1,
634    /// Reset reference registers
635    RstRefs = 2,
636}
637
638/// Represents the FIFO event types.
639///
640/// # Variants
641///
642/// - `FifoEvWtm`: FIFO watermark event.
643/// - `FifoEvFull`: FIFO full event.
644///
645/// # Description
646///
647/// This enum is used to specify the FIFO event type, allowing for watermark or full event configurations.
648#[repr(u8)]
649#[derive(Clone, Copy, PartialEq, Default, TryFrom)]
650#[try_from(repr)]
651pub enum FifoEvent {
652    #[default]
653    Wtm = 0x0,
654    Full = 0x1,
655}
656
657#[derive(Default)]
658pub struct BusMode {
659    pub interface: Interface,
660    pub filter: Filter,
661    pub i3c_ibi_time: I3cIbiTime,
662}
663
664pub struct Stat {
665    pub sw_reset: u8,
666    pub boot: u8,
667    pub drdy_pres: u8,
668    pub drdy_temp: u8,
669    pub ovr_pres: u8,
670    pub ovr_temp: u8,
671    pub end_meas: u8,
672    pub ref_done: u8,
673}
674
675pub struct PinConf {
676    pub int_push_pull: u8,
677    pub int_pull_down: u8,
678    pub sdo_pull_up: u8,
679    pub sda_pull_up: u8,
680    pub cs_pull_up: u8,
681}
682
683pub struct AllSources {
684    pub drdy_pres: u8,
685    pub drdy_temp: u8,
686    pub over_pres: u8,
687    pub under_pres: u8,
688    pub thrsld_pres: u8,
689    pub fifo_full: u8,
690    pub fifo_ovr: u8,
691    pub fifo_th: u8,
692}
693
694#[derive(Default)]
695pub struct Md {
696    pub odr: Odr,
697    pub avg: Avg,
698    pub lpf: LowPassFilter,
699}
700
701#[derive(Copy, Clone)]
702pub struct FifoData {
703    pub hpa: f32,
704    pub raw: i32,
705}
706
707pub struct IntMode {
708    pub int_latched: u8,
709    pub active_low: u8,
710    pub drdy_latched: u8,
711}
712
713#[derive(Default)]
714pub struct PinIntRoute {
715    pub drdy_pres: u8,
716    pub fifo_th: u8,
717    pub fifo_ovr: u8,
718    pub fifo_full: u8,
719}
720
721pub struct IntThMd {
722    pub threshold: u16,
723    pub over_th: u8,
724    pub under_th: u8,
725}
726
727pub struct RefMd {
728    pub apply_ref: ApplyRef,
729    pub get_ref: u8,
730}
731
732#[derive(Copy, Clone)]
733pub struct Pressure {
734    pub hpa: f32,
735    pub raw: i32, // 32-bit signed-left aligned format
736}
737#[derive(Copy, Clone)]
738pub struct Heat {
739    pub deg_c: f32,
740    pub raw: i16,
741}
742#[derive(Copy, Clone)]
743pub struct Data {
744    pub pressure: Pressure,
745    pub heat: Heat,
746}
lps22df_rs/register/main.rs

lps22df_rs/register/
main.rs
