lpc845_pac/syscon/
syspllctrl.rs

1#[doc = "Register `SYSPLLCTRL` reader"]
2pub struct R(crate::R<SYSPLLCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SYSPLLCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SYSPLLCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SYSPLLCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SYSPLLCTRL` writer"]
17pub struct W(crate::W<SYSPLLCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SYSPLLCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SYSPLLCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SYSPLLCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `MSEL` reader - Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32"]
38pub struct MSEL_R(crate::FieldReader<u8, u8>);
39impl MSEL_R {
40    pub(crate) fn new(bits: u8) -> Self {
41        MSEL_R(crate::FieldReader::new(bits))
42    }
43}
44impl core::ops::Deref for MSEL_R {
45    type Target = crate::FieldReader<u8, u8>;
46    #[inline(always)]
47    fn deref(&self) -> &Self::Target {
48        &self.0
49    }
50}
51#[doc = "Field `MSEL` writer - Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32"]
52pub struct MSEL_W<'a> {
53    w: &'a mut W,
54}
55impl<'a> MSEL_W<'a> {
56    #[doc = r"Writes raw bits to the field"]
57    #[inline(always)]
58    pub unsafe fn bits(self, value: u8) -> &'a mut W {
59        self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f);
60        self.w
61    }
62}
63#[doc = "Post divider ratio P. The division ratio is 2 x P.\n\nValue on reset: 0"]
64#[derive(Clone, Copy, Debug, PartialEq)]
65#[repr(u8)]
66pub enum PSEL_A {
67    #[doc = "0: P = 1"]
68    PSEL_0 = 0,
69    #[doc = "1: P = 2"]
70    PSEL_1 = 1,
71    #[doc = "2: P = 4"]
72    PSEL_2 = 2,
73    #[doc = "3: P = 8"]
74    PSEL_3 = 3,
75}
76impl From<PSEL_A> for u8 {
77    #[inline(always)]
78    fn from(variant: PSEL_A) -> Self {
79        variant as _
80    }
81}
82#[doc = "Field `PSEL` reader - Post divider ratio P. The division ratio is 2 x P."]
83pub struct PSEL_R(crate::FieldReader<u8, PSEL_A>);
84impl PSEL_R {
85    pub(crate) fn new(bits: u8) -> Self {
86        PSEL_R(crate::FieldReader::new(bits))
87    }
88    #[doc = r"Get enumerated values variant"]
89    #[inline(always)]
90    pub fn variant(&self) -> PSEL_A {
91        match self.bits {
92            0 => PSEL_A::PSEL_0,
93            1 => PSEL_A::PSEL_1,
94            2 => PSEL_A::PSEL_2,
95            3 => PSEL_A::PSEL_3,
96            _ => unreachable!(),
97        }
98    }
99    #[doc = "Checks if the value of the field is `PSEL_0`"]
100    #[inline(always)]
101    pub fn is_psel_0(&self) -> bool {
102        **self == PSEL_A::PSEL_0
103    }
104    #[doc = "Checks if the value of the field is `PSEL_1`"]
105    #[inline(always)]
106    pub fn is_psel_1(&self) -> bool {
107        **self == PSEL_A::PSEL_1
108    }
109    #[doc = "Checks if the value of the field is `PSEL_2`"]
110    #[inline(always)]
111    pub fn is_psel_2(&self) -> bool {
112        **self == PSEL_A::PSEL_2
113    }
114    #[doc = "Checks if the value of the field is `PSEL_3`"]
115    #[inline(always)]
116    pub fn is_psel_3(&self) -> bool {
117        **self == PSEL_A::PSEL_3
118    }
119}
120impl core::ops::Deref for PSEL_R {
121    type Target = crate::FieldReader<u8, PSEL_A>;
122    #[inline(always)]
123    fn deref(&self) -> &Self::Target {
124        &self.0
125    }
126}
127#[doc = "Field `PSEL` writer - Post divider ratio P. The division ratio is 2 x P."]
128pub struct PSEL_W<'a> {
129    w: &'a mut W,
130}
131impl<'a> PSEL_W<'a> {
132    #[doc = r"Writes `variant` to the field"]
133    #[inline(always)]
134    pub fn variant(self, variant: PSEL_A) -> &'a mut W {
135        self.bits(variant.into())
136    }
137    #[doc = "P = 1"]
138    #[inline(always)]
139    pub fn psel_0(self) -> &'a mut W {
140        self.variant(PSEL_A::PSEL_0)
141    }
142    #[doc = "P = 2"]
143    #[inline(always)]
144    pub fn psel_1(self) -> &'a mut W {
145        self.variant(PSEL_A::PSEL_1)
146    }
147    #[doc = "P = 4"]
148    #[inline(always)]
149    pub fn psel_2(self) -> &'a mut W {
150        self.variant(PSEL_A::PSEL_2)
151    }
152    #[doc = "P = 8"]
153    #[inline(always)]
154    pub fn psel_3(self) -> &'a mut W {
155        self.variant(PSEL_A::PSEL_3)
156    }
157    #[doc = r"Writes raw bits to the field"]
158    #[inline(always)]
159    pub fn bits(self, value: u8) -> &'a mut W {
160        self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5);
161        self.w
162    }
163}
164impl R {
165    #[doc = "Bits 0:4 - Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32"]
166    #[inline(always)]
167    pub fn msel(&self) -> MSEL_R {
168        MSEL_R::new((self.bits & 0x1f) as u8)
169    }
170    #[doc = "Bits 5:6 - Post divider ratio P. The division ratio is 2 x P."]
171    #[inline(always)]
172    pub fn psel(&self) -> PSEL_R {
173        PSEL_R::new(((self.bits >> 5) & 0x03) as u8)
174    }
175}
176impl W {
177    #[doc = "Bits 0:4 - Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32"]
178    #[inline(always)]
179    pub fn msel(&mut self) -> MSEL_W {
180        MSEL_W { w: self }
181    }
182    #[doc = "Bits 5:6 - Post divider ratio P. The division ratio is 2 x P."]
183    #[inline(always)]
184    pub fn psel(&mut self) -> PSEL_W {
185        PSEL_W { w: self }
186    }
187    #[doc = "Writes raw bits to the register."]
188    #[inline(always)]
189    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
190        self.0.bits(bits);
191        self
192    }
193}
194#[doc = "PLL control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syspllctrl](index.html) module"]
195pub struct SYSPLLCTRL_SPEC;
196impl crate::RegisterSpec for SYSPLLCTRL_SPEC {
197    type Ux = u32;
198}
199#[doc = "`read()` method returns [syspllctrl::R](R) reader structure"]
200impl crate::Readable for SYSPLLCTRL_SPEC {
201    type Reader = R;
202}
203#[doc = "`write(|w| ..)` method takes [syspllctrl::W](W) writer structure"]
204impl crate::Writable for SYSPLLCTRL_SPEC {
205    type Writer = W;
206}
207#[doc = "`reset()` method sets SYSPLLCTRL to value 0"]
208impl crate::Resettable for SYSPLLCTRL_SPEC {
209    #[inline(always)]
210    fn reset_value() -> Self::Ux {
211        0
212    }
213}
lpc845_pac/syscon/syspllctrl.rs

lpc845_pac/syscon/
syspllctrl.rs
