lpc845_pac/syscon/
fclksel.rs1#[doc = "Register `FCLKSEL[%s]` reader"]
2pub struct R(crate::R<FCLKSEL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<FCLKSEL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<FCLKSEL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<FCLKSEL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `FCLKSEL[%s]` writer"]
17pub struct W(crate::W<FCLKSEL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<FCLKSEL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<FCLKSEL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<FCLKSEL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Peripheral clock source\n\nValue on reset: 7"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum SEL_A {
41 #[doc = "0: FRO"]
42 FRO = 0,
43 #[doc = "1: main clock"]
44 MAIN_CLK = 1,
45 #[doc = "2: Frg0clk"]
46 FRG0CLK = 2,
47 #[doc = "3: Frg1clk"]
48 FRG1CLK = 3,
49 #[doc = "4: FRO_DIV"]
50 FRO_DIV = 4,
51 #[doc = "7: none"]
52 NONE = 7,
53}
54impl From<SEL_A> for u8 {
55 #[inline(always)]
56 fn from(variant: SEL_A) -> Self {
57 variant as _
58 }
59}
60#[doc = "Field `SEL` reader - Peripheral clock source"]
61pub struct SEL_R(crate::FieldReader<u8, SEL_A>);
62impl SEL_R {
63 pub(crate) fn new(bits: u8) -> Self {
64 SEL_R(crate::FieldReader::new(bits))
65 }
66 #[doc = r"Get enumerated values variant"]
67 #[inline(always)]
68 pub fn variant(&self) -> Option<SEL_A> {
69 match self.bits {
70 0 => Some(SEL_A::FRO),
71 1 => Some(SEL_A::MAIN_CLK),
72 2 => Some(SEL_A::FRG0CLK),
73 3 => Some(SEL_A::FRG1CLK),
74 4 => Some(SEL_A::FRO_DIV),
75 7 => Some(SEL_A::NONE),
76 _ => None,
77 }
78 }
79 #[doc = "Checks if the value of the field is `FRO`"]
80 #[inline(always)]
81 pub fn is_fro(&self) -> bool {
82 **self == SEL_A::FRO
83 }
84 #[doc = "Checks if the value of the field is `MAIN_CLK`"]
85 #[inline(always)]
86 pub fn is_main_clk(&self) -> bool {
87 **self == SEL_A::MAIN_CLK
88 }
89 #[doc = "Checks if the value of the field is `FRG0CLK`"]
90 #[inline(always)]
91 pub fn is_frg0clk(&self) -> bool {
92 **self == SEL_A::FRG0CLK
93 }
94 #[doc = "Checks if the value of the field is `FRG1CLK`"]
95 #[inline(always)]
96 pub fn is_frg1clk(&self) -> bool {
97 **self == SEL_A::FRG1CLK
98 }
99 #[doc = "Checks if the value of the field is `FRO_DIV`"]
100 #[inline(always)]
101 pub fn is_fro_div(&self) -> bool {
102 **self == SEL_A::FRO_DIV
103 }
104 #[doc = "Checks if the value of the field is `NONE`"]
105 #[inline(always)]
106 pub fn is_none(&self) -> bool {
107 **self == SEL_A::NONE
108 }
109}
110impl core::ops::Deref for SEL_R {
111 type Target = crate::FieldReader<u8, SEL_A>;
112 #[inline(always)]
113 fn deref(&self) -> &Self::Target {
114 &self.0
115 }
116}
117#[doc = "Field `SEL` writer - Peripheral clock source"]
118pub struct SEL_W<'a> {
119 w: &'a mut W,
120}
121impl<'a> SEL_W<'a> {
122 #[doc = r"Writes `variant` to the field"]
123 #[inline(always)]
124 pub fn variant(self, variant: SEL_A) -> &'a mut W {
125 unsafe { self.bits(variant.into()) }
126 }
127 #[doc = "FRO"]
128 #[inline(always)]
129 pub fn fro(self) -> &'a mut W {
130 self.variant(SEL_A::FRO)
131 }
132 #[doc = "main clock"]
133 #[inline(always)]
134 pub fn main_clk(self) -> &'a mut W {
135 self.variant(SEL_A::MAIN_CLK)
136 }
137 #[doc = "Frg0clk"]
138 #[inline(always)]
139 pub fn frg0clk(self) -> &'a mut W {
140 self.variant(SEL_A::FRG0CLK)
141 }
142 #[doc = "Frg1clk"]
143 #[inline(always)]
144 pub fn frg1clk(self) -> &'a mut W {
145 self.variant(SEL_A::FRG1CLK)
146 }
147 #[doc = "FRO_DIV"]
148 #[inline(always)]
149 pub fn fro_div(self) -> &'a mut W {
150 self.variant(SEL_A::FRO_DIV)
151 }
152 #[doc = "none"]
153 #[inline(always)]
154 pub fn none(self) -> &'a mut W {
155 self.variant(SEL_A::NONE)
156 }
157 #[doc = r"Writes raw bits to the field"]
158 #[inline(always)]
159 pub unsafe fn bits(self, value: u8) -> &'a mut W {
160 self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07);
161 self.w
162 }
163}
164impl R {
165 #[doc = "Bits 0:2 - Peripheral clock source"]
166 #[inline(always)]
167 pub fn sel(&self) -> SEL_R {
168 SEL_R::new((self.bits & 0x07) as u8)
169 }
170}
171impl W {
172 #[doc = "Bits 0:2 - Peripheral clock source"]
173 #[inline(always)]
174 pub fn sel(&mut self) -> SEL_W {
175 SEL_W { w: self }
176 }
177 #[doc = "Writes raw bits to the register."]
178 #[inline(always)]
179 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
180 self.0.bits(bits);
181 self
182 }
183}
184#[doc = "peripheral clock source select register. FCLK0SEL~FCLK4SEL are for UART0~UART4 clock source select register. FCLK5SEL~FCLK8SEL are for I2C0~I2C3 clock source select register. FCLK9SEL~FCLK10SEL are for SPI0~SPI1 clock source select register.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fclksel](index.html) module"]
185pub struct FCLKSEL_SPEC;
186impl crate::RegisterSpec for FCLKSEL_SPEC {
187 type Ux = u32;
188}
189#[doc = "`read()` method returns [fclksel::R](R) reader structure"]
190impl crate::Readable for FCLKSEL_SPEC {
191 type Reader = R;
192}
193#[doc = "`write(|w| ..)` method takes [fclksel::W](W) writer structure"]
194impl crate::Writable for FCLKSEL_SPEC {
195 type Writer = W;
196}
197#[doc = "`reset()` method sets FCLKSEL[%s]
198to value 0x07"]
199impl crate::Resettable for FCLKSEL_SPEC {
200 #[inline(always)]
201 fn reset_value() -> Self::Ux {
202 0x07
203 }
204}