1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CTRL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CTRL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `MATCHSEL` reader - Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running."]
38pub struct MATCHSEL_R(crate::FieldReader<u8, u8>);
39impl MATCHSEL_R {
40 pub(crate) fn new(bits: u8) -> Self {
41 MATCHSEL_R(crate::FieldReader::new(bits))
42 }
43}
44impl core::ops::Deref for MATCHSEL_R {
45 type Target = crate::FieldReader<u8, u8>;
46 #[inline(always)]
47 fn deref(&self) -> &Self::Target {
48 &self.0
49 }
50}
51#[doc = "Field `MATCHSEL` writer - Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running."]
52pub struct MATCHSEL_W<'a> {
53 w: &'a mut W,
54}
55impl<'a> MATCHSEL_W<'a> {
56 #[doc = r"Writes raw bits to the field"]
57 #[inline(always)]
58 pub unsafe fn bits(self, value: u8) -> &'a mut W {
59 self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f);
60 self.w
61 }
62}
63#[doc = "Select L/H counter. Do not set this bit if UNIFY = 1.\n\nValue on reset: 0"]
64#[derive(Clone, Copy, Debug, PartialEq)]
65pub enum HEVENT_A {
66 #[doc = "0: Selects the L state and the L match register selected by MATCHSEL."]
67 L_COUNTER = 0,
68 #[doc = "1: Selects the H state and the H match register selected by MATCHSEL."]
69 H_COUNTER = 1,
70}
71impl From<HEVENT_A> for bool {
72 #[inline(always)]
73 fn from(variant: HEVENT_A) -> Self {
74 variant as u8 != 0
75 }
76}
77#[doc = "Field `HEVENT` reader - Select L/H counter. Do not set this bit if UNIFY = 1."]
78pub struct HEVENT_R(crate::FieldReader<bool, HEVENT_A>);
79impl HEVENT_R {
80 pub(crate) fn new(bits: bool) -> Self {
81 HEVENT_R(crate::FieldReader::new(bits))
82 }
83 #[doc = r"Get enumerated values variant"]
84 #[inline(always)]
85 pub fn variant(&self) -> HEVENT_A {
86 match self.bits {
87 false => HEVENT_A::L_COUNTER,
88 true => HEVENT_A::H_COUNTER,
89 }
90 }
91 #[doc = "Checks if the value of the field is `L_COUNTER`"]
92 #[inline(always)]
93 pub fn is_l_counter(&self) -> bool {
94 **self == HEVENT_A::L_COUNTER
95 }
96 #[doc = "Checks if the value of the field is `H_COUNTER`"]
97 #[inline(always)]
98 pub fn is_h_counter(&self) -> bool {
99 **self == HEVENT_A::H_COUNTER
100 }
101}
102impl core::ops::Deref for HEVENT_R {
103 type Target = crate::FieldReader<bool, HEVENT_A>;
104 #[inline(always)]
105 fn deref(&self) -> &Self::Target {
106 &self.0
107 }
108}
109#[doc = "Field `HEVENT` writer - Select L/H counter. Do not set this bit if UNIFY = 1."]
110pub struct HEVENT_W<'a> {
111 w: &'a mut W,
112}
113impl<'a> HEVENT_W<'a> {
114 #[doc = r"Writes `variant` to the field"]
115 #[inline(always)]
116 pub fn variant(self, variant: HEVENT_A) -> &'a mut W {
117 self.bit(variant.into())
118 }
119 #[doc = "Selects the L state and the L match register selected by MATCHSEL."]
120 #[inline(always)]
121 pub fn l_counter(self) -> &'a mut W {
122 self.variant(HEVENT_A::L_COUNTER)
123 }
124 #[doc = "Selects the H state and the H match register selected by MATCHSEL."]
125 #[inline(always)]
126 pub fn h_counter(self) -> &'a mut W {
127 self.variant(HEVENT_A::H_COUNTER)
128 }
129 #[doc = r"Sets the field bit"]
130 #[inline(always)]
131 pub fn set_bit(self) -> &'a mut W {
132 self.bit(true)
133 }
134 #[doc = r"Clears the field bit"]
135 #[inline(always)]
136 pub fn clear_bit(self) -> &'a mut W {
137 self.bit(false)
138 }
139 #[doc = r"Writes raw bits to the field"]
140 #[inline(always)]
141 pub fn bit(self, value: bool) -> &'a mut W {
142 self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
143 self.w
144 }
145}
146#[doc = "Input/output select\n\nValue on reset: 0"]
147#[derive(Clone, Copy, Debug, PartialEq)]
148pub enum OUTSEL_A {
149 #[doc = "0: Selects the inputs selected by IOSEL."]
150 INPUT = 0,
151 #[doc = "1: Selects the outputs selected by IOSEL."]
152 OUTPUT = 1,
153}
154impl From<OUTSEL_A> for bool {
155 #[inline(always)]
156 fn from(variant: OUTSEL_A) -> Self {
157 variant as u8 != 0
158 }
159}
160#[doc = "Field `OUTSEL` reader - Input/output select"]
161pub struct OUTSEL_R(crate::FieldReader<bool, OUTSEL_A>);
162impl OUTSEL_R {
163 pub(crate) fn new(bits: bool) -> Self {
164 OUTSEL_R(crate::FieldReader::new(bits))
165 }
166 #[doc = r"Get enumerated values variant"]
167 #[inline(always)]
168 pub fn variant(&self) -> OUTSEL_A {
169 match self.bits {
170 false => OUTSEL_A::INPUT,
171 true => OUTSEL_A::OUTPUT,
172 }
173 }
174 #[doc = "Checks if the value of the field is `INPUT`"]
175 #[inline(always)]
176 pub fn is_input(&self) -> bool {
177 **self == OUTSEL_A::INPUT
178 }
179 #[doc = "Checks if the value of the field is `OUTPUT`"]
180 #[inline(always)]
181 pub fn is_output(&self) -> bool {
182 **self == OUTSEL_A::OUTPUT
183 }
184}
185impl core::ops::Deref for OUTSEL_R {
186 type Target = crate::FieldReader<bool, OUTSEL_A>;
187 #[inline(always)]
188 fn deref(&self) -> &Self::Target {
189 &self.0
190 }
191}
192#[doc = "Field `OUTSEL` writer - Input/output select"]
193pub struct OUTSEL_W<'a> {
194 w: &'a mut W,
195}
196impl<'a> OUTSEL_W<'a> {
197 #[doc = r"Writes `variant` to the field"]
198 #[inline(always)]
199 pub fn variant(self, variant: OUTSEL_A) -> &'a mut W {
200 self.bit(variant.into())
201 }
202 #[doc = "Selects the inputs selected by IOSEL."]
203 #[inline(always)]
204 pub fn input(self) -> &'a mut W {
205 self.variant(OUTSEL_A::INPUT)
206 }
207 #[doc = "Selects the outputs selected by IOSEL."]
208 #[inline(always)]
209 pub fn output(self) -> &'a mut W {
210 self.variant(OUTSEL_A::OUTPUT)
211 }
212 #[doc = r"Sets the field bit"]
213 #[inline(always)]
214 pub fn set_bit(self) -> &'a mut W {
215 self.bit(true)
216 }
217 #[doc = r"Clears the field bit"]
218 #[inline(always)]
219 pub fn clear_bit(self) -> &'a mut W {
220 self.bit(false)
221 }
222 #[doc = r"Writes raw bits to the field"]
223 #[inline(always)]
224 pub fn bit(self, value: bool) -> &'a mut W {
225 self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
226 self.w
227 }
228}
229#[doc = "Field `IOSEL` reader - Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event."]
230pub struct IOSEL_R(crate::FieldReader<u8, u8>);
231impl IOSEL_R {
232 pub(crate) fn new(bits: u8) -> Self {
233 IOSEL_R(crate::FieldReader::new(bits))
234 }
235}
236impl core::ops::Deref for IOSEL_R {
237 type Target = crate::FieldReader<u8, u8>;
238 #[inline(always)]
239 fn deref(&self) -> &Self::Target {
240 &self.0
241 }
242}
243#[doc = "Field `IOSEL` writer - Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event."]
244pub struct IOSEL_W<'a> {
245 w: &'a mut W,
246}
247impl<'a> IOSEL_W<'a> {
248 #[doc = r"Writes raw bits to the field"]
249 #[inline(always)]
250 pub unsafe fn bits(self, value: u8) -> &'a mut W {
251 self.w.bits = (self.w.bits & !(0x0f << 6)) | ((value as u32 & 0x0f) << 6);
252 self.w
253 }
254}
255#[doc = "Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .\n\nValue on reset: 0"]
256#[derive(Clone, Copy, Debug, PartialEq)]
257#[repr(u8)]
258pub enum IOCOND_A {
259 #[doc = "0: LOW"]
260 LOW = 0,
261 #[doc = "1: Rise"]
262 RISE = 1,
263 #[doc = "2: Fall"]
264 FALL = 2,
265 #[doc = "3: HIGH"]
266 HIGH = 3,
267}
268impl From<IOCOND_A> for u8 {
269 #[inline(always)]
270 fn from(variant: IOCOND_A) -> Self {
271 variant as _
272 }
273}
274#[doc = "Field `IOCOND` reader - Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ."]
275pub struct IOCOND_R(crate::FieldReader<u8, IOCOND_A>);
276impl IOCOND_R {
277 pub(crate) fn new(bits: u8) -> Self {
278 IOCOND_R(crate::FieldReader::new(bits))
279 }
280 #[doc = r"Get enumerated values variant"]
281 #[inline(always)]
282 pub fn variant(&self) -> IOCOND_A {
283 match self.bits {
284 0 => IOCOND_A::LOW,
285 1 => IOCOND_A::RISE,
286 2 => IOCOND_A::FALL,
287 3 => IOCOND_A::HIGH,
288 _ => unreachable!(),
289 }
290 }
291 #[doc = "Checks if the value of the field is `LOW`"]
292 #[inline(always)]
293 pub fn is_low(&self) -> bool {
294 **self == IOCOND_A::LOW
295 }
296 #[doc = "Checks if the value of the field is `RISE`"]
297 #[inline(always)]
298 pub fn is_rise(&self) -> bool {
299 **self == IOCOND_A::RISE
300 }
301 #[doc = "Checks if the value of the field is `FALL`"]
302 #[inline(always)]
303 pub fn is_fall(&self) -> bool {
304 **self == IOCOND_A::FALL
305 }
306 #[doc = "Checks if the value of the field is `HIGH`"]
307 #[inline(always)]
308 pub fn is_high(&self) -> bool {
309 **self == IOCOND_A::HIGH
310 }
311}
312impl core::ops::Deref for IOCOND_R {
313 type Target = crate::FieldReader<u8, IOCOND_A>;
314 #[inline(always)]
315 fn deref(&self) -> &Self::Target {
316 &self.0
317 }
318}
319#[doc = "Field `IOCOND` writer - Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ."]
320pub struct IOCOND_W<'a> {
321 w: &'a mut W,
322}
323impl<'a> IOCOND_W<'a> {
324 #[doc = r"Writes `variant` to the field"]
325 #[inline(always)]
326 pub fn variant(self, variant: IOCOND_A) -> &'a mut W {
327 self.bits(variant.into())
328 }
329 #[doc = "LOW"]
330 #[inline(always)]
331 pub fn low(self) -> &'a mut W {
332 self.variant(IOCOND_A::LOW)
333 }
334 #[doc = "Rise"]
335 #[inline(always)]
336 pub fn rise(self) -> &'a mut W {
337 self.variant(IOCOND_A::RISE)
338 }
339 #[doc = "Fall"]
340 #[inline(always)]
341 pub fn fall(self) -> &'a mut W {
342 self.variant(IOCOND_A::FALL)
343 }
344 #[doc = "HIGH"]
345 #[inline(always)]
346 pub fn high(self) -> &'a mut W {
347 self.variant(IOCOND_A::HIGH)
348 }
349 #[doc = r"Writes raw bits to the field"]
350 #[inline(always)]
351 pub fn bits(self, value: u8) -> &'a mut W {
352 self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u32 & 0x03) << 10);
353 self.w
354 }
355}
356#[doc = "Selects how the specified match and I/O condition are used and combined.\n\nValue on reset: 0"]
357#[derive(Clone, Copy, Debug, PartialEq)]
358#[repr(u8)]
359pub enum COMBMODE_A {
360 #[doc = "0: OR. The event occurs when either the specified match or I/O condition occurs."]
361 OR = 0,
362 #[doc = "1: MATCH. Uses the specified match only."]
363 MATCH = 1,
364 #[doc = "2: IO. Uses the specified I/O condition only."]
365 IO = 2,
366 #[doc = "3: AND. The event occurs when the specified match and I/O condition occur simultaneously."]
367 AND = 3,
368}
369impl From<COMBMODE_A> for u8 {
370 #[inline(always)]
371 fn from(variant: COMBMODE_A) -> Self {
372 variant as _
373 }
374}
375#[doc = "Field `COMBMODE` reader - Selects how the specified match and I/O condition are used and combined."]
376pub struct COMBMODE_R(crate::FieldReader<u8, COMBMODE_A>);
377impl COMBMODE_R {
378 pub(crate) fn new(bits: u8) -> Self {
379 COMBMODE_R(crate::FieldReader::new(bits))
380 }
381 #[doc = r"Get enumerated values variant"]
382 #[inline(always)]
383 pub fn variant(&self) -> COMBMODE_A {
384 match self.bits {
385 0 => COMBMODE_A::OR,
386 1 => COMBMODE_A::MATCH,
387 2 => COMBMODE_A::IO,
388 3 => COMBMODE_A::AND,
389 _ => unreachable!(),
390 }
391 }
392 #[doc = "Checks if the value of the field is `OR`"]
393 #[inline(always)]
394 pub fn is_or(&self) -> bool {
395 **self == COMBMODE_A::OR
396 }
397 #[doc = "Checks if the value of the field is `MATCH`"]
398 #[inline(always)]
399 pub fn is_match(&self) -> bool {
400 **self == COMBMODE_A::MATCH
401 }
402 #[doc = "Checks if the value of the field is `IO`"]
403 #[inline(always)]
404 pub fn is_io(&self) -> bool {
405 **self == COMBMODE_A::IO
406 }
407 #[doc = "Checks if the value of the field is `AND`"]
408 #[inline(always)]
409 pub fn is_and(&self) -> bool {
410 **self == COMBMODE_A::AND
411 }
412}
413impl core::ops::Deref for COMBMODE_R {
414 type Target = crate::FieldReader<u8, COMBMODE_A>;
415 #[inline(always)]
416 fn deref(&self) -> &Self::Target {
417 &self.0
418 }
419}
420#[doc = "Field `COMBMODE` writer - Selects how the specified match and I/O condition are used and combined."]
421pub struct COMBMODE_W<'a> {
422 w: &'a mut W,
423}
424impl<'a> COMBMODE_W<'a> {
425 #[doc = r"Writes `variant` to the field"]
426 #[inline(always)]
427 pub fn variant(self, variant: COMBMODE_A) -> &'a mut W {
428 self.bits(variant.into())
429 }
430 #[doc = "OR. The event occurs when either the specified match or I/O condition occurs."]
431 #[inline(always)]
432 pub fn or(self) -> &'a mut W {
433 self.variant(COMBMODE_A::OR)
434 }
435 #[doc = "MATCH. Uses the specified match only."]
436 #[inline(always)]
437 pub fn match_(self) -> &'a mut W {
438 self.variant(COMBMODE_A::MATCH)
439 }
440 #[doc = "IO. Uses the specified I/O condition only."]
441 #[inline(always)]
442 pub fn io(self) -> &'a mut W {
443 self.variant(COMBMODE_A::IO)
444 }
445 #[doc = "AND. The event occurs when the specified match and I/O condition occur simultaneously."]
446 #[inline(always)]
447 pub fn and(self) -> &'a mut W {
448 self.variant(COMBMODE_A::AND)
449 }
450 #[doc = r"Writes raw bits to the field"]
451 #[inline(always)]
452 pub fn bits(self, value: u8) -> &'a mut W {
453 self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u32 & 0x03) << 12);
454 self.w
455 }
456}
457#[doc = "This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.\n\nValue on reset: 0"]
458#[derive(Clone, Copy, Debug, PartialEq)]
459pub enum STATELD_A {
460 #[doc = "0: STATEV value is added into STATE (the carry-out is ignored)."]
461 ADD = 0,
462 #[doc = "1: STATEV value is loaded into STATE."]
463 LOAD = 1,
464}
465impl From<STATELD_A> for bool {
466 #[inline(always)]
467 fn from(variant: STATELD_A) -> Self {
468 variant as u8 != 0
469 }
470}
471#[doc = "Field `STATELD` reader - This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state."]
472pub struct STATELD_R(crate::FieldReader<bool, STATELD_A>);
473impl STATELD_R {
474 pub(crate) fn new(bits: bool) -> Self {
475 STATELD_R(crate::FieldReader::new(bits))
476 }
477 #[doc = r"Get enumerated values variant"]
478 #[inline(always)]
479 pub fn variant(&self) -> STATELD_A {
480 match self.bits {
481 false => STATELD_A::ADD,
482 true => STATELD_A::LOAD,
483 }
484 }
485 #[doc = "Checks if the value of the field is `ADD`"]
486 #[inline(always)]
487 pub fn is_add(&self) -> bool {
488 **self == STATELD_A::ADD
489 }
490 #[doc = "Checks if the value of the field is `LOAD`"]
491 #[inline(always)]
492 pub fn is_load(&self) -> bool {
493 **self == STATELD_A::LOAD
494 }
495}
496impl core::ops::Deref for STATELD_R {
497 type Target = crate::FieldReader<bool, STATELD_A>;
498 #[inline(always)]
499 fn deref(&self) -> &Self::Target {
500 &self.0
501 }
502}
503#[doc = "Field `STATELD` writer - This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state."]
504pub struct STATELD_W<'a> {
505 w: &'a mut W,
506}
507impl<'a> STATELD_W<'a> {
508 #[doc = r"Writes `variant` to the field"]
509 #[inline(always)]
510 pub fn variant(self, variant: STATELD_A) -> &'a mut W {
511 self.bit(variant.into())
512 }
513 #[doc = "STATEV value is added into STATE (the carry-out is ignored)."]
514 #[inline(always)]
515 pub fn add(self) -> &'a mut W {
516 self.variant(STATELD_A::ADD)
517 }
518 #[doc = "STATEV value is loaded into STATE."]
519 #[inline(always)]
520 pub fn load(self) -> &'a mut W {
521 self.variant(STATELD_A::LOAD)
522 }
523 #[doc = r"Sets the field bit"]
524 #[inline(always)]
525 pub fn set_bit(self) -> &'a mut W {
526 self.bit(true)
527 }
528 #[doc = r"Clears the field bit"]
529 #[inline(always)]
530 pub fn clear_bit(self) -> &'a mut W {
531 self.bit(false)
532 }
533 #[doc = r"Writes raw bits to the field"]
534 #[inline(always)]
535 pub fn bit(self, value: bool) -> &'a mut W {
536 self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14);
537 self.w
538 }
539}
540#[doc = "Field `STATEV` reader - This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value."]
541pub struct STATEV_R(crate::FieldReader<u8, u8>);
542impl STATEV_R {
543 pub(crate) fn new(bits: u8) -> Self {
544 STATEV_R(crate::FieldReader::new(bits))
545 }
546}
547impl core::ops::Deref for STATEV_R {
548 type Target = crate::FieldReader<u8, u8>;
549 #[inline(always)]
550 fn deref(&self) -> &Self::Target {
551 &self.0
552 }
553}
554#[doc = "Field `STATEV` writer - This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value."]
555pub struct STATEV_W<'a> {
556 w: &'a mut W,
557}
558impl<'a> STATEV_W<'a> {
559 #[doc = r"Writes raw bits to the field"]
560 #[inline(always)]
561 pub unsafe fn bits(self, value: u8) -> &'a mut W {
562 self.w.bits = (self.w.bits & !(0x1f << 15)) | ((value as u32 & 0x1f) << 15);
563 self.w
564 }
565}
566#[doc = "Field `MATCHMEM` reader - If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value."]
567pub struct MATCHMEM_R(crate::FieldReader<bool, bool>);
568impl MATCHMEM_R {
569 pub(crate) fn new(bits: bool) -> Self {
570 MATCHMEM_R(crate::FieldReader::new(bits))
571 }
572}
573impl core::ops::Deref for MATCHMEM_R {
574 type Target = crate::FieldReader<bool, bool>;
575 #[inline(always)]
576 fn deref(&self) -> &Self::Target {
577 &self.0
578 }
579}
580#[doc = "Field `MATCHMEM` writer - If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value."]
581pub struct MATCHMEM_W<'a> {
582 w: &'a mut W,
583}
584impl<'a> MATCHMEM_W<'a> {
585 #[doc = r"Sets the field bit"]
586 #[inline(always)]
587 pub fn set_bit(self) -> &'a mut W {
588 self.bit(true)
589 }
590 #[doc = r"Clears the field bit"]
591 #[inline(always)]
592 pub fn clear_bit(self) -> &'a mut W {
593 self.bit(false)
594 }
595 #[doc = r"Writes raw bits to the field"]
596 #[inline(always)]
597 pub fn bit(self, value: bool) -> &'a mut W {
598 self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20);
599 self.w
600 }
601}
602#[doc = "Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.\n\nValue on reset: 0"]
603#[derive(Clone, Copy, Debug, PartialEq)]
604#[repr(u8)]
605pub enum DIRECTION_A {
606 #[doc = "0: Direction independent. This event is triggered regardless of the count direction."]
607 DIRECTION_INDEPENDENT = 0,
608 #[doc = "1: Counting up. This event is triggered only during up-counting when BIDIR = 1."]
609 COUNTING_UP = 1,
610 #[doc = "2: Counting down. This event is triggered only during down-counting when BIDIR = 1."]
611 COUNTING_DOWN = 2,
612}
613impl From<DIRECTION_A> for u8 {
614 #[inline(always)]
615 fn from(variant: DIRECTION_A) -> Self {
616 variant as _
617 }
618}
619#[doc = "Field `DIRECTION` reader - Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved."]
620pub struct DIRECTION_R(crate::FieldReader<u8, DIRECTION_A>);
621impl DIRECTION_R {
622 pub(crate) fn new(bits: u8) -> Self {
623 DIRECTION_R(crate::FieldReader::new(bits))
624 }
625 #[doc = r"Get enumerated values variant"]
626 #[inline(always)]
627 pub fn variant(&self) -> Option<DIRECTION_A> {
628 match self.bits {
629 0 => Some(DIRECTION_A::DIRECTION_INDEPENDENT),
630 1 => Some(DIRECTION_A::COUNTING_UP),
631 2 => Some(DIRECTION_A::COUNTING_DOWN),
632 _ => None,
633 }
634 }
635 #[doc = "Checks if the value of the field is `DIRECTION_INDEPENDENT`"]
636 #[inline(always)]
637 pub fn is_direction_independent(&self) -> bool {
638 **self == DIRECTION_A::DIRECTION_INDEPENDENT
639 }
640 #[doc = "Checks if the value of the field is `COUNTING_UP`"]
641 #[inline(always)]
642 pub fn is_counting_up(&self) -> bool {
643 **self == DIRECTION_A::COUNTING_UP
644 }
645 #[doc = "Checks if the value of the field is `COUNTING_DOWN`"]
646 #[inline(always)]
647 pub fn is_counting_down(&self) -> bool {
648 **self == DIRECTION_A::COUNTING_DOWN
649 }
650}
651impl core::ops::Deref for DIRECTION_R {
652 type Target = crate::FieldReader<u8, DIRECTION_A>;
653 #[inline(always)]
654 fn deref(&self) -> &Self::Target {
655 &self.0
656 }
657}
658#[doc = "Field `DIRECTION` writer - Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved."]
659pub struct DIRECTION_W<'a> {
660 w: &'a mut W,
661}
662impl<'a> DIRECTION_W<'a> {
663 #[doc = r"Writes `variant` to the field"]
664 #[inline(always)]
665 pub fn variant(self, variant: DIRECTION_A) -> &'a mut W {
666 unsafe { self.bits(variant.into()) }
667 }
668 #[doc = "Direction independent. This event is triggered regardless of the count direction."]
669 #[inline(always)]
670 pub fn direction_independent(self) -> &'a mut W {
671 self.variant(DIRECTION_A::DIRECTION_INDEPENDENT)
672 }
673 #[doc = "Counting up. This event is triggered only during up-counting when BIDIR = 1."]
674 #[inline(always)]
675 pub fn counting_up(self) -> &'a mut W {
676 self.variant(DIRECTION_A::COUNTING_UP)
677 }
678 #[doc = "Counting down. This event is triggered only during down-counting when BIDIR = 1."]
679 #[inline(always)]
680 pub fn counting_down(self) -> &'a mut W {
681 self.variant(DIRECTION_A::COUNTING_DOWN)
682 }
683 #[doc = r"Writes raw bits to the field"]
684 #[inline(always)]
685 pub unsafe fn bits(self, value: u8) -> &'a mut W {
686 self.w.bits = (self.w.bits & !(0x03 << 21)) | ((value as u32 & 0x03) << 21);
687 self.w
688 }
689}
690impl R {
691 #[doc = "Bits 0:3 - Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running."]
692 #[inline(always)]
693 pub fn matchsel(&self) -> MATCHSEL_R {
694 MATCHSEL_R::new((self.bits & 0x0f) as u8)
695 }
696 #[doc = "Bit 4 - Select L/H counter. Do not set this bit if UNIFY = 1."]
697 #[inline(always)]
698 pub fn hevent(&self) -> HEVENT_R {
699 HEVENT_R::new(((self.bits >> 4) & 0x01) != 0)
700 }
701 #[doc = "Bit 5 - Input/output select"]
702 #[inline(always)]
703 pub fn outsel(&self) -> OUTSEL_R {
704 OUTSEL_R::new(((self.bits >> 5) & 0x01) != 0)
705 }
706 #[doc = "Bits 6:9 - Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event."]
707 #[inline(always)]
708 pub fn iosel(&self) -> IOSEL_R {
709 IOSEL_R::new(((self.bits >> 6) & 0x0f) as u8)
710 }
711 #[doc = "Bits 10:11 - Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ."]
712 #[inline(always)]
713 pub fn iocond(&self) -> IOCOND_R {
714 IOCOND_R::new(((self.bits >> 10) & 0x03) as u8)
715 }
716 #[doc = "Bits 12:13 - Selects how the specified match and I/O condition are used and combined."]
717 #[inline(always)]
718 pub fn combmode(&self) -> COMBMODE_R {
719 COMBMODE_R::new(((self.bits >> 12) & 0x03) as u8)
720 }
721 #[doc = "Bit 14 - This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state."]
722 #[inline(always)]
723 pub fn stateld(&self) -> STATELD_R {
724 STATELD_R::new(((self.bits >> 14) & 0x01) != 0)
725 }
726 #[doc = "Bits 15:19 - This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value."]
727 #[inline(always)]
728 pub fn statev(&self) -> STATEV_R {
729 STATEV_R::new(((self.bits >> 15) & 0x1f) as u8)
730 }
731 #[doc = "Bit 20 - If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value."]
732 #[inline(always)]
733 pub fn matchmem(&self) -> MATCHMEM_R {
734 MATCHMEM_R::new(((self.bits >> 20) & 0x01) != 0)
735 }
736 #[doc = "Bits 21:22 - Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved."]
737 #[inline(always)]
738 pub fn direction(&self) -> DIRECTION_R {
739 DIRECTION_R::new(((self.bits >> 21) & 0x03) as u8)
740 }
741}
742impl W {
743 #[doc = "Bits 0:3 - Selects the Match register associated with this event (if any). A match can occur only when the counter selected by the HEVENT bit is running."]
744 #[inline(always)]
745 pub fn matchsel(&mut self) -> MATCHSEL_W {
746 MATCHSEL_W { w: self }
747 }
748 #[doc = "Bit 4 - Select L/H counter. Do not set this bit if UNIFY = 1."]
749 #[inline(always)]
750 pub fn hevent(&mut self) -> HEVENT_W {
751 HEVENT_W { w: self }
752 }
753 #[doc = "Bit 5 - Input/output select"]
754 #[inline(always)]
755 pub fn outsel(&mut self) -> OUTSEL_W {
756 OUTSEL_W { w: self }
757 }
758 #[doc = "Bits 6:9 - Selects the input or output signal number associated with this event (if any). Do not select an input in this register if CKMODE is 1x. In this case the clock input is an implicit ingredient of every event."]
759 #[inline(always)]
760 pub fn iosel(&mut self) -> IOSEL_W {
761 IOSEL_W { w: self }
762 }
763 #[doc = "Bits 10:11 - Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period ."]
764 #[inline(always)]
765 pub fn iocond(&mut self) -> IOCOND_W {
766 IOCOND_W { w: self }
767 }
768 #[doc = "Bits 12:13 - Selects how the specified match and I/O condition are used and combined."]
769 #[inline(always)]
770 pub fn combmode(&mut self) -> COMBMODE_W {
771 COMBMODE_W { w: self }
772 }
773 #[doc = "Bit 14 - This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state."]
774 #[inline(always)]
775 pub fn stateld(&mut self) -> STATELD_W {
776 STATELD_W { w: self }
777 }
778 #[doc = "Bits 15:19 - This value is loaded into or added to the state selected by HEVENT, depending on STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and STATEV are both zero, there is no change to the STATE value."]
779 #[inline(always)]
780 pub fn statev(&mut self) -> STATEV_W {
781 STATEV_W { w: self }
782 }
783 #[doc = "Bit 20 - If this bit is one and the COMBMODE field specifies a match component to the triggering of this event, then a match is considered to be active whenever the counter value is GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR EQUAL TO the match value when counting down. If this bit is zero, a match is only be active during the cycle when the counter is equal to the match value."]
784 #[inline(always)]
785 pub fn matchmem(&mut self) -> MATCHMEM_W {
786 MATCHMEM_W { w: self }
787 }
788 #[doc = "Bits 21:22 - Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved."]
789 #[inline(always)]
790 pub fn direction(&mut self) -> DIRECTION_W {
791 DIRECTION_W { w: self }
792 }
793 #[doc = "Writes raw bits to the register."]
794 #[inline(always)]
795 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
796 self.0.bits(bits);
797 self
798 }
799}
800#[doc = "SCT event control register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
801pub struct CTRL_SPEC;
802impl crate::RegisterSpec for CTRL_SPEC {
803 type Ux = u32;
804}
805#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
806impl crate::Readable for CTRL_SPEC {
807 type Reader = R;
808}
809#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
810impl crate::Writable for CTRL_SPEC {
811 type Writer = W;
812}
813#[doc = "`reset()` method sets CTRL to value 0"]
814impl crate::Resettable for CTRL_SPEC {
815 #[inline(always)]
816 fn reset_value() -> Self::Ux {
817 0
818 }
819}