lpc845_pac/inputmux/
dma_itrig_inmux.rs

1#[doc = "Register `DMA_ITRIG_INMUX[%s]` reader"]
2pub struct R(crate::R<DMA_ITRIG_INMUX_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DMA_ITRIG_INMUX_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DMA_ITRIG_INMUX_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DMA_ITRIG_INMUX_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DMA_ITRIG_INMUX[%s]` writer"]
17pub struct W(crate::W<DMA_ITRIG_INMUX_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DMA_ITRIG_INMUX_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DMA_ITRIG_INMUX_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DMA_ITRIG_INMUX_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `INP` reader - Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1"]
38pub struct INP_R(crate::FieldReader<u8, u8>);
39impl INP_R {
40    pub(crate) fn new(bits: u8) -> Self {
41        INP_R(crate::FieldReader::new(bits))
42    }
43}
44impl core::ops::Deref for INP_R {
45    type Target = crate::FieldReader<u8, u8>;
46    #[inline(always)]
47    fn deref(&self) -> &Self::Target {
48        &self.0
49    }
50}
51#[doc = "Field `INP` writer - Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1"]
52pub struct INP_W<'a> {
53    w: &'a mut W,
54}
55impl<'a> INP_W<'a> {
56    #[doc = r"Writes raw bits to the field"]
57    #[inline(always)]
58    pub unsafe fn bits(self, value: u8) -> &'a mut W {
59        self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f);
60        self.w
61    }
62}
63impl R {
64    #[doc = "Bits 0:3 - Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1"]
65    #[inline(always)]
66    pub fn inp(&self) -> INP_R {
67        INP_R::new((self.bits & 0x0f) as u8)
68    }
69}
70impl W {
71    #[doc = "Bits 0:3 - Trigger input number (decimal value) for DMA channel n (n = 0 to 12). 0 = ADC0 Sequence A interrupt 1 = ADC0 Sequence B interrupt 2 = SCT0 DMA request 0 3 = SCT0 DMA request 1 4= Comparator out 5 = Pin interrupt 4 6 = Pin interrupt 5 7 = Pin interrupt 6 8 = Pin interrupt 7 9= Timer CTIMER0 Match 0 dma request 10 = Timer CTIMER0 Match 1 dma request 11 = DMA output trigger mux 0 12 = DMA output trigger mux 1"]
72    #[inline(always)]
73    pub fn inp(&mut self) -> INP_W {
74        INP_W { w: self }
75    }
76    #[doc = "Writes raw bits to the register."]
77    #[inline(always)]
78    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
79        self.0.bits(bits);
80        self
81    }
82}
83#[doc = "Trigger select register for DMA channel\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_itrig_inmux](index.html) module"]
84pub struct DMA_ITRIG_INMUX_SPEC;
85impl crate::RegisterSpec for DMA_ITRIG_INMUX_SPEC {
86    type Ux = u32;
87}
88#[doc = "`read()` method returns [dma_itrig_inmux::R](R) reader structure"]
89impl crate::Readable for DMA_ITRIG_INMUX_SPEC {
90    type Reader = R;
91}
92#[doc = "`write(|w| ..)` method takes [dma_itrig_inmux::W](W) writer structure"]
93impl crate::Writable for DMA_ITRIG_INMUX_SPEC {
94    type Writer = W;
95}
96#[doc = "`reset()` method sets DMA_ITRIG_INMUX[%s]
97to value 0x0f"]
98impl crate::Resettable for DMA_ITRIG_INMUX_SPEC {
99    #[inline(always)]
100    fn reset_value() -> Self::Ux {
101        0x0f
102    }
103}
lpc845_pac/inputmux/dma_itrig_inmux.rs

lpc845_pac/inputmux/
dma_itrig_inmux.rs
