lpc845_pac/adc0/
seq_gdat.rs1#[doc = "Register `SEQ_GDAT%s` reader"]
2pub struct R(crate::R<SEQ_GDAT_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<SEQ_GDAT_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<SEQ_GDAT_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<SEQ_GDAT_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Field `RESULT` reader - This field contains the 12-bit ADC conversion result from the most recent conversion performed under conversion sequence associated with this register. The result is a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this result has not yet been read."]
17pub struct RESULT_R(crate::FieldReader<u16, u16>);
18impl RESULT_R {
19 pub(crate) fn new(bits: u16) -> Self {
20 RESULT_R(crate::FieldReader::new(bits))
21 }
22}
23impl core::ops::Deref for RESULT_R {
24 type Target = crate::FieldReader<u16, u16>;
25 #[inline(always)]
26 fn deref(&self) -> &Self::Target {
27 &self.0
28 }
29}
30#[doc = "Field `THCMPRANGE` reader - Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH)."]
31pub struct THCMPRANGE_R(crate::FieldReader<u8, u8>);
32impl THCMPRANGE_R {
33 pub(crate) fn new(bits: u8) -> Self {
34 THCMPRANGE_R(crate::FieldReader::new(bits))
35 }
36}
37impl core::ops::Deref for THCMPRANGE_R {
38 type Target = crate::FieldReader<u8, u8>;
39 #[inline(always)]
40 fn deref(&self) -> &Self::Target {
41 &self.0
42 }
43}
44#[doc = "Field `THCMPCROSS` reader - Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred."]
45pub struct THCMPCROSS_R(crate::FieldReader<u8, u8>);
46impl THCMPCROSS_R {
47 pub(crate) fn new(bits: u8) -> Self {
48 THCMPCROSS_R(crate::FieldReader::new(bits))
49 }
50}
51impl core::ops::Deref for THCMPCROSS_R {
52 type Target = crate::FieldReader<u8, u8>;
53 #[inline(always)]
54 fn deref(&self) -> &Self::Target {
55 &self.0
56 }
57}
58#[doc = "Field `CHN` reader - These bits contain the channel from which the RESULT bits were converted (e.g. 0000 identifies channel 0, 0001 channel 1, etc.)."]
59pub struct CHN_R(crate::FieldReader<u8, u8>);
60impl CHN_R {
61 pub(crate) fn new(bits: u8) -> Self {
62 CHN_R(crate::FieldReader::new(bits))
63 }
64}
65impl core::ops::Deref for CHN_R {
66 type Target = crate::FieldReader<u8, u8>;
67 #[inline(always)]
68 fn deref(&self) -> &Self::Target {
69 &self.0
70 }
71}
72#[doc = "Field `OVERRUN` reader - This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set to '0' (and if the overrun interrupt is enabled)."]
73pub struct OVERRUN_R(crate::FieldReader<bool, bool>);
74impl OVERRUN_R {
75 pub(crate) fn new(bits: bool) -> Self {
76 OVERRUN_R(crate::FieldReader::new(bits))
77 }
78}
79impl core::ops::Deref for OVERRUN_R {
80 type Target = crate::FieldReader<bool, bool>;
81 #[inline(always)]
82 fn deref(&self) -> &Self::Target {
83 &self.0
84 }
85}
86#[doc = "Field `DATAVALID` reader - This bit is set to '1' at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that sequence is set to 0 (and if the interrupt is enabled)."]
87pub struct DATAVALID_R(crate::FieldReader<bool, bool>);
88impl DATAVALID_R {
89 pub(crate) fn new(bits: bool) -> Self {
90 DATAVALID_R(crate::FieldReader::new(bits))
91 }
92}
93impl core::ops::Deref for DATAVALID_R {
94 type Target = crate::FieldReader<bool, bool>;
95 #[inline(always)]
96 fn deref(&self) -> &Self::Target {
97 &self.0
98 }
99}
100impl R {
101 #[doc = "Bits 4:15 - This field contains the 12-bit ADC conversion result from the most recent conversion performed under conversion sequence associated with this register. The result is a binary fraction representing the voltage on the currently-selected input channel as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this result has not yet been read."]
102 #[inline(always)]
103 pub fn result(&self) -> RESULT_R {
104 RESULT_R::new(((self.bits >> 4) & 0x0fff) as u16)
105 }
106 #[doc = "Bits 16:17 - Indicates whether the result of the last conversion performed was above, below or within the range established by the designated threshold comparison registers (THRn_LOW and THRn_HIGH)."]
107 #[inline(always)]
108 pub fn thcmprange(&self) -> THCMPRANGE_R {
109 THCMPRANGE_R::new(((self.bits >> 16) & 0x03) as u8)
110 }
111 #[doc = "Bits 18:19 - Indicates whether the result of the last conversion performed represented a crossing of the threshold level established by the designated LOW threshold comparison register (THRn_LOW) and, if so, in what direction the crossing occurred."]
112 #[inline(always)]
113 pub fn thcmpcross(&self) -> THCMPCROSS_R {
114 THCMPCROSS_R::new(((self.bits >> 18) & 0x03) as u8)
115 }
116 #[doc = "Bits 26:29 - These bits contain the channel from which the RESULT bits were converted (e.g. 0000 identifies channel 0, 0001 channel 1, etc.)."]
117 #[inline(always)]
118 pub fn chn(&self) -> CHN_R {
119 CHN_R::new(((self.bits >> 26) & 0x0f) as u8)
120 }
121 #[doc = "Bit 30 - This bit is set if a new conversion result is loaded into the RESULT field before a previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set to '0' (and if the overrun interrupt is enabled)."]
122 #[inline(always)]
123 pub fn overrun(&self) -> OVERRUN_R {
124 OVERRUN_R::new(((self.bits >> 30) & 0x01) != 0)
125 }
126 #[doc = "Bit 31 - This bit is set to '1' at the end of each conversion when a new result is loaded into the RESULT field. It is cleared whenever this register is read. This bit will cause a conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that sequence is set to 0 (and if the interrupt is enabled)."]
127 #[inline(always)]
128 pub fn datavalid(&self) -> DATAVALID_R {
129 DATAVALID_R::new(((self.bits >> 31) & 0x01) != 0)
130 }
131}
132#[doc = "ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seq_gdat](index.html) module"]
133pub struct SEQ_GDAT_SPEC;
134impl crate::RegisterSpec for SEQ_GDAT_SPEC {
135 type Ux = u32;
136}
137#[doc = "`read()` method returns [seq_gdat::R](R) reader structure"]
138impl crate::Readable for SEQ_GDAT_SPEC {
139 type Reader = R;
140}
141#[doc = "`reset()` method sets SEQ_GDAT%s to value 0"]
142impl crate::Resettable for SEQ_GDAT_SPEC {
143 #[inline(always)]
144 fn reset_value() -> Self::Ux {
145 0
146 }
147}