lpc845_pac/adc0/
inten.rs

1#[doc = "Register `INTEN` reader"]
2pub struct R(crate::R<INTEN_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<INTEN_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<INTEN_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<INTEN_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `INTEN` writer"]
17pub struct W(crate::W<INTEN_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<INTEN_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<INTEN_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<INTEN_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Sequence A interrupt enable.\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum SEQA_INTEN_A {
40    #[doc = "0: Disabled. The sequence A interrupt/DMA trigger is disabled."]
41    DISABLED = 0,
42    #[doc = "1: Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of conversions, depending on the MODE bit in the SEQA_CTRL register."]
43    ENABLED = 1,
44}
45impl From<SEQA_INTEN_A> for bool {
46    #[inline(always)]
47    fn from(variant: SEQA_INTEN_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `SEQA_INTEN` reader - Sequence A interrupt enable."]
52pub struct SEQA_INTEN_R(crate::FieldReader<bool, SEQA_INTEN_A>);
53impl SEQA_INTEN_R {
54    pub(crate) fn new(bits: bool) -> Self {
55        SEQA_INTEN_R(crate::FieldReader::new(bits))
56    }
57    #[doc = r"Get enumerated values variant"]
58    #[inline(always)]
59    pub fn variant(&self) -> SEQA_INTEN_A {
60        match self.bits {
61            false => SEQA_INTEN_A::DISABLED,
62            true => SEQA_INTEN_A::ENABLED,
63        }
64    }
65    #[doc = "Checks if the value of the field is `DISABLED`"]
66    #[inline(always)]
67    pub fn is_disabled(&self) -> bool {
68        **self == SEQA_INTEN_A::DISABLED
69    }
70    #[doc = "Checks if the value of the field is `ENABLED`"]
71    #[inline(always)]
72    pub fn is_enabled(&self) -> bool {
73        **self == SEQA_INTEN_A::ENABLED
74    }
75}
76impl core::ops::Deref for SEQA_INTEN_R {
77    type Target = crate::FieldReader<bool, SEQA_INTEN_A>;
78    #[inline(always)]
79    fn deref(&self) -> &Self::Target {
80        &self.0
81    }
82}
83#[doc = "Field `SEQA_INTEN` writer - Sequence A interrupt enable."]
84pub struct SEQA_INTEN_W<'a> {
85    w: &'a mut W,
86}
87impl<'a> SEQA_INTEN_W<'a> {
88    #[doc = r"Writes `variant` to the field"]
89    #[inline(always)]
90    pub fn variant(self, variant: SEQA_INTEN_A) -> &'a mut W {
91        self.bit(variant.into())
92    }
93    #[doc = "Disabled. The sequence A interrupt/DMA trigger is disabled."]
94    #[inline(always)]
95    pub fn disabled(self) -> &'a mut W {
96        self.variant(SEQA_INTEN_A::DISABLED)
97    }
98    #[doc = "Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of conversions, depending on the MODE bit in the SEQA_CTRL register."]
99    #[inline(always)]
100    pub fn enabled(self) -> &'a mut W {
101        self.variant(SEQA_INTEN_A::ENABLED)
102    }
103    #[doc = r"Sets the field bit"]
104    #[inline(always)]
105    pub fn set_bit(self) -> &'a mut W {
106        self.bit(true)
107    }
108    #[doc = r"Clears the field bit"]
109    #[inline(always)]
110    pub fn clear_bit(self) -> &'a mut W {
111        self.bit(false)
112    }
113    #[doc = r"Writes raw bits to the field"]
114    #[inline(always)]
115    pub fn bit(self, value: bool) -> &'a mut W {
116        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
117        self.w
118    }
119}
120#[doc = "Sequence B interrupt enable.\n\nValue on reset: 0"]
121#[derive(Clone, Copy, Debug, PartialEq)]
122pub enum SEQB_INTEN_A {
123    #[doc = "0: Disabled. The sequence B interrupt/DMA trigger is disabled."]
124    DISABLED = 0,
125    #[doc = "1: Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of conversions, depending on the MODE bit in the SEQB_CTRL register."]
126    ENABLED = 1,
127}
128impl From<SEQB_INTEN_A> for bool {
129    #[inline(always)]
130    fn from(variant: SEQB_INTEN_A) -> Self {
131        variant as u8 != 0
132    }
133}
134#[doc = "Field `SEQB_INTEN` reader - Sequence B interrupt enable."]
135pub struct SEQB_INTEN_R(crate::FieldReader<bool, SEQB_INTEN_A>);
136impl SEQB_INTEN_R {
137    pub(crate) fn new(bits: bool) -> Self {
138        SEQB_INTEN_R(crate::FieldReader::new(bits))
139    }
140    #[doc = r"Get enumerated values variant"]
141    #[inline(always)]
142    pub fn variant(&self) -> SEQB_INTEN_A {
143        match self.bits {
144            false => SEQB_INTEN_A::DISABLED,
145            true => SEQB_INTEN_A::ENABLED,
146        }
147    }
148    #[doc = "Checks if the value of the field is `DISABLED`"]
149    #[inline(always)]
150    pub fn is_disabled(&self) -> bool {
151        **self == SEQB_INTEN_A::DISABLED
152    }
153    #[doc = "Checks if the value of the field is `ENABLED`"]
154    #[inline(always)]
155    pub fn is_enabled(&self) -> bool {
156        **self == SEQB_INTEN_A::ENABLED
157    }
158}
159impl core::ops::Deref for SEQB_INTEN_R {
160    type Target = crate::FieldReader<bool, SEQB_INTEN_A>;
161    #[inline(always)]
162    fn deref(&self) -> &Self::Target {
163        &self.0
164    }
165}
166#[doc = "Field `SEQB_INTEN` writer - Sequence B interrupt enable."]
167pub struct SEQB_INTEN_W<'a> {
168    w: &'a mut W,
169}
170impl<'a> SEQB_INTEN_W<'a> {
171    #[doc = r"Writes `variant` to the field"]
172    #[inline(always)]
173    pub fn variant(self, variant: SEQB_INTEN_A) -> &'a mut W {
174        self.bit(variant.into())
175    }
176    #[doc = "Disabled. The sequence B interrupt/DMA trigger is disabled."]
177    #[inline(always)]
178    pub fn disabled(self) -> &'a mut W {
179        self.variant(SEQB_INTEN_A::DISABLED)
180    }
181    #[doc = "Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of conversions, depending on the MODE bit in the SEQB_CTRL register."]
182    #[inline(always)]
183    pub fn enabled(self) -> &'a mut W {
184        self.variant(SEQB_INTEN_A::ENABLED)
185    }
186    #[doc = r"Sets the field bit"]
187    #[inline(always)]
188    pub fn set_bit(self) -> &'a mut W {
189        self.bit(true)
190    }
191    #[doc = r"Clears the field bit"]
192    #[inline(always)]
193    pub fn clear_bit(self) -> &'a mut W {
194        self.bit(false)
195    }
196    #[doc = r"Writes raw bits to the field"]
197    #[inline(always)]
198    pub fn bit(self, value: bool) -> &'a mut W {
199        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
200        self.w
201    }
202}
203#[doc = "Overrun interrupt enable.\n\nValue on reset: 0"]
204#[derive(Clone, Copy, Debug, PartialEq)]
205pub enum OVR_INTEN_A {
206    #[doc = "0: Disabled. The overrun interrupt is disabled."]
207    DISABLED = 0,
208    #[doc = "1: Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular sequence is 0, then an overrun in the global data register for that sequence will also cause this interrupt/DMA trigger to be asserted."]
209    ENABLED = 1,
210}
211impl From<OVR_INTEN_A> for bool {
212    #[inline(always)]
213    fn from(variant: OVR_INTEN_A) -> Self {
214        variant as u8 != 0
215    }
216}
217#[doc = "Field `OVR_INTEN` reader - Overrun interrupt enable."]
218pub struct OVR_INTEN_R(crate::FieldReader<bool, OVR_INTEN_A>);
219impl OVR_INTEN_R {
220    pub(crate) fn new(bits: bool) -> Self {
221        OVR_INTEN_R(crate::FieldReader::new(bits))
222    }
223    #[doc = r"Get enumerated values variant"]
224    #[inline(always)]
225    pub fn variant(&self) -> OVR_INTEN_A {
226        match self.bits {
227            false => OVR_INTEN_A::DISABLED,
228            true => OVR_INTEN_A::ENABLED,
229        }
230    }
231    #[doc = "Checks if the value of the field is `DISABLED`"]
232    #[inline(always)]
233    pub fn is_disabled(&self) -> bool {
234        **self == OVR_INTEN_A::DISABLED
235    }
236    #[doc = "Checks if the value of the field is `ENABLED`"]
237    #[inline(always)]
238    pub fn is_enabled(&self) -> bool {
239        **self == OVR_INTEN_A::ENABLED
240    }
241}
242impl core::ops::Deref for OVR_INTEN_R {
243    type Target = crate::FieldReader<bool, OVR_INTEN_A>;
244    #[inline(always)]
245    fn deref(&self) -> &Self::Target {
246        &self.0
247    }
248}
249#[doc = "Field `OVR_INTEN` writer - Overrun interrupt enable."]
250pub struct OVR_INTEN_W<'a> {
251    w: &'a mut W,
252}
253impl<'a> OVR_INTEN_W<'a> {
254    #[doc = r"Writes `variant` to the field"]
255    #[inline(always)]
256    pub fn variant(self, variant: OVR_INTEN_A) -> &'a mut W {
257        self.bit(variant.into())
258    }
259    #[doc = "Disabled. The overrun interrupt is disabled."]
260    #[inline(always)]
261    pub fn disabled(self) -> &'a mut W {
262        self.variant(OVR_INTEN_A::DISABLED)
263    }
264    #[doc = "Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular sequence is 0, then an overrun in the global data register for that sequence will also cause this interrupt/DMA trigger to be asserted."]
265    #[inline(always)]
266    pub fn enabled(self) -> &'a mut W {
267        self.variant(OVR_INTEN_A::ENABLED)
268    }
269    #[doc = r"Sets the field bit"]
270    #[inline(always)]
271    pub fn set_bit(self) -> &'a mut W {
272        self.bit(true)
273    }
274    #[doc = r"Clears the field bit"]
275    #[inline(always)]
276    pub fn clear_bit(self) -> &'a mut W {
277        self.bit(false)
278    }
279    #[doc = r"Writes raw bits to the field"]
280    #[inline(always)]
281    pub fn bit(self, value: bool) -> &'a mut W {
282        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
283        self.w
284    }
285}
286#[doc = "Threshold comparison interrupt enable for channel 0.\n\nValue on reset: 0"]
287#[derive(Clone, Copy, Debug, PartialEq)]
288#[repr(u8)]
289pub enum ADCMPINTEN0_A {
290    #[doc = "0: Disabled."]
291    DISABLED = 0,
292    #[doc = "1: Outside threshold."]
293    OUTSIDE_THRESHOLD = 1,
294    #[doc = "2: Crossing threshold."]
295    CROSSING_THRESHOLD = 2,
296}
297impl From<ADCMPINTEN0_A> for u8 {
298    #[inline(always)]
299    fn from(variant: ADCMPINTEN0_A) -> Self {
300        variant as _
301    }
302}
303#[doc = "Field `ADCMPINTEN0` reader - Threshold comparison interrupt enable for channel 0."]
304pub struct ADCMPINTEN0_R(crate::FieldReader<u8, ADCMPINTEN0_A>);
305impl ADCMPINTEN0_R {
306    pub(crate) fn new(bits: u8) -> Self {
307        ADCMPINTEN0_R(crate::FieldReader::new(bits))
308    }
309    #[doc = r"Get enumerated values variant"]
310    #[inline(always)]
311    pub fn variant(&self) -> Option<ADCMPINTEN0_A> {
312        match self.bits {
313            0 => Some(ADCMPINTEN0_A::DISABLED),
314            1 => Some(ADCMPINTEN0_A::OUTSIDE_THRESHOLD),
315            2 => Some(ADCMPINTEN0_A::CROSSING_THRESHOLD),
316            _ => None,
317        }
318    }
319    #[doc = "Checks if the value of the field is `DISABLED`"]
320    #[inline(always)]
321    pub fn is_disabled(&self) -> bool {
322        **self == ADCMPINTEN0_A::DISABLED
323    }
324    #[doc = "Checks if the value of the field is `OUTSIDE_THRESHOLD`"]
325    #[inline(always)]
326    pub fn is_outside_threshold(&self) -> bool {
327        **self == ADCMPINTEN0_A::OUTSIDE_THRESHOLD
328    }
329    #[doc = "Checks if the value of the field is `CROSSING_THRESHOLD`"]
330    #[inline(always)]
331    pub fn is_crossing_threshold(&self) -> bool {
332        **self == ADCMPINTEN0_A::CROSSING_THRESHOLD
333    }
334}
335impl core::ops::Deref for ADCMPINTEN0_R {
336    type Target = crate::FieldReader<u8, ADCMPINTEN0_A>;
337    #[inline(always)]
338    fn deref(&self) -> &Self::Target {
339        &self.0
340    }
341}
342#[doc = "Field `ADCMPINTEN0` writer - Threshold comparison interrupt enable for channel 0."]
343pub struct ADCMPINTEN0_W<'a> {
344    w: &'a mut W,
345}
346impl<'a> ADCMPINTEN0_W<'a> {
347    #[doc = r"Writes `variant` to the field"]
348    #[inline(always)]
349    pub fn variant(self, variant: ADCMPINTEN0_A) -> &'a mut W {
350        unsafe { self.bits(variant.into()) }
351    }
352    #[doc = "Disabled."]
353    #[inline(always)]
354    pub fn disabled(self) -> &'a mut W {
355        self.variant(ADCMPINTEN0_A::DISABLED)
356    }
357    #[doc = "Outside threshold."]
358    #[inline(always)]
359    pub fn outside_threshold(self) -> &'a mut W {
360        self.variant(ADCMPINTEN0_A::OUTSIDE_THRESHOLD)
361    }
362    #[doc = "Crossing threshold."]
363    #[inline(always)]
364    pub fn crossing_threshold(self) -> &'a mut W {
365        self.variant(ADCMPINTEN0_A::CROSSING_THRESHOLD)
366    }
367    #[doc = r"Writes raw bits to the field"]
368    #[inline(always)]
369    pub unsafe fn bits(self, value: u8) -> &'a mut W {
370        self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3);
371        self.w
372    }
373}
374#[doc = "Field `ADCMPINTEN1` reader - Channel 1 threshold comparison interrupt enable. See description for channel 0."]
375pub struct ADCMPINTEN1_R(crate::FieldReader<u8, u8>);
376impl ADCMPINTEN1_R {
377    pub(crate) fn new(bits: u8) -> Self {
378        ADCMPINTEN1_R(crate::FieldReader::new(bits))
379    }
380}
381impl core::ops::Deref for ADCMPINTEN1_R {
382    type Target = crate::FieldReader<u8, u8>;
383    #[inline(always)]
384    fn deref(&self) -> &Self::Target {
385        &self.0
386    }
387}
388#[doc = "Field `ADCMPINTEN1` writer - Channel 1 threshold comparison interrupt enable. See description for channel 0."]
389pub struct ADCMPINTEN1_W<'a> {
390    w: &'a mut W,
391}
392impl<'a> ADCMPINTEN1_W<'a> {
393    #[doc = r"Writes raw bits to the field"]
394    #[inline(always)]
395    pub unsafe fn bits(self, value: u8) -> &'a mut W {
396        self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5);
397        self.w
398    }
399}
400#[doc = "Field `ADCMPINTEN2` reader - Channel 2 threshold comparison interrupt enable. See description for channel 0."]
401pub struct ADCMPINTEN2_R(crate::FieldReader<u8, u8>);
402impl ADCMPINTEN2_R {
403    pub(crate) fn new(bits: u8) -> Self {
404        ADCMPINTEN2_R(crate::FieldReader::new(bits))
405    }
406}
407impl core::ops::Deref for ADCMPINTEN2_R {
408    type Target = crate::FieldReader<u8, u8>;
409    #[inline(always)]
410    fn deref(&self) -> &Self::Target {
411        &self.0
412    }
413}
414#[doc = "Field `ADCMPINTEN2` writer - Channel 2 threshold comparison interrupt enable. See description for channel 0."]
415pub struct ADCMPINTEN2_W<'a> {
416    w: &'a mut W,
417}
418impl<'a> ADCMPINTEN2_W<'a> {
419    #[doc = r"Writes raw bits to the field"]
420    #[inline(always)]
421    pub unsafe fn bits(self, value: u8) -> &'a mut W {
422        self.w.bits = (self.w.bits & !(0x03 << 7)) | ((value as u32 & 0x03) << 7);
423        self.w
424    }
425}
426#[doc = "Field `ADCMPINTEN3` reader - Channel 3 threshold comparison interrupt enable. See description for channel 0."]
427pub struct ADCMPINTEN3_R(crate::FieldReader<u8, u8>);
428impl ADCMPINTEN3_R {
429    pub(crate) fn new(bits: u8) -> Self {
430        ADCMPINTEN3_R(crate::FieldReader::new(bits))
431    }
432}
433impl core::ops::Deref for ADCMPINTEN3_R {
434    type Target = crate::FieldReader<u8, u8>;
435    #[inline(always)]
436    fn deref(&self) -> &Self::Target {
437        &self.0
438    }
439}
440#[doc = "Field `ADCMPINTEN3` writer - Channel 3 threshold comparison interrupt enable. See description for channel 0."]
441pub struct ADCMPINTEN3_W<'a> {
442    w: &'a mut W,
443}
444impl<'a> ADCMPINTEN3_W<'a> {
445    #[doc = r"Writes raw bits to the field"]
446    #[inline(always)]
447    pub unsafe fn bits(self, value: u8) -> &'a mut W {
448        self.w.bits = (self.w.bits & !(0x03 << 9)) | ((value as u32 & 0x03) << 9);
449        self.w
450    }
451}
452#[doc = "Field `ADCMPINTEN4` reader - Channel 4 threshold comparison interrupt enable. See description for channel 0."]
453pub struct ADCMPINTEN4_R(crate::FieldReader<u8, u8>);
454impl ADCMPINTEN4_R {
455    pub(crate) fn new(bits: u8) -> Self {
456        ADCMPINTEN4_R(crate::FieldReader::new(bits))
457    }
458}
459impl core::ops::Deref for ADCMPINTEN4_R {
460    type Target = crate::FieldReader<u8, u8>;
461    #[inline(always)]
462    fn deref(&self) -> &Self::Target {
463        &self.0
464    }
465}
466#[doc = "Field `ADCMPINTEN4` writer - Channel 4 threshold comparison interrupt enable. See description for channel 0."]
467pub struct ADCMPINTEN4_W<'a> {
468    w: &'a mut W,
469}
470impl<'a> ADCMPINTEN4_W<'a> {
471    #[doc = r"Writes raw bits to the field"]
472    #[inline(always)]
473    pub unsafe fn bits(self, value: u8) -> &'a mut W {
474        self.w.bits = (self.w.bits & !(0x03 << 11)) | ((value as u32 & 0x03) << 11);
475        self.w
476    }
477}
478#[doc = "Field `ADCMPINTEN5` reader - Channel 5 threshold comparison interrupt enable. See description for channel 0."]
479pub struct ADCMPINTEN5_R(crate::FieldReader<u8, u8>);
480impl ADCMPINTEN5_R {
481    pub(crate) fn new(bits: u8) -> Self {
482        ADCMPINTEN5_R(crate::FieldReader::new(bits))
483    }
484}
485impl core::ops::Deref for ADCMPINTEN5_R {
486    type Target = crate::FieldReader<u8, u8>;
487    #[inline(always)]
488    fn deref(&self) -> &Self::Target {
489        &self.0
490    }
491}
492#[doc = "Field `ADCMPINTEN5` writer - Channel 5 threshold comparison interrupt enable. See description for channel 0."]
493pub struct ADCMPINTEN5_W<'a> {
494    w: &'a mut W,
495}
496impl<'a> ADCMPINTEN5_W<'a> {
497    #[doc = r"Writes raw bits to the field"]
498    #[inline(always)]
499    pub unsafe fn bits(self, value: u8) -> &'a mut W {
500        self.w.bits = (self.w.bits & !(0x03 << 13)) | ((value as u32 & 0x03) << 13);
501        self.w
502    }
503}
504#[doc = "Field `ADCMPINTEN6` reader - Channel 6 threshold comparison interrupt enable. See description for channel 0."]
505pub struct ADCMPINTEN6_R(crate::FieldReader<u8, u8>);
506impl ADCMPINTEN6_R {
507    pub(crate) fn new(bits: u8) -> Self {
508        ADCMPINTEN6_R(crate::FieldReader::new(bits))
509    }
510}
511impl core::ops::Deref for ADCMPINTEN6_R {
512    type Target = crate::FieldReader<u8, u8>;
513    #[inline(always)]
514    fn deref(&self) -> &Self::Target {
515        &self.0
516    }
517}
518#[doc = "Field `ADCMPINTEN6` writer - Channel 6 threshold comparison interrupt enable. See description for channel 0."]
519pub struct ADCMPINTEN6_W<'a> {
520    w: &'a mut W,
521}
522impl<'a> ADCMPINTEN6_W<'a> {
523    #[doc = r"Writes raw bits to the field"]
524    #[inline(always)]
525    pub unsafe fn bits(self, value: u8) -> &'a mut W {
526        self.w.bits = (self.w.bits & !(0x03 << 15)) | ((value as u32 & 0x03) << 15);
527        self.w
528    }
529}
530#[doc = "Field `ADCMPINTEN7` reader - Channel 7 threshold comparison interrupt enable. See description for channel 0."]
531pub struct ADCMPINTEN7_R(crate::FieldReader<u8, u8>);
532impl ADCMPINTEN7_R {
533    pub(crate) fn new(bits: u8) -> Self {
534        ADCMPINTEN7_R(crate::FieldReader::new(bits))
535    }
536}
537impl core::ops::Deref for ADCMPINTEN7_R {
538    type Target = crate::FieldReader<u8, u8>;
539    #[inline(always)]
540    fn deref(&self) -> &Self::Target {
541        &self.0
542    }
543}
544#[doc = "Field `ADCMPINTEN7` writer - Channel 7 threshold comparison interrupt enable. See description for channel 0."]
545pub struct ADCMPINTEN7_W<'a> {
546    w: &'a mut W,
547}
548impl<'a> ADCMPINTEN7_W<'a> {
549    #[doc = r"Writes raw bits to the field"]
550    #[inline(always)]
551    pub unsafe fn bits(self, value: u8) -> &'a mut W {
552        self.w.bits = (self.w.bits & !(0x03 << 17)) | ((value as u32 & 0x03) << 17);
553        self.w
554    }
555}
556#[doc = "Field `ADCMPINTEN8` reader - Channel 8 threshold comparison interrupt enable. See description for channel 0."]
557pub struct ADCMPINTEN8_R(crate::FieldReader<u8, u8>);
558impl ADCMPINTEN8_R {
559    pub(crate) fn new(bits: u8) -> Self {
560        ADCMPINTEN8_R(crate::FieldReader::new(bits))
561    }
562}
563impl core::ops::Deref for ADCMPINTEN8_R {
564    type Target = crate::FieldReader<u8, u8>;
565    #[inline(always)]
566    fn deref(&self) -> &Self::Target {
567        &self.0
568    }
569}
570#[doc = "Field `ADCMPINTEN8` writer - Channel 8 threshold comparison interrupt enable. See description for channel 0."]
571pub struct ADCMPINTEN8_W<'a> {
572    w: &'a mut W,
573}
574impl<'a> ADCMPINTEN8_W<'a> {
575    #[doc = r"Writes raw bits to the field"]
576    #[inline(always)]
577    pub unsafe fn bits(self, value: u8) -> &'a mut W {
578        self.w.bits = (self.w.bits & !(0x03 << 19)) | ((value as u32 & 0x03) << 19);
579        self.w
580    }
581}
582#[doc = "Field `ADCMPINTEN9` reader - Channel 9 threshold comparison interrupt enable. See description for channel 0."]
583pub struct ADCMPINTEN9_R(crate::FieldReader<u8, u8>);
584impl ADCMPINTEN9_R {
585    pub(crate) fn new(bits: u8) -> Self {
586        ADCMPINTEN9_R(crate::FieldReader::new(bits))
587    }
588}
589impl core::ops::Deref for ADCMPINTEN9_R {
590    type Target = crate::FieldReader<u8, u8>;
591    #[inline(always)]
592    fn deref(&self) -> &Self::Target {
593        &self.0
594    }
595}
596#[doc = "Field `ADCMPINTEN9` writer - Channel 9 threshold comparison interrupt enable. See description for channel 0."]
597pub struct ADCMPINTEN9_W<'a> {
598    w: &'a mut W,
599}
600impl<'a> ADCMPINTEN9_W<'a> {
601    #[doc = r"Writes raw bits to the field"]
602    #[inline(always)]
603    pub unsafe fn bits(self, value: u8) -> &'a mut W {
604        self.w.bits = (self.w.bits & !(0x03 << 21)) | ((value as u32 & 0x03) << 21);
605        self.w
606    }
607}
608#[doc = "Field `ADCMPINTEN10` reader - Channel 10 threshold comparison interrupt enable. See description for channel 0."]
609pub struct ADCMPINTEN10_R(crate::FieldReader<u8, u8>);
610impl ADCMPINTEN10_R {
611    pub(crate) fn new(bits: u8) -> Self {
612        ADCMPINTEN10_R(crate::FieldReader::new(bits))
613    }
614}
615impl core::ops::Deref for ADCMPINTEN10_R {
616    type Target = crate::FieldReader<u8, u8>;
617    #[inline(always)]
618    fn deref(&self) -> &Self::Target {
619        &self.0
620    }
621}
622#[doc = "Field `ADCMPINTEN10` writer - Channel 10 threshold comparison interrupt enable. See description for channel 0."]
623pub struct ADCMPINTEN10_W<'a> {
624    w: &'a mut W,
625}
626impl<'a> ADCMPINTEN10_W<'a> {
627    #[doc = r"Writes raw bits to the field"]
628    #[inline(always)]
629    pub unsafe fn bits(self, value: u8) -> &'a mut W {
630        self.w.bits = (self.w.bits & !(0x03 << 23)) | ((value as u32 & 0x03) << 23);
631        self.w
632    }
633}
634#[doc = "Field `ADCMPINTEN11` reader - Channel 21 threshold comparison interrupt enable. See description for channel 0."]
635pub struct ADCMPINTEN11_R(crate::FieldReader<u8, u8>);
636impl ADCMPINTEN11_R {
637    pub(crate) fn new(bits: u8) -> Self {
638        ADCMPINTEN11_R(crate::FieldReader::new(bits))
639    }
640}
641impl core::ops::Deref for ADCMPINTEN11_R {
642    type Target = crate::FieldReader<u8, u8>;
643    #[inline(always)]
644    fn deref(&self) -> &Self::Target {
645        &self.0
646    }
647}
648#[doc = "Field `ADCMPINTEN11` writer - Channel 21 threshold comparison interrupt enable. See description for channel 0."]
649pub struct ADCMPINTEN11_W<'a> {
650    w: &'a mut W,
651}
652impl<'a> ADCMPINTEN11_W<'a> {
653    #[doc = r"Writes raw bits to the field"]
654    #[inline(always)]
655    pub unsafe fn bits(self, value: u8) -> &'a mut W {
656        self.w.bits = (self.w.bits & !(0x03 << 25)) | ((value as u32 & 0x03) << 25);
657        self.w
658    }
659}
660impl R {
661    #[doc = "Bit 0 - Sequence A interrupt enable."]
662    #[inline(always)]
663    pub fn seqa_inten(&self) -> SEQA_INTEN_R {
664        SEQA_INTEN_R::new((self.bits & 0x01) != 0)
665    }
666    #[doc = "Bit 1 - Sequence B interrupt enable."]
667    #[inline(always)]
668    pub fn seqb_inten(&self) -> SEQB_INTEN_R {
669        SEQB_INTEN_R::new(((self.bits >> 1) & 0x01) != 0)
670    }
671    #[doc = "Bit 2 - Overrun interrupt enable."]
672    #[inline(always)]
673    pub fn ovr_inten(&self) -> OVR_INTEN_R {
674        OVR_INTEN_R::new(((self.bits >> 2) & 0x01) != 0)
675    }
676    #[doc = "Bits 3:4 - Threshold comparison interrupt enable for channel 0."]
677    #[inline(always)]
678    pub fn adcmpinten0(&self) -> ADCMPINTEN0_R {
679        ADCMPINTEN0_R::new(((self.bits >> 3) & 0x03) as u8)
680    }
681    #[doc = "Bits 5:6 - Channel 1 threshold comparison interrupt enable. See description for channel 0."]
682    #[inline(always)]
683    pub fn adcmpinten1(&self) -> ADCMPINTEN1_R {
684        ADCMPINTEN1_R::new(((self.bits >> 5) & 0x03) as u8)
685    }
686    #[doc = "Bits 7:8 - Channel 2 threshold comparison interrupt enable. See description for channel 0."]
687    #[inline(always)]
688    pub fn adcmpinten2(&self) -> ADCMPINTEN2_R {
689        ADCMPINTEN2_R::new(((self.bits >> 7) & 0x03) as u8)
690    }
691    #[doc = "Bits 9:10 - Channel 3 threshold comparison interrupt enable. See description for channel 0."]
692    #[inline(always)]
693    pub fn adcmpinten3(&self) -> ADCMPINTEN3_R {
694        ADCMPINTEN3_R::new(((self.bits >> 9) & 0x03) as u8)
695    }
696    #[doc = "Bits 11:12 - Channel 4 threshold comparison interrupt enable. See description for channel 0."]
697    #[inline(always)]
698    pub fn adcmpinten4(&self) -> ADCMPINTEN4_R {
699        ADCMPINTEN4_R::new(((self.bits >> 11) & 0x03) as u8)
700    }
701    #[doc = "Bits 13:14 - Channel 5 threshold comparison interrupt enable. See description for channel 0."]
702    #[inline(always)]
703    pub fn adcmpinten5(&self) -> ADCMPINTEN5_R {
704        ADCMPINTEN5_R::new(((self.bits >> 13) & 0x03) as u8)
705    }
706    #[doc = "Bits 15:16 - Channel 6 threshold comparison interrupt enable. See description for channel 0."]
707    #[inline(always)]
708    pub fn adcmpinten6(&self) -> ADCMPINTEN6_R {
709        ADCMPINTEN6_R::new(((self.bits >> 15) & 0x03) as u8)
710    }
711    #[doc = "Bits 17:18 - Channel 7 threshold comparison interrupt enable. See description for channel 0."]
712    #[inline(always)]
713    pub fn adcmpinten7(&self) -> ADCMPINTEN7_R {
714        ADCMPINTEN7_R::new(((self.bits >> 17) & 0x03) as u8)
715    }
716    #[doc = "Bits 19:20 - Channel 8 threshold comparison interrupt enable. See description for channel 0."]
717    #[inline(always)]
718    pub fn adcmpinten8(&self) -> ADCMPINTEN8_R {
719        ADCMPINTEN8_R::new(((self.bits >> 19) & 0x03) as u8)
720    }
721    #[doc = "Bits 21:22 - Channel 9 threshold comparison interrupt enable. See description for channel 0."]
722    #[inline(always)]
723    pub fn adcmpinten9(&self) -> ADCMPINTEN9_R {
724        ADCMPINTEN9_R::new(((self.bits >> 21) & 0x03) as u8)
725    }
726    #[doc = "Bits 23:24 - Channel 10 threshold comparison interrupt enable. See description for channel 0."]
727    #[inline(always)]
728    pub fn adcmpinten10(&self) -> ADCMPINTEN10_R {
729        ADCMPINTEN10_R::new(((self.bits >> 23) & 0x03) as u8)
730    }
731    #[doc = "Bits 25:26 - Channel 21 threshold comparison interrupt enable. See description for channel 0."]
732    #[inline(always)]
733    pub fn adcmpinten11(&self) -> ADCMPINTEN11_R {
734        ADCMPINTEN11_R::new(((self.bits >> 25) & 0x03) as u8)
735    }
736}
737impl W {
738    #[doc = "Bit 0 - Sequence A interrupt enable."]
739    #[inline(always)]
740    pub fn seqa_inten(&mut self) -> SEQA_INTEN_W {
741        SEQA_INTEN_W { w: self }
742    }
743    #[doc = "Bit 1 - Sequence B interrupt enable."]
744    #[inline(always)]
745    pub fn seqb_inten(&mut self) -> SEQB_INTEN_W {
746        SEQB_INTEN_W { w: self }
747    }
748    #[doc = "Bit 2 - Overrun interrupt enable."]
749    #[inline(always)]
750    pub fn ovr_inten(&mut self) -> OVR_INTEN_W {
751        OVR_INTEN_W { w: self }
752    }
753    #[doc = "Bits 3:4 - Threshold comparison interrupt enable for channel 0."]
754    #[inline(always)]
755    pub fn adcmpinten0(&mut self) -> ADCMPINTEN0_W {
756        ADCMPINTEN0_W { w: self }
757    }
758    #[doc = "Bits 5:6 - Channel 1 threshold comparison interrupt enable. See description for channel 0."]
759    #[inline(always)]
760    pub fn adcmpinten1(&mut self) -> ADCMPINTEN1_W {
761        ADCMPINTEN1_W { w: self }
762    }
763    #[doc = "Bits 7:8 - Channel 2 threshold comparison interrupt enable. See description for channel 0."]
764    #[inline(always)]
765    pub fn adcmpinten2(&mut self) -> ADCMPINTEN2_W {
766        ADCMPINTEN2_W { w: self }
767    }
768    #[doc = "Bits 9:10 - Channel 3 threshold comparison interrupt enable. See description for channel 0."]
769    #[inline(always)]
770    pub fn adcmpinten3(&mut self) -> ADCMPINTEN3_W {
771        ADCMPINTEN3_W { w: self }
772    }
773    #[doc = "Bits 11:12 - Channel 4 threshold comparison interrupt enable. See description for channel 0."]
774    #[inline(always)]
775    pub fn adcmpinten4(&mut self) -> ADCMPINTEN4_W {
776        ADCMPINTEN4_W { w: self }
777    }
778    #[doc = "Bits 13:14 - Channel 5 threshold comparison interrupt enable. See description for channel 0."]
779    #[inline(always)]
780    pub fn adcmpinten5(&mut self) -> ADCMPINTEN5_W {
781        ADCMPINTEN5_W { w: self }
782    }
783    #[doc = "Bits 15:16 - Channel 6 threshold comparison interrupt enable. See description for channel 0."]
784    #[inline(always)]
785    pub fn adcmpinten6(&mut self) -> ADCMPINTEN6_W {
786        ADCMPINTEN6_W { w: self }
787    }
788    #[doc = "Bits 17:18 - Channel 7 threshold comparison interrupt enable. See description for channel 0."]
789    #[inline(always)]
790    pub fn adcmpinten7(&mut self) -> ADCMPINTEN7_W {
791        ADCMPINTEN7_W { w: self }
792    }
793    #[doc = "Bits 19:20 - Channel 8 threshold comparison interrupt enable. See description for channel 0."]
794    #[inline(always)]
795    pub fn adcmpinten8(&mut self) -> ADCMPINTEN8_W {
796        ADCMPINTEN8_W { w: self }
797    }
798    #[doc = "Bits 21:22 - Channel 9 threshold comparison interrupt enable. See description for channel 0."]
799    #[inline(always)]
800    pub fn adcmpinten9(&mut self) -> ADCMPINTEN9_W {
801        ADCMPINTEN9_W { w: self }
802    }
803    #[doc = "Bits 23:24 - Channel 10 threshold comparison interrupt enable. See description for channel 0."]
804    #[inline(always)]
805    pub fn adcmpinten10(&mut self) -> ADCMPINTEN10_W {
806        ADCMPINTEN10_W { w: self }
807    }
808    #[doc = "Bits 25:26 - Channel 21 threshold comparison interrupt enable. See description for channel 0."]
809    #[inline(always)]
810    pub fn adcmpinten11(&mut self) -> ADCMPINTEN11_W {
811        ADCMPINTEN11_W { w: self }
812    }
813    #[doc = "Writes raw bits to the register."]
814    #[inline(always)]
815    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
816        self.0.bits(bits);
817        self
818    }
819}
820#[doc = "ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inten](index.html) module"]
821pub struct INTEN_SPEC;
822impl crate::RegisterSpec for INTEN_SPEC {
823    type Ux = u32;
824}
825#[doc = "`read()` method returns [inten::R](R) reader structure"]
826impl crate::Readable for INTEN_SPEC {
827    type Reader = R;
828}
829#[doc = "`write(|w| ..)` method takes [inten::W](W) writer structure"]
830impl crate::Writable for INTEN_SPEC {
831    type Writer = W;
832}
833#[doc = "`reset()` method sets INTEN to value 0"]
834impl crate::Resettable for INTEN_SPEC {
835    #[inline(always)]
836    fn reset_value() -> Self::Ux {
837        0
838    }
839}
lpc845_pac/adc0/inten.rs

lpc845_pac/adc0/
inten.rs
