Struct lpc845_pac::spi0::intenset::W [−][src]
pub struct W(_);
Expand description
Register INTENSET
writer
Implementations
Bit 0 - Determines whether an interrupt occurs when receiver data is available.
Bit 1 - Determines whether an interrupt occurs when the transmitter holding register is available.
Bit 2 - Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur.
Bit 3 - Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available.
Bit 4 - Determines whether an interrupt occurs when the Slave Select is asserted.
Bit 5 - Determines whether an interrupt occurs when the Slave Select is deasserted.
Methods from Deref<Target = W<INTENSET_SPEC>>
Trait Implementations
Performs the conversion.