1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CTRL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CTRL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Mode of operation. May only change from 0 to another value. So, if 2 or 3, must be changed to 0 1st. Any attempt to go from non-0 to non-0 will result in 0 anyway.\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum POLLMODE_A {
41 #[doc = "0: None, inactive. Poll and time counters are turned off. Writing this will reset state and stop any collection in progress. Note: this has no effect on STATUS - those must be cleared manually."]
42 NONE = 0,
43 #[doc = "1: Poll now - forces a manual poll to be started immediately, using XPINSEL X pin(s) to activate in the integration loop (all pins set together). Self clears - clear is not indication it is done (see STATUS)."]
44 POLL_NOW = 1,
45 #[doc = "2: Normal polling using poll delay from POLL_TCNT register. This will start with the poll delay (which can be 0)."]
46 NORMAL = 2,
47 #[doc = "3: The CAPT block will operate in low-power mode. This means it will use GPIO as input, use combination touch measurements, and assume it is to wake the system. This will use the POLL_TCNT poll delay, and start with the delay."]
48 LOW_POWER_MODE = 3,
49}
50impl From<POLLMODE_A> for u8 {
51 #[inline(always)]
52 fn from(variant: POLLMODE_A) -> Self {
53 variant as _
54 }
55}
56#[doc = "Field `POLLMODE` reader - Mode of operation. May only change from 0 to another value. So, if 2 or 3, must be changed to 0 1st. Any attempt to go from non-0 to non-0 will result in 0 anyway."]
57pub struct POLLMODE_R(crate::FieldReader<u8, POLLMODE_A>);
58impl POLLMODE_R {
59 pub(crate) fn new(bits: u8) -> Self {
60 POLLMODE_R(crate::FieldReader::new(bits))
61 }
62 #[doc = r"Get enumerated values variant"]
63 #[inline(always)]
64 pub fn variant(&self) -> POLLMODE_A {
65 match self.bits {
66 0 => POLLMODE_A::NONE,
67 1 => POLLMODE_A::POLL_NOW,
68 2 => POLLMODE_A::NORMAL,
69 3 => POLLMODE_A::LOW_POWER_MODE,
70 _ => unreachable!(),
71 }
72 }
73 #[doc = "Checks if the value of the field is `NONE`"]
74 #[inline(always)]
75 pub fn is_none(&self) -> bool {
76 **self == POLLMODE_A::NONE
77 }
78 #[doc = "Checks if the value of the field is `POLL_NOW`"]
79 #[inline(always)]
80 pub fn is_poll_now(&self) -> bool {
81 **self == POLLMODE_A::POLL_NOW
82 }
83 #[doc = "Checks if the value of the field is `NORMAL`"]
84 #[inline(always)]
85 pub fn is_normal(&self) -> bool {
86 **self == POLLMODE_A::NORMAL
87 }
88 #[doc = "Checks if the value of the field is `LOW_POWER_MODE`"]
89 #[inline(always)]
90 pub fn is_low_power_mode(&self) -> bool {
91 **self == POLLMODE_A::LOW_POWER_MODE
92 }
93}
94impl core::ops::Deref for POLLMODE_R {
95 type Target = crate::FieldReader<u8, POLLMODE_A>;
96 #[inline(always)]
97 fn deref(&self) -> &Self::Target {
98 &self.0
99 }
100}
101#[doc = "Field `POLLMODE` writer - Mode of operation. May only change from 0 to another value. So, if 2 or 3, must be changed to 0 1st. Any attempt to go from non-0 to non-0 will result in 0 anyway."]
102pub struct POLLMODE_W<'a> {
103 w: &'a mut W,
104}
105impl<'a> POLLMODE_W<'a> {
106 #[doc = r"Writes `variant` to the field"]
107 #[inline(always)]
108 pub fn variant(self, variant: POLLMODE_A) -> &'a mut W {
109 self.bits(variant.into())
110 }
111 #[doc = "None, inactive. Poll and time counters are turned off. Writing this will reset state and stop any collection in progress. Note: this has no effect on STATUS - those must be cleared manually."]
112 #[inline(always)]
113 pub fn none(self) -> &'a mut W {
114 self.variant(POLLMODE_A::NONE)
115 }
116 #[doc = "Poll now - forces a manual poll to be started immediately, using XPINSEL X pin(s) to activate in the integration loop (all pins set together). Self clears - clear is not indication it is done (see STATUS)."]
117 #[inline(always)]
118 pub fn poll_now(self) -> &'a mut W {
119 self.variant(POLLMODE_A::POLL_NOW)
120 }
121 #[doc = "Normal polling using poll delay from POLL_TCNT register. This will start with the poll delay (which can be 0)."]
122 #[inline(always)]
123 pub fn normal(self) -> &'a mut W {
124 self.variant(POLLMODE_A::NORMAL)
125 }
126 #[doc = "The CAPT block will operate in low-power mode. This means it will use GPIO as input, use combination touch measurements, and assume it is to wake the system. This will use the POLL_TCNT poll delay, and start with the delay."]
127 #[inline(always)]
128 pub fn low_power_mode(self) -> &'a mut W {
129 self.variant(POLLMODE_A::LOW_POWER_MODE)
130 }
131 #[doc = r"Writes raw bits to the field"]
132 #[inline(always)]
133 pub fn bits(self, value: u8) -> &'a mut W {
134 self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03);
135 self.w
136 }
137}
138#[doc = "Selects type of Touch arrangement to use and so how to handle XPINSEL bits\n\nValue on reset: 0"]
139#[derive(Clone, Copy, Debug, PartialEq)]
140#[repr(u8)]
141pub enum TYPE_A {
142 #[doc = "0: Normal - all X elements are treated as normal, such as buttons and sliders."]
143 TYPE_0 = 0,
144 #[doc = "1: 3x3 grid using NXP Complementary measurements. The 1st 9 Xs are assumed to be the 3x3 grid. After that would be normal X elements. This will also allow 3x1 and 3x2 Note: Only possible if XMAX in STATUS is >=8"]
145 TYPE_1 = 1,
146 #[doc = "2: 5 Sensors interleaved to act as 3x3 touch area using NXP Complementary measurements. 1st 5 Xs used for this, all remaining are treated as normal. Note that if 16 X pins allowed, the 16th will not be usable when TYPE=1. (use TYPE=0 and select 1 smaller than 15 ( and any others from 1 smaller than 5 on up in XPINSEL)."]
147 TYPE_2 = 2,
148 #[doc = "3: 9 Sensors interleaved to act as 5x5 touch area using NXP Complementary measurements. 1st 9 Xs used for this, all remaining are treated as normal. Note: Only possible if XMAX in STATUS is >=8"]
149 TYPE_3 = 3,
150}
151impl From<TYPE_A> for u8 {
152 #[inline(always)]
153 fn from(variant: TYPE_A) -> Self {
154 variant as _
155 }
156}
157#[doc = "Field `TYPE` reader - Selects type of Touch arrangement to use and so how to handle XPINSEL bits"]
158pub struct TYPE_R(crate::FieldReader<u8, TYPE_A>);
159impl TYPE_R {
160 pub(crate) fn new(bits: u8) -> Self {
161 TYPE_R(crate::FieldReader::new(bits))
162 }
163 #[doc = r"Get enumerated values variant"]
164 #[inline(always)]
165 pub fn variant(&self) -> TYPE_A {
166 match self.bits {
167 0 => TYPE_A::TYPE_0,
168 1 => TYPE_A::TYPE_1,
169 2 => TYPE_A::TYPE_2,
170 3 => TYPE_A::TYPE_3,
171 _ => unreachable!(),
172 }
173 }
174 #[doc = "Checks if the value of the field is `TYPE_0`"]
175 #[inline(always)]
176 pub fn is_type_0(&self) -> bool {
177 **self == TYPE_A::TYPE_0
178 }
179 #[doc = "Checks if the value of the field is `TYPE_1`"]
180 #[inline(always)]
181 pub fn is_type_1(&self) -> bool {
182 **self == TYPE_A::TYPE_1
183 }
184 #[doc = "Checks if the value of the field is `TYPE_2`"]
185 #[inline(always)]
186 pub fn is_type_2(&self) -> bool {
187 **self == TYPE_A::TYPE_2
188 }
189 #[doc = "Checks if the value of the field is `TYPE_3`"]
190 #[inline(always)]
191 pub fn is_type_3(&self) -> bool {
192 **self == TYPE_A::TYPE_3
193 }
194}
195impl core::ops::Deref for TYPE_R {
196 type Target = crate::FieldReader<u8, TYPE_A>;
197 #[inline(always)]
198 fn deref(&self) -> &Self::Target {
199 &self.0
200 }
201}
202#[doc = "Field `TYPE` writer - Selects type of Touch arrangement to use and so how to handle XPINSEL bits"]
203pub struct TYPE_W<'a> {
204 w: &'a mut W,
205}
206impl<'a> TYPE_W<'a> {
207 #[doc = r"Writes `variant` to the field"]
208 #[inline(always)]
209 pub fn variant(self, variant: TYPE_A) -> &'a mut W {
210 self.bits(variant.into())
211 }
212 #[doc = "Normal - all X elements are treated as normal, such as buttons and sliders."]
213 #[inline(always)]
214 pub fn type_0(self) -> &'a mut W {
215 self.variant(TYPE_A::TYPE_0)
216 }
217 #[doc = "3x3 grid using NXP Complementary measurements. The 1st 9 Xs are assumed to be the 3x3 grid. After that would be normal X elements. This will also allow 3x1 and 3x2 Note: Only possible if XMAX in STATUS is >=8"]
218 #[inline(always)]
219 pub fn type_1(self) -> &'a mut W {
220 self.variant(TYPE_A::TYPE_1)
221 }
222 #[doc = "5 Sensors interleaved to act as 3x3 touch area using NXP Complementary measurements. 1st 5 Xs used for this, all remaining are treated as normal. Note that if 16 X pins allowed, the 16th will not be usable when TYPE=1. (use TYPE=0 and select 1 smaller than 15 ( and any others from 1 smaller than 5 on up in XPINSEL)."]
223 #[inline(always)]
224 pub fn type_2(self) -> &'a mut W {
225 self.variant(TYPE_A::TYPE_2)
226 }
227 #[doc = "9 Sensors interleaved to act as 5x5 touch area using NXP Complementary measurements. 1st 9 Xs used for this, all remaining are treated as normal. Note: Only possible if XMAX in STATUS is >=8"]
228 #[inline(always)]
229 pub fn type_3(self) -> &'a mut W {
230 self.variant(TYPE_A::TYPE_3)
231 }
232 #[doc = r"Writes raw bits to the field"]
233 #[inline(always)]
234 pub fn bits(self, value: u8) -> &'a mut W {
235 self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2);
236 self.w
237 }
238}
239#[doc = "This selects what is being used as the trigger\n\nValue on reset: 0"]
240#[derive(Clone, Copy, Debug, PartialEq)]
241pub enum TRIGGER_A {
242 #[doc = "0: Uses YH GPIO. This is not normally used except in Low-power mode. But, it can be used with POLLNOW to baseline that measurement."]
243 USES_YH_GPIO = 0,
244 #[doc = "1: ACMP (if fitted). This assumes the ACMP state is fed in asynchronously and it will sample."]
245 ACMP = 1,
246}
247impl From<TRIGGER_A> for bool {
248 #[inline(always)]
249 fn from(variant: TRIGGER_A) -> Self {
250 variant as u8 != 0
251 }
252}
253#[doc = "Field `TRIGGER` reader - This selects what is being used as the trigger"]
254pub struct TRIGGER_R(crate::FieldReader<bool, TRIGGER_A>);
255impl TRIGGER_R {
256 pub(crate) fn new(bits: bool) -> Self {
257 TRIGGER_R(crate::FieldReader::new(bits))
258 }
259 #[doc = r"Get enumerated values variant"]
260 #[inline(always)]
261 pub fn variant(&self) -> TRIGGER_A {
262 match self.bits {
263 false => TRIGGER_A::USES_YH_GPIO,
264 true => TRIGGER_A::ACMP,
265 }
266 }
267 #[doc = "Checks if the value of the field is `USES_YH_GPIO`"]
268 #[inline(always)]
269 pub fn is_uses_yh_gpio(&self) -> bool {
270 **self == TRIGGER_A::USES_YH_GPIO
271 }
272 #[doc = "Checks if the value of the field is `ACMP`"]
273 #[inline(always)]
274 pub fn is_acmp(&self) -> bool {
275 **self == TRIGGER_A::ACMP
276 }
277}
278impl core::ops::Deref for TRIGGER_R {
279 type Target = crate::FieldReader<bool, TRIGGER_A>;
280 #[inline(always)]
281 fn deref(&self) -> &Self::Target {
282 &self.0
283 }
284}
285#[doc = "Field `TRIGGER` writer - This selects what is being used as the trigger"]
286pub struct TRIGGER_W<'a> {
287 w: &'a mut W,
288}
289impl<'a> TRIGGER_W<'a> {
290 #[doc = r"Writes `variant` to the field"]
291 #[inline(always)]
292 pub fn variant(self, variant: TRIGGER_A) -> &'a mut W {
293 self.bit(variant.into())
294 }
295 #[doc = "Uses YH GPIO. This is not normally used except in Low-power mode. But, it can be used with POLLNOW to baseline that measurement."]
296 #[inline(always)]
297 pub fn uses_yh_gpio(self) -> &'a mut W {
298 self.variant(TRIGGER_A::USES_YH_GPIO)
299 }
300 #[doc = "ACMP (if fitted). This assumes the ACMP state is fed in asynchronously and it will sample."]
301 #[inline(always)]
302 pub fn acmp(self) -> &'a mut W {
303 self.variant(TRIGGER_A::ACMP)
304 }
305 #[doc = r"Sets the field bit"]
306 #[inline(always)]
307 pub fn set_bit(self) -> &'a mut W {
308 self.bit(true)
309 }
310 #[doc = r"Clears the field bit"]
311 #[inline(always)]
312 pub fn clear_bit(self) -> &'a mut W {
313 self.bit(false)
314 }
315 #[doc = r"Writes raw bits to the field"]
316 #[inline(always)]
317 pub fn bit(self, value: bool) -> &'a mut W {
318 self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
319 self.w
320 }
321}
322#[doc = "Field `WAIT` reader - If 0, the block will continue its X based measurements, even if the TOUCH register has not been read (and so could OVERRUN). If 1, it will wait until read when a touch (TOUCH's ISTOUCH bit is set) before starting the next. This should not normally be needed."]
323pub struct WAIT_R(crate::FieldReader<bool, bool>);
324impl WAIT_R {
325 pub(crate) fn new(bits: bool) -> Self {
326 WAIT_R(crate::FieldReader::new(bits))
327 }
328}
329impl core::ops::Deref for WAIT_R {
330 type Target = crate::FieldReader<bool, bool>;
331 #[inline(always)]
332 fn deref(&self) -> &Self::Target {
333 &self.0
334 }
335}
336#[doc = "Field `WAIT` writer - If 0, the block will continue its X based measurements, even if the TOUCH register has not been read (and so could OVERRUN). If 1, it will wait until read when a touch (TOUCH's ISTOUCH bit is set) before starting the next. This should not normally be needed."]
337pub struct WAIT_W<'a> {
338 w: &'a mut W,
339}
340impl<'a> WAIT_W<'a> {
341 #[doc = r"Sets the field bit"]
342 #[inline(always)]
343 pub fn set_bit(self) -> &'a mut W {
344 self.bit(true)
345 }
346 #[doc = r"Clears the field bit"]
347 #[inline(always)]
348 pub fn clear_bit(self) -> &'a mut W {
349 self.bit(false)
350 }
351 #[doc = r"Writes raw bits to the field"]
352 #[inline(always)]
353 pub fn bit(self, value: bool) -> &'a mut W {
354 self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
355 self.w
356 }
357}
358#[doc = "If not 0, will use the DMA to read out touch events from TOUCH register. The values are shown below. This may be changed while active.\n\nValue on reset: 0"]
359#[derive(Clone, Copy, Debug, PartialEq)]
360#[repr(u8)]
361pub enum DMA_A {
362 #[doc = "0: No DMA. Application will use ISRs to read out data"]
363 DMA_0 = 0,
364 #[doc = "1: Trigger DMA on Touch events"]
365 DMA_1 = 1,
366 #[doc = "2: Trigger DMA on both Touch and No-Touch events"]
367 DMA_2 = 2,
368 #[doc = "3: Trigger DMA on both plus Timeout."]
369 DMA_3 = 3,
370}
371impl From<DMA_A> for u8 {
372 #[inline(always)]
373 fn from(variant: DMA_A) -> Self {
374 variant as _
375 }
376}
377#[doc = "Field `DMA` reader - If not 0, will use the DMA to read out touch events from TOUCH register. The values are shown below. This may be changed while active."]
378pub struct DMA_R(crate::FieldReader<u8, DMA_A>);
379impl DMA_R {
380 pub(crate) fn new(bits: u8) -> Self {
381 DMA_R(crate::FieldReader::new(bits))
382 }
383 #[doc = r"Get enumerated values variant"]
384 #[inline(always)]
385 pub fn variant(&self) -> DMA_A {
386 match self.bits {
387 0 => DMA_A::DMA_0,
388 1 => DMA_A::DMA_1,
389 2 => DMA_A::DMA_2,
390 3 => DMA_A::DMA_3,
391 _ => unreachable!(),
392 }
393 }
394 #[doc = "Checks if the value of the field is `DMA_0`"]
395 #[inline(always)]
396 pub fn is_dma_0(&self) -> bool {
397 **self == DMA_A::DMA_0
398 }
399 #[doc = "Checks if the value of the field is `DMA_1`"]
400 #[inline(always)]
401 pub fn is_dma_1(&self) -> bool {
402 **self == DMA_A::DMA_1
403 }
404 #[doc = "Checks if the value of the field is `DMA_2`"]
405 #[inline(always)]
406 pub fn is_dma_2(&self) -> bool {
407 **self == DMA_A::DMA_2
408 }
409 #[doc = "Checks if the value of the field is `DMA_3`"]
410 #[inline(always)]
411 pub fn is_dma_3(&self) -> bool {
412 **self == DMA_A::DMA_3
413 }
414}
415impl core::ops::Deref for DMA_R {
416 type Target = crate::FieldReader<u8, DMA_A>;
417 #[inline(always)]
418 fn deref(&self) -> &Self::Target {
419 &self.0
420 }
421}
422#[doc = "Field `DMA` writer - If not 0, will use the DMA to read out touch events from TOUCH register. The values are shown below. This may be changed while active."]
423pub struct DMA_W<'a> {
424 w: &'a mut W,
425}
426impl<'a> DMA_W<'a> {
427 #[doc = r"Writes `variant` to the field"]
428 #[inline(always)]
429 pub fn variant(self, variant: DMA_A) -> &'a mut W {
430 self.bits(variant.into())
431 }
432 #[doc = "No DMA. Application will use ISRs to read out data"]
433 #[inline(always)]
434 pub fn dma_0(self) -> &'a mut W {
435 self.variant(DMA_A::DMA_0)
436 }
437 #[doc = "Trigger DMA on Touch events"]
438 #[inline(always)]
439 pub fn dma_1(self) -> &'a mut W {
440 self.variant(DMA_A::DMA_1)
441 }
442 #[doc = "Trigger DMA on both Touch and No-Touch events"]
443 #[inline(always)]
444 pub fn dma_2(self) -> &'a mut W {
445 self.variant(DMA_A::DMA_2)
446 }
447 #[doc = "Trigger DMA on both plus Timeout."]
448 #[inline(always)]
449 pub fn dma_3(self) -> &'a mut W {
450 self.variant(DMA_A::DMA_3)
451 }
452 #[doc = r"Writes raw bits to the field"]
453 #[inline(always)]
454 pub fn bits(self, value: u8) -> &'a mut W {
455 self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u32 & 0x03) << 6);
456 self.w
457 }
458}
459#[doc = "Functional clock divider, or 0 if no divide. The term \"clocks\" in this spec then refer to divided clocks. For a 12MHz input (e.g. FRO 12MHz), this would normally be set to generate a 4MHz output (so, 2). For a 1MHz input, it should be 0. Note for internal use: this does not produce a 50/50 duty cycle when non even divide.\n\nValue on reset: 0"]
460#[derive(Clone, Copy, Debug, PartialEq)]
461#[repr(u8)]
462pub enum FDIV_A {
463 #[doc = "0: No divide"]
464 FDIV_0 = 0,
465 #[doc = "1: /2"]
466 FDIV_1 = 1,
467 #[doc = "2: /3"]
468 FDIV_2 = 2,
469 #[doc = "3: /4"]
470 FDIV_3 = 3,
471 #[doc = "4: /5"]
472 FDIV_4 = 4,
473 #[doc = "5: /6"]
474 FDIV_5 = 5,
475 #[doc = "7: /(FDIV+1)"]
476 FDIV_7 = 7,
477 #[doc = "8: /(FDIV+1)"]
478 FDIV_8 = 8,
479 #[doc = "9: /(FDIV+1)"]
480 FDIV_9 = 9,
481 #[doc = "10: /(FDIV+1)"]
482 FDIV_10 = 10,
483 #[doc = "11: /(FDIV+1)"]
484 FDIV_11 = 11,
485 #[doc = "12: /(FDIV+1)"]
486 FDIV_12 = 12,
487 #[doc = "13: /(FDIV+1)"]
488 FDIV_13 = 13,
489 #[doc = "14: /(FDIV+1)"]
490 FDIV_14 = 14,
491 #[doc = "15: /(FDIV+1)"]
492 FDIV_15 = 15,
493}
494impl From<FDIV_A> for u8 {
495 #[inline(always)]
496 fn from(variant: FDIV_A) -> Self {
497 variant as _
498 }
499}
500#[doc = "Field `FDIV` reader - Functional clock divider, or 0 if no divide. The term \"clocks\" in this spec then refer to divided clocks. For a 12MHz input (e.g. FRO 12MHz), this would normally be set to generate a 4MHz output (so, 2). For a 1MHz input, it should be 0. Note for internal use: this does not produce a 50/50 duty cycle when non even divide."]
501pub struct FDIV_R(crate::FieldReader<u8, FDIV_A>);
502impl FDIV_R {
503 pub(crate) fn new(bits: u8) -> Self {
504 FDIV_R(crate::FieldReader::new(bits))
505 }
506 #[doc = r"Get enumerated values variant"]
507 #[inline(always)]
508 pub fn variant(&self) -> Option<FDIV_A> {
509 match self.bits {
510 0 => Some(FDIV_A::FDIV_0),
511 1 => Some(FDIV_A::FDIV_1),
512 2 => Some(FDIV_A::FDIV_2),
513 3 => Some(FDIV_A::FDIV_3),
514 4 => Some(FDIV_A::FDIV_4),
515 5 => Some(FDIV_A::FDIV_5),
516 7 => Some(FDIV_A::FDIV_7),
517 8 => Some(FDIV_A::FDIV_8),
518 9 => Some(FDIV_A::FDIV_9),
519 10 => Some(FDIV_A::FDIV_10),
520 11 => Some(FDIV_A::FDIV_11),
521 12 => Some(FDIV_A::FDIV_12),
522 13 => Some(FDIV_A::FDIV_13),
523 14 => Some(FDIV_A::FDIV_14),
524 15 => Some(FDIV_A::FDIV_15),
525 _ => None,
526 }
527 }
528 #[doc = "Checks if the value of the field is `FDIV_0`"]
529 #[inline(always)]
530 pub fn is_fdiv_0(&self) -> bool {
531 **self == FDIV_A::FDIV_0
532 }
533 #[doc = "Checks if the value of the field is `FDIV_1`"]
534 #[inline(always)]
535 pub fn is_fdiv_1(&self) -> bool {
536 **self == FDIV_A::FDIV_1
537 }
538 #[doc = "Checks if the value of the field is `FDIV_2`"]
539 #[inline(always)]
540 pub fn is_fdiv_2(&self) -> bool {
541 **self == FDIV_A::FDIV_2
542 }
543 #[doc = "Checks if the value of the field is `FDIV_3`"]
544 #[inline(always)]
545 pub fn is_fdiv_3(&self) -> bool {
546 **self == FDIV_A::FDIV_3
547 }
548 #[doc = "Checks if the value of the field is `FDIV_4`"]
549 #[inline(always)]
550 pub fn is_fdiv_4(&self) -> bool {
551 **self == FDIV_A::FDIV_4
552 }
553 #[doc = "Checks if the value of the field is `FDIV_5`"]
554 #[inline(always)]
555 pub fn is_fdiv_5(&self) -> bool {
556 **self == FDIV_A::FDIV_5
557 }
558 #[doc = "Checks if the value of the field is `FDIV_7`"]
559 #[inline(always)]
560 pub fn is_fdiv_7(&self) -> bool {
561 **self == FDIV_A::FDIV_7
562 }
563 #[doc = "Checks if the value of the field is `FDIV_8`"]
564 #[inline(always)]
565 pub fn is_fdiv_8(&self) -> bool {
566 **self == FDIV_A::FDIV_8
567 }
568 #[doc = "Checks if the value of the field is `FDIV_9`"]
569 #[inline(always)]
570 pub fn is_fdiv_9(&self) -> bool {
571 **self == FDIV_A::FDIV_9
572 }
573 #[doc = "Checks if the value of the field is `FDIV_10`"]
574 #[inline(always)]
575 pub fn is_fdiv_10(&self) -> bool {
576 **self == FDIV_A::FDIV_10
577 }
578 #[doc = "Checks if the value of the field is `FDIV_11`"]
579 #[inline(always)]
580 pub fn is_fdiv_11(&self) -> bool {
581 **self == FDIV_A::FDIV_11
582 }
583 #[doc = "Checks if the value of the field is `FDIV_12`"]
584 #[inline(always)]
585 pub fn is_fdiv_12(&self) -> bool {
586 **self == FDIV_A::FDIV_12
587 }
588 #[doc = "Checks if the value of the field is `FDIV_13`"]
589 #[inline(always)]
590 pub fn is_fdiv_13(&self) -> bool {
591 **self == FDIV_A::FDIV_13
592 }
593 #[doc = "Checks if the value of the field is `FDIV_14`"]
594 #[inline(always)]
595 pub fn is_fdiv_14(&self) -> bool {
596 **self == FDIV_A::FDIV_14
597 }
598 #[doc = "Checks if the value of the field is `FDIV_15`"]
599 #[inline(always)]
600 pub fn is_fdiv_15(&self) -> bool {
601 **self == FDIV_A::FDIV_15
602 }
603}
604impl core::ops::Deref for FDIV_R {
605 type Target = crate::FieldReader<u8, FDIV_A>;
606 #[inline(always)]
607 fn deref(&self) -> &Self::Target {
608 &self.0
609 }
610}
611#[doc = "Field `FDIV` writer - Functional clock divider, or 0 if no divide. The term \"clocks\" in this spec then refer to divided clocks. For a 12MHz input (e.g. FRO 12MHz), this would normally be set to generate a 4MHz output (so, 2). For a 1MHz input, it should be 0. Note for internal use: this does not produce a 50/50 duty cycle when non even divide."]
612pub struct FDIV_W<'a> {
613 w: &'a mut W,
614}
615impl<'a> FDIV_W<'a> {
616 #[doc = r"Writes `variant` to the field"]
617 #[inline(always)]
618 pub fn variant(self, variant: FDIV_A) -> &'a mut W {
619 unsafe { self.bits(variant.into()) }
620 }
621 #[doc = "No divide"]
622 #[inline(always)]
623 pub fn fdiv_0(self) -> &'a mut W {
624 self.variant(FDIV_A::FDIV_0)
625 }
626 #[doc = "/2"]
627 #[inline(always)]
628 pub fn fdiv_1(self) -> &'a mut W {
629 self.variant(FDIV_A::FDIV_1)
630 }
631 #[doc = "/3"]
632 #[inline(always)]
633 pub fn fdiv_2(self) -> &'a mut W {
634 self.variant(FDIV_A::FDIV_2)
635 }
636 #[doc = "/4"]
637 #[inline(always)]
638 pub fn fdiv_3(self) -> &'a mut W {
639 self.variant(FDIV_A::FDIV_3)
640 }
641 #[doc = "/5"]
642 #[inline(always)]
643 pub fn fdiv_4(self) -> &'a mut W {
644 self.variant(FDIV_A::FDIV_4)
645 }
646 #[doc = "/6"]
647 #[inline(always)]
648 pub fn fdiv_5(self) -> &'a mut W {
649 self.variant(FDIV_A::FDIV_5)
650 }
651 #[doc = "/(FDIV+1)"]
652 #[inline(always)]
653 pub fn fdiv_7(self) -> &'a mut W {
654 self.variant(FDIV_A::FDIV_7)
655 }
656 #[doc = "/(FDIV+1)"]
657 #[inline(always)]
658 pub fn fdiv_8(self) -> &'a mut W {
659 self.variant(FDIV_A::FDIV_8)
660 }
661 #[doc = "/(FDIV+1)"]
662 #[inline(always)]
663 pub fn fdiv_9(self) -> &'a mut W {
664 self.variant(FDIV_A::FDIV_9)
665 }
666 #[doc = "/(FDIV+1)"]
667 #[inline(always)]
668 pub fn fdiv_10(self) -> &'a mut W {
669 self.variant(FDIV_A::FDIV_10)
670 }
671 #[doc = "/(FDIV+1)"]
672 #[inline(always)]
673 pub fn fdiv_11(self) -> &'a mut W {
674 self.variant(FDIV_A::FDIV_11)
675 }
676 #[doc = "/(FDIV+1)"]
677 #[inline(always)]
678 pub fn fdiv_12(self) -> &'a mut W {
679 self.variant(FDIV_A::FDIV_12)
680 }
681 #[doc = "/(FDIV+1)"]
682 #[inline(always)]
683 pub fn fdiv_13(self) -> &'a mut W {
684 self.variant(FDIV_A::FDIV_13)
685 }
686 #[doc = "/(FDIV+1)"]
687 #[inline(always)]
688 pub fn fdiv_14(self) -> &'a mut W {
689 self.variant(FDIV_A::FDIV_14)
690 }
691 #[doc = "/(FDIV+1)"]
692 #[inline(always)]
693 pub fn fdiv_15(self) -> &'a mut W {
694 self.variant(FDIV_A::FDIV_15)
695 }
696 #[doc = r"Writes raw bits to the field"]
697 #[inline(always)]
698 pub unsafe fn bits(self, value: u8) -> &'a mut W {
699 self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8);
700 self.w
701 }
702}
703#[doc = "Controls how X pins selected in XPINSEL are used when not active in the current polling round.\n\nValue on reset: 0"]
704#[derive(Clone, Copy, Debug, PartialEq)]
705#[repr(u8)]
706pub enum XPINUSE_A {
707 #[doc = "0: Normal mode. Each inactive X pin is Hi-Z."]
708 NORMAL_MDOE = 0,
709 #[doc = "1: Ground mode. Each inactive X pin is Low"]
710 GROUND_MDOE = 1,
711}
712impl From<XPINUSE_A> for u8 {
713 #[inline(always)]
714 fn from(variant: XPINUSE_A) -> Self {
715 variant as _
716 }
717}
718#[doc = "Field `XPINUSE` reader - Controls how X pins selected in XPINSEL are used when not active in the current polling round."]
719pub struct XPINUSE_R(crate::FieldReader<u8, XPINUSE_A>);
720impl XPINUSE_R {
721 pub(crate) fn new(bits: u8) -> Self {
722 XPINUSE_R(crate::FieldReader::new(bits))
723 }
724 #[doc = r"Get enumerated values variant"]
725 #[inline(always)]
726 pub fn variant(&self) -> Option<XPINUSE_A> {
727 match self.bits {
728 0 => Some(XPINUSE_A::NORMAL_MDOE),
729 1 => Some(XPINUSE_A::GROUND_MDOE),
730 _ => None,
731 }
732 }
733 #[doc = "Checks if the value of the field is `NORMAL_MDOE`"]
734 #[inline(always)]
735 pub fn is_normal_mdoe(&self) -> bool {
736 **self == XPINUSE_A::NORMAL_MDOE
737 }
738 #[doc = "Checks if the value of the field is `GROUND_MDOE`"]
739 #[inline(always)]
740 pub fn is_ground_mdoe(&self) -> bool {
741 **self == XPINUSE_A::GROUND_MDOE
742 }
743}
744impl core::ops::Deref for XPINUSE_R {
745 type Target = crate::FieldReader<u8, XPINUSE_A>;
746 #[inline(always)]
747 fn deref(&self) -> &Self::Target {
748 &self.0
749 }
750}
751#[doc = "Field `XPINUSE` writer - Controls how X pins selected in XPINSEL are used when not active in the current polling round."]
752pub struct XPINUSE_W<'a> {
753 w: &'a mut W,
754}
755impl<'a> XPINUSE_W<'a> {
756 #[doc = r"Writes `variant` to the field"]
757 #[inline(always)]
758 pub fn variant(self, variant: XPINUSE_A) -> &'a mut W {
759 unsafe { self.bits(variant.into()) }
760 }
761 #[doc = "Normal mode. Each inactive X pin is Hi-Z."]
762 #[inline(always)]
763 pub fn normal_mdoe(self) -> &'a mut W {
764 self.variant(XPINUSE_A::NORMAL_MDOE)
765 }
766 #[doc = "Ground mode. Each inactive X pin is Low"]
767 #[inline(always)]
768 pub fn ground_mdoe(self) -> &'a mut W {
769 self.variant(XPINUSE_A::GROUND_MDOE)
770 }
771 #[doc = r"Writes raw bits to the field"]
772 #[inline(always)]
773 pub unsafe fn bits(self, value: u8) -> &'a mut W {
774 self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u32 & 0x03) << 12);
775 self.w
776 }
777}
778#[doc = "Field `INCHANGE` reader - If 1, do not attempt to write to this register again. This means the last change has not been propagated. This can only happen after changing POLLMODE and DMA. Worse case time would be based on divided FCLK."]
779pub struct INCHANGE_R(crate::FieldReader<bool, bool>);
780impl INCHANGE_R {
781 pub(crate) fn new(bits: bool) -> Self {
782 INCHANGE_R(crate::FieldReader::new(bits))
783 }
784}
785impl core::ops::Deref for INCHANGE_R {
786 type Target = crate::FieldReader<bool, bool>;
787 #[inline(always)]
788 fn deref(&self) -> &Self::Target {
789 &self.0
790 }
791}
792#[doc = "Field `XPINSEL` reader - Selects which of the X pins are to be used within the allowed pins - see XMAX in STATUS. The X pins are mapped via the IOCON (as are the YH and YL pins) to physical pads. So, this only selects which are to be used as the X half of the touch element. Note: when polling, these are \"walked\" (active) one at a time. When using POLLNOW, the 1 or more selected are used at the same time. Likewise, when in low-power mode, they are used at the same time (or small groups). X pads not selected by XPINSEL are kept at High-Z if they are connected to a pad. This allows using controlled sets for touch detection based on context."]
793pub struct XPINSEL_R(crate::FieldReader<u16, u16>);
794impl XPINSEL_R {
795 pub(crate) fn new(bits: u16) -> Self {
796 XPINSEL_R(crate::FieldReader::new(bits))
797 }
798}
799impl core::ops::Deref for XPINSEL_R {
800 type Target = crate::FieldReader<u16, u16>;
801 #[inline(always)]
802 fn deref(&self) -> &Self::Target {
803 &self.0
804 }
805}
806#[doc = "Field `XPINSEL` writer - Selects which of the X pins are to be used within the allowed pins - see XMAX in STATUS. The X pins are mapped via the IOCON (as are the YH and YL pins) to physical pads. So, this only selects which are to be used as the X half of the touch element. Note: when polling, these are \"walked\" (active) one at a time. When using POLLNOW, the 1 or more selected are used at the same time. Likewise, when in low-power mode, they are used at the same time (or small groups). X pads not selected by XPINSEL are kept at High-Z if they are connected to a pad. This allows using controlled sets for touch detection based on context."]
807pub struct XPINSEL_W<'a> {
808 w: &'a mut W,
809}
810impl<'a> XPINSEL_W<'a> {
811 #[doc = r"Writes raw bits to the field"]
812 #[inline(always)]
813 pub unsafe fn bits(self, value: u16) -> &'a mut W {
814 self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16);
815 self.w
816 }
817}
818impl R {
819 #[doc = "Bits 0:1 - Mode of operation. May only change from 0 to another value. So, if 2 or 3, must be changed to 0 1st. Any attempt to go from non-0 to non-0 will result in 0 anyway."]
820 #[inline(always)]
821 pub fn pollmode(&self) -> POLLMODE_R {
822 POLLMODE_R::new((self.bits & 0x03) as u8)
823 }
824 #[doc = "Bits 2:3 - Selects type of Touch arrangement to use and so how to handle XPINSEL bits"]
825 #[inline(always)]
826 pub fn type_(&self) -> TYPE_R {
827 TYPE_R::new(((self.bits >> 2) & 0x03) as u8)
828 }
829 #[doc = "Bit 4 - This selects what is being used as the trigger"]
830 #[inline(always)]
831 pub fn trigger(&self) -> TRIGGER_R {
832 TRIGGER_R::new(((self.bits >> 4) & 0x01) != 0)
833 }
834 #[doc = "Bit 5 - If 0, the block will continue its X based measurements, even if the TOUCH register has not been read (and so could OVERRUN). If 1, it will wait until read when a touch (TOUCH's ISTOUCH bit is set) before starting the next. This should not normally be needed."]
835 #[inline(always)]
836 pub fn wait(&self) -> WAIT_R {
837 WAIT_R::new(((self.bits >> 5) & 0x01) != 0)
838 }
839 #[doc = "Bits 6:7 - If not 0, will use the DMA to read out touch events from TOUCH register. The values are shown below. This may be changed while active."]
840 #[inline(always)]
841 pub fn dma(&self) -> DMA_R {
842 DMA_R::new(((self.bits >> 6) & 0x03) as u8)
843 }
844 #[doc = "Bits 8:11 - Functional clock divider, or 0 if no divide. The term \"clocks\" in this spec then refer to divided clocks. For a 12MHz input (e.g. FRO 12MHz), this would normally be set to generate a 4MHz output (so, 2). For a 1MHz input, it should be 0. Note for internal use: this does not produce a 50/50 duty cycle when non even divide."]
845 #[inline(always)]
846 pub fn fdiv(&self) -> FDIV_R {
847 FDIV_R::new(((self.bits >> 8) & 0x0f) as u8)
848 }
849 #[doc = "Bits 12:13 - Controls how X pins selected in XPINSEL are used when not active in the current polling round."]
850 #[inline(always)]
851 pub fn xpinuse(&self) -> XPINUSE_R {
852 XPINUSE_R::new(((self.bits >> 12) & 0x03) as u8)
853 }
854 #[doc = "Bit 15 - If 1, do not attempt to write to this register again. This means the last change has not been propagated. This can only happen after changing POLLMODE and DMA. Worse case time would be based on divided FCLK."]
855 #[inline(always)]
856 pub fn inchange(&self) -> INCHANGE_R {
857 INCHANGE_R::new(((self.bits >> 15) & 0x01) != 0)
858 }
859 #[doc = "Bits 16:31 - Selects which of the X pins are to be used within the allowed pins - see XMAX in STATUS. The X pins are mapped via the IOCON (as are the YH and YL pins) to physical pads. So, this only selects which are to be used as the X half of the touch element. Note: when polling, these are \"walked\" (active) one at a time. When using POLLNOW, the 1 or more selected are used at the same time. Likewise, when in low-power mode, they are used at the same time (or small groups). X pads not selected by XPINSEL are kept at High-Z if they are connected to a pad. This allows using controlled sets for touch detection based on context."]
860 #[inline(always)]
861 pub fn xpinsel(&self) -> XPINSEL_R {
862 XPINSEL_R::new(((self.bits >> 16) & 0xffff) as u16)
863 }
864}
865impl W {
866 #[doc = "Bits 0:1 - Mode of operation. May only change from 0 to another value. So, if 2 or 3, must be changed to 0 1st. Any attempt to go from non-0 to non-0 will result in 0 anyway."]
867 #[inline(always)]
868 pub fn pollmode(&mut self) -> POLLMODE_W {
869 POLLMODE_W { w: self }
870 }
871 #[doc = "Bits 2:3 - Selects type of Touch arrangement to use and so how to handle XPINSEL bits"]
872 #[inline(always)]
873 pub fn type_(&mut self) -> TYPE_W {
874 TYPE_W { w: self }
875 }
876 #[doc = "Bit 4 - This selects what is being used as the trigger"]
877 #[inline(always)]
878 pub fn trigger(&mut self) -> TRIGGER_W {
879 TRIGGER_W { w: self }
880 }
881 #[doc = "Bit 5 - If 0, the block will continue its X based measurements, even if the TOUCH register has not been read (and so could OVERRUN). If 1, it will wait until read when a touch (TOUCH's ISTOUCH bit is set) before starting the next. This should not normally be needed."]
882 #[inline(always)]
883 pub fn wait(&mut self) -> WAIT_W {
884 WAIT_W { w: self }
885 }
886 #[doc = "Bits 6:7 - If not 0, will use the DMA to read out touch events from TOUCH register. The values are shown below. This may be changed while active."]
887 #[inline(always)]
888 pub fn dma(&mut self) -> DMA_W {
889 DMA_W { w: self }
890 }
891 #[doc = "Bits 8:11 - Functional clock divider, or 0 if no divide. The term \"clocks\" in this spec then refer to divided clocks. For a 12MHz input (e.g. FRO 12MHz), this would normally be set to generate a 4MHz output (so, 2). For a 1MHz input, it should be 0. Note for internal use: this does not produce a 50/50 duty cycle when non even divide."]
892 #[inline(always)]
893 pub fn fdiv(&mut self) -> FDIV_W {
894 FDIV_W { w: self }
895 }
896 #[doc = "Bits 12:13 - Controls how X pins selected in XPINSEL are used when not active in the current polling round."]
897 #[inline(always)]
898 pub fn xpinuse(&mut self) -> XPINUSE_W {
899 XPINUSE_W { w: self }
900 }
901 #[doc = "Bits 16:31 - Selects which of the X pins are to be used within the allowed pins - see XMAX in STATUS. The X pins are mapped via the IOCON (as are the YH and YL pins) to physical pads. So, this only selects which are to be used as the X half of the touch element. Note: when polling, these are \"walked\" (active) one at a time. When using POLLNOW, the 1 or more selected are used at the same time. Likewise, when in low-power mode, they are used at the same time (or small groups). X pads not selected by XPINSEL are kept at High-Z if they are connected to a pad. This allows using controlled sets for touch detection based on context."]
902 #[inline(always)]
903 pub fn xpinsel(&mut self) -> XPINSEL_W {
904 XPINSEL_W { w: self }
905 }
906 #[doc = "Writes raw bits to the register."]
907 #[inline(always)]
908 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
909 self.0.bits(bits);
910 self
911 }
912}
913#[doc = "Configuration and control to setup the functional clock, the rules, and the pin selections and rules.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
914pub struct CTRL_SPEC;
915impl crate::RegisterSpec for CTRL_SPEC {
916 type Ux = u32;
917}
918#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
919impl crate::Readable for CTRL_SPEC {
920 type Reader = R;
921}
922#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
923impl crate::Writable for CTRL_SPEC {
924 type Writer = W;
925}
926#[doc = "`reset()` method sets CTRL to value 0"]
927impl crate::Resettable for CTRL_SPEC {
928 #[inline(always)]
929 fn reset_value() -> Self::Ux {
930 0
931 }
932}