1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - System Remap register"]
5 pub sysmemremap: crate::Reg<sysmemremap::SYSMEMREMAP_SPEC>,
6 _reserved1: [u8; 0x04],
7 #[doc = "0x08 - PLL control"]
8 pub syspllctrl: crate::Reg<syspllctrl::SYSPLLCTRL_SPEC>,
9 #[doc = "0x0c - PLL status"]
10 pub syspllstat: crate::Reg<syspllstat::SYSPLLSTAT_SPEC>,
11 _reserved3: [u8; 0x10],
12 #[doc = "0x20 - system oscillator control"]
13 pub sysoscctrl: crate::Reg<sysoscctrl::SYSOSCCTRL_SPEC>,
14 #[doc = "0x24 - Watchdog oscillator control"]
15 pub wdtoscctrl: crate::Reg<wdtoscctrl::WDTOSCCTRL_SPEC>,
16 #[doc = "0x28 - FRO oscillator control"]
17 pub frooscctrl: crate::Reg<frooscctrl::FROOSCCTRL_SPEC>,
18 _reserved6: [u8; 0x04],
19 #[doc = "0x30 - FRO direct clock source update enable register"]
20 pub frodirectclkuen: crate::Reg<frodirectclkuen::FRODIRECTCLKUEN_SPEC>,
21 _reserved7: [u8; 0x04],
22 #[doc = "0x38 - System reset status register"]
23 pub sysrststat: crate::Reg<sysrststat::SYSRSTSTAT_SPEC>,
24 _reserved8: [u8; 0x04],
25 #[doc = "0x40 - System PLL clock source select register"]
26 pub syspllclksel: crate::Reg<syspllclksel::SYSPLLCLKSEL_SPEC>,
27 #[doc = "0x44 - System PLL clock source update enable register"]
28 pub syspllclkuen: crate::Reg<syspllclkuen::SYSPLLCLKUEN_SPEC>,
29 #[doc = "0x48 - Main clock source select register"]
30 pub mainclkpllsel: crate::Reg<mainclkpllsel::MAINCLKPLLSEL_SPEC>,
31 #[doc = "0x4c - Main clock source update enable register"]
32 pub mainclkplluen: crate::Reg<mainclkplluen::MAINCLKPLLUEN_SPEC>,
33 #[doc = "0x50 - Main clock source select register"]
34 pub mainclksel: crate::Reg<mainclksel::MAINCLKSEL_SPEC>,
35 #[doc = "0x54 - Main clock source update enable register"]
36 pub mainclkuen: crate::Reg<mainclkuen::MAINCLKUEN_SPEC>,
37 #[doc = "0x58 - System clock divider register"]
38 pub sysahbclkdiv: crate::Reg<sysahbclkdiv::SYSAHBCLKDIV_SPEC>,
39 _reserved15: [u8; 0x04],
40 #[doc = "0x60 - CAPT clock source select register"]
41 pub captclksel: crate::Reg<captclksel::CAPTCLKSEL_SPEC>,
42 #[doc = "0x64 - ADC clock source select register"]
43 pub adcclksel: crate::Reg<adcclksel::ADCCLKSEL_SPEC>,
44 #[doc = "0x68 - ADC clock divider register"]
45 pub adcclkdiv: crate::Reg<adcclkdiv::ADCCLKDIV_SPEC>,
46 #[doc = "0x6c - SCT clock source select register"]
47 pub sctclksel: crate::Reg<sctclksel::SCTCLKSEL_SPEC>,
48 #[doc = "0x70 - SCT clock divider register"]
49 pub sctclkdiv: crate::Reg<sctclkdiv::SCTCLKDIV_SPEC>,
50 #[doc = "0x74 - external clock source select register"]
51 pub extclksel: crate::Reg<extclksel::EXTCLKSEL_SPEC>,
52 _reserved21: [u8; 0x08],
53 #[doc = "0x80 - System clock group 0 control register"]
54 pub sysahbclkctrl0: crate::Reg<sysahbclkctrl0::SYSAHBCLKCTRL0_SPEC>,
55 #[doc = "0x84 - System clock group 1 control register"]
56 pub sysahbclkctrl1: crate::Reg<sysahbclkctrl1::SYSAHBCLKCTRL1_SPEC>,
57 #[doc = "0x88 - Peripheral reset group 0 control register"]
58 pub presetctrl0: crate::Reg<presetctrl0::PRESETCTRL0_SPEC>,
59 #[doc = "0x8c - Peripheral reset group 1 control register"]
60 pub presetctrl1: crate::Reg<presetctrl1::PRESETCTRL1_SPEC>,
61 #[doc = "0x90..0xbc - peripheral clock source select register. FCLK0SEL~FCLK4SEL are for UART0~UART4 clock source select register. FCLK5SEL~FCLK8SEL are for I2C0~I2C3 clock source select register. FCLK9SEL~FCLK10SEL are for SPI0~SPI1 clock source select register."]
62 pub fclksel: [crate::Reg<fclksel::FCLKSEL_SPEC>; 11],
63 _reserved26: [u8; 0x14],
64 #[doc = "0xd0..0xdc - no description available"]
65 pub frg0: FRG,
66 _reserved27: [u8; 0x04],
67 #[doc = "0xe0..0xec - no description available"]
68 pub frg1: FRG,
69 _reserved28: [u8; 0x04],
70 #[doc = "0xf0 - CLKOUT clock source select register"]
71 pub clkoutsel: crate::Reg<clkoutsel::CLKOUTSEL_SPEC>,
72 #[doc = "0xf4 - CLKOUT clock divider registers"]
73 pub clkoutdiv: crate::Reg<clkoutdiv::CLKOUTDIV_SPEC>,
74 _reserved30: [u8; 0x04],
75 #[doc = "0xfc - External trace buffer command register"]
76 pub exttracecmd: crate::Reg<exttracecmd::EXTTRACECMD_SPEC>,
77 #[doc = "0x100..0x108 - POR captured PIO N status register(PIO0 has 32 PIOs, PIO1 has 22 PIOs)"]
78 pub pioporcap: [crate::Reg<pioporcap::PIOPORCAP_SPEC>; 2],
79 _reserved32: [u8; 0x2c],
80 #[doc = "0x134 - Peripheral clock 6 to the IOCON block for programmable glitch filter"]
81 pub ioconclkdiv6: crate::Reg<ioconclkdiv6::IOCONCLKDIV6_SPEC>,
82 #[doc = "0x138 - Peripheral clock 6 to the IOCON block for programmable glitch filter"]
83 pub ioconclkdiv5: crate::Reg<ioconclkdiv5::IOCONCLKDIV5_SPEC>,
84 #[doc = "0x13c - Peripheral clock 4 to the IOCON block for programmable glitch filter"]
85 pub ioconclkdiv4: crate::Reg<ioconclkdiv4::IOCONCLKDIV4_SPEC>,
86 #[doc = "0x140 - Peripheral clock 3 to the IOCON block for programmable glitch filter"]
87 pub ioconclkdiv3: crate::Reg<ioconclkdiv3::IOCONCLKDIV3_SPEC>,
88 #[doc = "0x144 - Peripheral clock 2 to the IOCON block for programmable glitch filter"]
89 pub ioconclkdiv2: crate::Reg<ioconclkdiv2::IOCONCLKDIV2_SPEC>,
90 #[doc = "0x148 - Peripheral clock 1 to the IOCON block for programmable glitch filter"]
91 pub ioconclkdiv1: crate::Reg<ioconclkdiv1::IOCONCLKDIV1_SPEC>,
92 #[doc = "0x14c - Peripheral clock 0 to the IOCON block for programmable glitch filter"]
93 pub ioconclkdiv0: crate::Reg<ioconclkdiv0::IOCONCLKDIV0_SPEC>,
94 #[doc = "0x150 - BOD control register"]
95 pub bodctrl: crate::Reg<bodctrl::BODCTRL_SPEC>,
96 #[doc = "0x154 - System tick timer calibration register"]
97 pub systckcal: crate::Reg<systckcal::SYSTCKCAL_SPEC>,
98 _reserved41: [u8; 0x18],
99 #[doc = "0x170 - IRQ latency register"]
100 pub irqlatency: crate::Reg<irqlatency::IRQLATENCY_SPEC>,
101 #[doc = "0x174 - NMI source selection register"]
102 pub nmisrc: crate::Reg<nmisrc::NMISRC_SPEC>,
103 #[doc = "0x178..0x198 - Pin interrupt select registers N"]
104 pub pintsel: [crate::Reg<pintsel::PINTSEL_SPEC>; 8],
105 _reserved44: [u8; 0x6c],
106 #[doc = "0x204 - Start logic 0 pin wake-up enable register 0"]
107 pub starterp0: crate::Reg<starterp0::STARTERP0_SPEC>,
108 _reserved45: [u8; 0x0c],
109 #[doc = "0x214 - Start logic 0 pin wake-up enable register 1"]
110 pub starterp1: crate::Reg<starterp1::STARTERP1_SPEC>,
111 _reserved46: [u8; 0x18],
112 #[doc = "0x230 - Deep-sleep configuration register"]
113 pub pdsleepcfg: crate::Reg<pdsleepcfg::PDSLEEPCFG_SPEC>,
114 #[doc = "0x234 - Wake-up configuration register"]
115 pub pdawakecfg: crate::Reg<pdawakecfg::PDAWAKECFG_SPEC>,
116 #[doc = "0x238 - Power configuration register"]
117 pub pdruncfg: crate::Reg<pdruncfg::PDRUNCFG_SPEC>,
118 _reserved49: [u8; 0x01bc],
119 #[doc = "0x3f8 - Part ID register"]
120 pub device_id: crate::Reg<device_id::DEVICE_ID_SPEC>,
121}
122#[doc = r"Register block"]
123#[repr(C)]
124pub struct FRG {
125 #[doc = "0x00 - fractional generator N divider value register"]
126 pub frgdiv: crate::Reg<self::frg::frgdiv::FRGDIV_SPEC>,
127 #[doc = "0x04 - fractional generator N multiplier value register"]
128 pub frgmult: crate::Reg<self::frg::frgmult::FRGMULT_SPEC>,
129 #[doc = "0x08 - FRG N clock source select register"]
130 pub frgclksel: crate::Reg<self::frg::frgclksel::FRGCLKSEL_SPEC>,
131}
132#[doc = r"Register block"]
133#[doc = "no description available"]
134pub mod frg;
135#[doc = "SYSMEMREMAP register accessor: an alias for `Reg<SYSMEMREMAP_SPEC>`"]
136pub type SYSMEMREMAP = crate::Reg<sysmemremap::SYSMEMREMAP_SPEC>;
137#[doc = "System Remap register"]
138pub mod sysmemremap;
139#[doc = "SYSPLLCTRL register accessor: an alias for `Reg<SYSPLLCTRL_SPEC>`"]
140pub type SYSPLLCTRL = crate::Reg<syspllctrl::SYSPLLCTRL_SPEC>;
141#[doc = "PLL control"]
142pub mod syspllctrl;
143#[doc = "SYSPLLSTAT register accessor: an alias for `Reg<SYSPLLSTAT_SPEC>`"]
144pub type SYSPLLSTAT = crate::Reg<syspllstat::SYSPLLSTAT_SPEC>;
145#[doc = "PLL status"]
146pub mod syspllstat;
147#[doc = "SYSOSCCTRL register accessor: an alias for `Reg<SYSOSCCTRL_SPEC>`"]
148pub type SYSOSCCTRL = crate::Reg<sysoscctrl::SYSOSCCTRL_SPEC>;
149#[doc = "system oscillator control"]
150pub mod sysoscctrl;
151#[doc = "WDTOSCCTRL register accessor: an alias for `Reg<WDTOSCCTRL_SPEC>`"]
152pub type WDTOSCCTRL = crate::Reg<wdtoscctrl::WDTOSCCTRL_SPEC>;
153#[doc = "Watchdog oscillator control"]
154pub mod wdtoscctrl;
155#[doc = "FROOSCCTRL register accessor: an alias for `Reg<FROOSCCTRL_SPEC>`"]
156pub type FROOSCCTRL = crate::Reg<frooscctrl::FROOSCCTRL_SPEC>;
157#[doc = "FRO oscillator control"]
158pub mod frooscctrl;
159#[doc = "FRODIRECTCLKUEN register accessor: an alias for `Reg<FRODIRECTCLKUEN_SPEC>`"]
160pub type FRODIRECTCLKUEN = crate::Reg<frodirectclkuen::FRODIRECTCLKUEN_SPEC>;
161#[doc = "FRO direct clock source update enable register"]
162pub mod frodirectclkuen;
163#[doc = "SYSRSTSTAT register accessor: an alias for `Reg<SYSRSTSTAT_SPEC>`"]
164pub type SYSRSTSTAT = crate::Reg<sysrststat::SYSRSTSTAT_SPEC>;
165#[doc = "System reset status register"]
166pub mod sysrststat;
167#[doc = "SYSPLLCLKSEL register accessor: an alias for `Reg<SYSPLLCLKSEL_SPEC>`"]
168pub type SYSPLLCLKSEL = crate::Reg<syspllclksel::SYSPLLCLKSEL_SPEC>;
169#[doc = "System PLL clock source select register"]
170pub mod syspllclksel;
171#[doc = "SYSPLLCLKUEN register accessor: an alias for `Reg<SYSPLLCLKUEN_SPEC>`"]
172pub type SYSPLLCLKUEN = crate::Reg<syspllclkuen::SYSPLLCLKUEN_SPEC>;
173#[doc = "System PLL clock source update enable register"]
174pub mod syspllclkuen;
175#[doc = "MAINCLKPLLSEL register accessor: an alias for `Reg<MAINCLKPLLSEL_SPEC>`"]
176pub type MAINCLKPLLSEL = crate::Reg<mainclkpllsel::MAINCLKPLLSEL_SPEC>;
177#[doc = "Main clock source select register"]
178pub mod mainclkpllsel;
179#[doc = "MAINCLKPLLUEN register accessor: an alias for `Reg<MAINCLKPLLUEN_SPEC>`"]
180pub type MAINCLKPLLUEN = crate::Reg<mainclkplluen::MAINCLKPLLUEN_SPEC>;
181#[doc = "Main clock source update enable register"]
182pub mod mainclkplluen;
183#[doc = "MAINCLKSEL register accessor: an alias for `Reg<MAINCLKSEL_SPEC>`"]
184pub type MAINCLKSEL = crate::Reg<mainclksel::MAINCLKSEL_SPEC>;
185#[doc = "Main clock source select register"]
186pub mod mainclksel;
187#[doc = "MAINCLKUEN register accessor: an alias for `Reg<MAINCLKUEN_SPEC>`"]
188pub type MAINCLKUEN = crate::Reg<mainclkuen::MAINCLKUEN_SPEC>;
189#[doc = "Main clock source update enable register"]
190pub mod mainclkuen;
191#[doc = "SYSAHBCLKDIV register accessor: an alias for `Reg<SYSAHBCLKDIV_SPEC>`"]
192pub type SYSAHBCLKDIV = crate::Reg<sysahbclkdiv::SYSAHBCLKDIV_SPEC>;
193#[doc = "System clock divider register"]
194pub mod sysahbclkdiv;
195#[doc = "CAPTCLKSEL register accessor: an alias for `Reg<CAPTCLKSEL_SPEC>`"]
196pub type CAPTCLKSEL = crate::Reg<captclksel::CAPTCLKSEL_SPEC>;
197#[doc = "CAPT clock source select register"]
198pub mod captclksel;
199#[doc = "ADCCLKSEL register accessor: an alias for `Reg<ADCCLKSEL_SPEC>`"]
200pub type ADCCLKSEL = crate::Reg<adcclksel::ADCCLKSEL_SPEC>;
201#[doc = "ADC clock source select register"]
202pub mod adcclksel;
203#[doc = "ADCCLKDIV register accessor: an alias for `Reg<ADCCLKDIV_SPEC>`"]
204pub type ADCCLKDIV = crate::Reg<adcclkdiv::ADCCLKDIV_SPEC>;
205#[doc = "ADC clock divider register"]
206pub mod adcclkdiv;
207#[doc = "SCTCLKSEL register accessor: an alias for `Reg<SCTCLKSEL_SPEC>`"]
208pub type SCTCLKSEL = crate::Reg<sctclksel::SCTCLKSEL_SPEC>;
209#[doc = "SCT clock source select register"]
210pub mod sctclksel;
211#[doc = "SCTCLKDIV register accessor: an alias for `Reg<SCTCLKDIV_SPEC>`"]
212pub type SCTCLKDIV = crate::Reg<sctclkdiv::SCTCLKDIV_SPEC>;
213#[doc = "SCT clock divider register"]
214pub mod sctclkdiv;
215#[doc = "EXTCLKSEL register accessor: an alias for `Reg<EXTCLKSEL_SPEC>`"]
216pub type EXTCLKSEL = crate::Reg<extclksel::EXTCLKSEL_SPEC>;
217#[doc = "external clock source select register"]
218pub mod extclksel;
219#[doc = "SYSAHBCLKCTRL0 register accessor: an alias for `Reg<SYSAHBCLKCTRL0_SPEC>`"]
220pub type SYSAHBCLKCTRL0 = crate::Reg<sysahbclkctrl0::SYSAHBCLKCTRL0_SPEC>;
221#[doc = "System clock group 0 control register"]
222pub mod sysahbclkctrl0;
223#[doc = "SYSAHBCLKCTRL1 register accessor: an alias for `Reg<SYSAHBCLKCTRL1_SPEC>`"]
224pub type SYSAHBCLKCTRL1 = crate::Reg<sysahbclkctrl1::SYSAHBCLKCTRL1_SPEC>;
225#[doc = "System clock group 1 control register"]
226pub mod sysahbclkctrl1;
227#[doc = "PRESETCTRL0 register accessor: an alias for `Reg<PRESETCTRL0_SPEC>`"]
228pub type PRESETCTRL0 = crate::Reg<presetctrl0::PRESETCTRL0_SPEC>;
229#[doc = "Peripheral reset group 0 control register"]
230pub mod presetctrl0;
231#[doc = "PRESETCTRL1 register accessor: an alias for `Reg<PRESETCTRL1_SPEC>`"]
232pub type PRESETCTRL1 = crate::Reg<presetctrl1::PRESETCTRL1_SPEC>;
233#[doc = "Peripheral reset group 1 control register"]
234pub mod presetctrl1;
235#[doc = "FCLKSEL register accessor: an alias for `Reg<FCLKSEL_SPEC>`"]
236pub type FCLKSEL = crate::Reg<fclksel::FCLKSEL_SPEC>;
237#[doc = "peripheral clock source select register. FCLK0SEL~FCLK4SEL are for UART0~UART4 clock source select register. FCLK5SEL~FCLK8SEL are for I2C0~I2C3 clock source select register. FCLK9SEL~FCLK10SEL are for SPI0~SPI1 clock source select register."]
238pub mod fclksel;
239#[doc = "CLKOUTSEL register accessor: an alias for `Reg<CLKOUTSEL_SPEC>`"]
240pub type CLKOUTSEL = crate::Reg<clkoutsel::CLKOUTSEL_SPEC>;
241#[doc = "CLKOUT clock source select register"]
242pub mod clkoutsel;
243#[doc = "CLKOUTDIV register accessor: an alias for `Reg<CLKOUTDIV_SPEC>`"]
244pub type CLKOUTDIV = crate::Reg<clkoutdiv::CLKOUTDIV_SPEC>;
245#[doc = "CLKOUT clock divider registers"]
246pub mod clkoutdiv;
247#[doc = "EXTTRACECMD register accessor: an alias for `Reg<EXTTRACECMD_SPEC>`"]
248pub type EXTTRACECMD = crate::Reg<exttracecmd::EXTTRACECMD_SPEC>;
249#[doc = "External trace buffer command register"]
250pub mod exttracecmd;
251#[doc = "PIOPORCAP register accessor: an alias for `Reg<PIOPORCAP_SPEC>`"]
252pub type PIOPORCAP = crate::Reg<pioporcap::PIOPORCAP_SPEC>;
253#[doc = "POR captured PIO N status register(PIO0 has 32 PIOs, PIO1 has 22 PIOs)"]
254pub mod pioporcap;
255#[doc = "IOCONCLKDIV6 register accessor: an alias for `Reg<IOCONCLKDIV6_SPEC>`"]
256pub type IOCONCLKDIV6 = crate::Reg<ioconclkdiv6::IOCONCLKDIV6_SPEC>;
257#[doc = "Peripheral clock 6 to the IOCON block for programmable glitch filter"]
258pub mod ioconclkdiv6;
259#[doc = "IOCONCLKDIV5 register accessor: an alias for `Reg<IOCONCLKDIV5_SPEC>`"]
260pub type IOCONCLKDIV5 = crate::Reg<ioconclkdiv5::IOCONCLKDIV5_SPEC>;
261#[doc = "Peripheral clock 6 to the IOCON block for programmable glitch filter"]
262pub mod ioconclkdiv5;
263#[doc = "IOCONCLKDIV4 register accessor: an alias for `Reg<IOCONCLKDIV4_SPEC>`"]
264pub type IOCONCLKDIV4 = crate::Reg<ioconclkdiv4::IOCONCLKDIV4_SPEC>;
265#[doc = "Peripheral clock 4 to the IOCON block for programmable glitch filter"]
266pub mod ioconclkdiv4;
267#[doc = "IOCONCLKDIV3 register accessor: an alias for `Reg<IOCONCLKDIV3_SPEC>`"]
268pub type IOCONCLKDIV3 = crate::Reg<ioconclkdiv3::IOCONCLKDIV3_SPEC>;
269#[doc = "Peripheral clock 3 to the IOCON block for programmable glitch filter"]
270pub mod ioconclkdiv3;
271#[doc = "IOCONCLKDIV2 register accessor: an alias for `Reg<IOCONCLKDIV2_SPEC>`"]
272pub type IOCONCLKDIV2 = crate::Reg<ioconclkdiv2::IOCONCLKDIV2_SPEC>;
273#[doc = "Peripheral clock 2 to the IOCON block for programmable glitch filter"]
274pub mod ioconclkdiv2;
275#[doc = "IOCONCLKDIV1 register accessor: an alias for `Reg<IOCONCLKDIV1_SPEC>`"]
276pub type IOCONCLKDIV1 = crate::Reg<ioconclkdiv1::IOCONCLKDIV1_SPEC>;
277#[doc = "Peripheral clock 1 to the IOCON block for programmable glitch filter"]
278pub mod ioconclkdiv1;
279#[doc = "IOCONCLKDIV0 register accessor: an alias for `Reg<IOCONCLKDIV0_SPEC>`"]
280pub type IOCONCLKDIV0 = crate::Reg<ioconclkdiv0::IOCONCLKDIV0_SPEC>;
281#[doc = "Peripheral clock 0 to the IOCON block for programmable glitch filter"]
282pub mod ioconclkdiv0;
283#[doc = "BODCTRL register accessor: an alias for `Reg<BODCTRL_SPEC>`"]
284pub type BODCTRL = crate::Reg<bodctrl::BODCTRL_SPEC>;
285#[doc = "BOD control register"]
286pub mod bodctrl;
287#[doc = "SYSTCKCAL register accessor: an alias for `Reg<SYSTCKCAL_SPEC>`"]
288pub type SYSTCKCAL = crate::Reg<systckcal::SYSTCKCAL_SPEC>;
289#[doc = "System tick timer calibration register"]
290pub mod systckcal;
291#[doc = "IRQLATENCY register accessor: an alias for `Reg<IRQLATENCY_SPEC>`"]
292pub type IRQLATENCY = crate::Reg<irqlatency::IRQLATENCY_SPEC>;
293#[doc = "IRQ latency register"]
294pub mod irqlatency;
295#[doc = "NMISRC register accessor: an alias for `Reg<NMISRC_SPEC>`"]
296pub type NMISRC = crate::Reg<nmisrc::NMISRC_SPEC>;
297#[doc = "NMI source selection register"]
298pub mod nmisrc;
299#[doc = "PINTSEL register accessor: an alias for `Reg<PINTSEL_SPEC>`"]
300pub type PINTSEL = crate::Reg<pintsel::PINTSEL_SPEC>;
301#[doc = "Pin interrupt select registers N"]
302pub mod pintsel;
303#[doc = "STARTERP0 register accessor: an alias for `Reg<STARTERP0_SPEC>`"]
304pub type STARTERP0 = crate::Reg<starterp0::STARTERP0_SPEC>;
305#[doc = "Start logic 0 pin wake-up enable register 0"]
306pub mod starterp0;
307#[doc = "STARTERP1 register accessor: an alias for `Reg<STARTERP1_SPEC>`"]
308pub type STARTERP1 = crate::Reg<starterp1::STARTERP1_SPEC>;
309#[doc = "Start logic 0 pin wake-up enable register 1"]
310pub mod starterp1;
311#[doc = "PDSLEEPCFG register accessor: an alias for `Reg<PDSLEEPCFG_SPEC>`"]
312pub type PDSLEEPCFG = crate::Reg<pdsleepcfg::PDSLEEPCFG_SPEC>;
313#[doc = "Deep-sleep configuration register"]
314pub mod pdsleepcfg;
315#[doc = "PDAWAKECFG register accessor: an alias for `Reg<PDAWAKECFG_SPEC>`"]
316pub type PDAWAKECFG = crate::Reg<pdawakecfg::PDAWAKECFG_SPEC>;
317#[doc = "Wake-up configuration register"]
318pub mod pdawakecfg;
319#[doc = "PDRUNCFG register accessor: an alias for `Reg<PDRUNCFG_SPEC>`"]
320pub type PDRUNCFG = crate::Reg<pdruncfg::PDRUNCFG_SPEC>;
321#[doc = "Power configuration register"]
322pub mod pdruncfg;
323#[doc = "DEVICE_ID register accessor: an alias for `Reg<DEVICE_ID_SPEC>`"]
324pub type DEVICE_ID = crate::Reg<device_id::DEVICE_ID_SPEC>;
325#[doc = "Part ID register"]
326pub mod device_id;