Struct lpc845_pac::spi0::div::DIVVAL_W

pub struct DIVVAL_W<'a> { /* fields omitted */ }

Field DIVVAL writer - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536.

Implementations

impl<'a> DIVVAL_W<'a>

pub unsafe fn bits(self, value: u16) -> &'a mut W

Writes raw bits to the field