Enum lpc845_pac::adc0::seq_ctrl::SYNCBYPASS_A [−][src]
pub enum SYNCBYPASS_A {
ENABLE_TRIGGER_SYNCH,
BYPASS_TRIGGER_SYNCH,
}
Expand description
Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period.
Value on reset: 0
Variants
0: Enable trigger synchronization. The hardware trigger bypass is not enabled.
1: Bypass trigger synchronization. The hardware trigger bypass is enabled.
Trait Implementations
Performs the conversion.