[−][src]Module lpc845_pac::spi0::txdatctl
SPI Transmit Data with Control
Structs
EOF_W | Write proxy for field |
EOT_W | Write proxy for field |
LEN_W | Write proxy for field |
RXIGNORE_W | Write proxy for field |
TXDAT_W | Write proxy for field |
TXSSEL0_N_W | Write proxy for field |
TXSSEL1_N_W | Write proxy for field |
TXSSEL2_N_W | Write proxy for field |
TXSSEL3_N_W | Write proxy for field |
Enums
EOF_A | End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits. |
EOT_A | End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register. |
LEN_A | Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. ... 0xF = Data transfer is 16 bits in length. |
RXIGNORE_A | Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA. |
TXSSEL0_N_A | Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in the CFG register. |
TXSSEL1_N_A | Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL1 pin is configured by bits in the CFG register. |
TXSSEL2_N_A | Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL2 pin is configured by bits in the CFG register. |
TXSSEL3_N_A | Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. Remark: The active state of the SSEL3 pin is configured by bits in the CFG register. |
Type Definitions
EOF_R | Reader of field |
EOT_R | Reader of field |
LEN_R | Reader of field |
R | Reader of register TXDATCTL |
RXIGNORE_R | Reader of field |
TXDAT_R | Reader of field |
TXSSEL0_N_R | Reader of field |
TXSSEL1_N_R | Reader of field |
TXSSEL2_N_R | Reader of field |
TXSSEL3_N_R | Reader of field |
W | Writer for register TXDATCTL |