[−][src]Module lpc845_pac::spi0::intenset
SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
Structs
| RXOVEN_W | Write proxy for field |
| RXRDYEN_W | Write proxy for field |
| SSAEN_W | Write proxy for field |
| SSDEN_W | Write proxy for field |
| TXRDYEN_W | Write proxy for field |
| TXUREN_W | Write proxy for field |
Enums
| RXOVEN_A | Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur. |
| RXRDYEN_A | Determines whether an interrupt occurs when receiver data is available. |
| SSAEN_A | Determines whether an interrupt occurs when the Slave Select is asserted. |
| SSDEN_A | Determines whether an interrupt occurs when the Slave Select is deasserted. |
| TXRDYEN_A | Determines whether an interrupt occurs when the transmitter holding register is available. |
| TXUREN_A | Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available. |
Type Definitions
| R | Reader of register INTENSET |
| RXOVEN_R | Reader of field |
| RXRDYEN_R | Reader of field |
| SSAEN_R | Reader of field |
| SSDEN_R | Reader of field |
| TXRDYEN_R | Reader of field |
| TXUREN_R | Reader of field |
| W | Writer for register INTENSET |