Struct lpc82x::usart0::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub cfg: CFG,
    pub ctl: CTL,
    pub stat: STAT,
    pub intenset: INTENSET,
    pub intenclr: INTENCLR,
    pub rxdat: RXDAT,
    pub rxdatstat: RXDATSTAT,
    pub txdat: TXDAT,
    pub brg: BRG,
    pub intstat: INTSTAT,
    pub osr: OSR,
    pub addr: ADDR,
}

Register block

Fields

cfg: CFG

0x00 - USART Configuration register. Basic USART configuration settings that typically are not changed during operation.

ctl: CTL

0x04 - USART Control register. USART control settings that are more likely to change during operation.

stat: STAT

0x08 - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.

intenset: INTENSET

0x0c - Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.

intenclr: INTENCLR

0x10 - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.

rxdat: RXDAT

0x14 - Receiver Data register. Contains the last character received.

rxdatstat: RXDATSTAT

0x18 - Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together.

txdat: TXDAT

0x1c - Transmit Data register. Data to be transmitted is written here.

brg: BRG

0x20 - Baud Rate Generator register. 16-bit integer baud rate divisor value.

intstat: INTSTAT

0x24 - Interrupt status register. Reflects interrupts that are currently enabled.

osr: OSR

0x28 - Oversample selection register for asynchronous communication.

addr: ADDR

0x2c - Address register for automatic address matching.

Trait Implementations