lpc82x_pac/acomp/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below):\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum EDGESEL_A {
41    #[doc = "0: Falling edges"]
42    FALLING_EDGES = 0,
43    #[doc = "1: Rising edges"]
44    RISING_EDGES = 1,
45    #[doc = "2: Both edges"]
46    BOTH_EDGES0 = 2,
47    #[doc = "3: Both edges"]
48    BOTH_EDGES1 = 3,
49}
50impl From<EDGESEL_A> for u8 {
51    #[inline(always)]
52    fn from(variant: EDGESEL_A) -> Self {
53        variant as _
54    }
55}
56#[doc = "Field `EDGESEL` reader - This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below):"]
57pub struct EDGESEL_R(crate::FieldReader<u8, EDGESEL_A>);
58impl EDGESEL_R {
59    pub(crate) fn new(bits: u8) -> Self {
60        EDGESEL_R(crate::FieldReader::new(bits))
61    }
62    #[doc = r"Get enumerated values variant"]
63    #[inline(always)]
64    pub fn variant(&self) -> EDGESEL_A {
65        match self.bits {
66            0 => EDGESEL_A::FALLING_EDGES,
67            1 => EDGESEL_A::RISING_EDGES,
68            2 => EDGESEL_A::BOTH_EDGES0,
69            3 => EDGESEL_A::BOTH_EDGES1,
70            _ => unreachable!(),
71        }
72    }
73    #[doc = "Checks if the value of the field is `FALLING_EDGES`"]
74    #[inline(always)]
75    pub fn is_falling_edges(&self) -> bool {
76        **self == EDGESEL_A::FALLING_EDGES
77    }
78    #[doc = "Checks if the value of the field is `RISING_EDGES`"]
79    #[inline(always)]
80    pub fn is_rising_edges(&self) -> bool {
81        **self == EDGESEL_A::RISING_EDGES
82    }
83    #[doc = "Checks if the value of the field is `BOTH_EDGES0`"]
84    #[inline(always)]
85    pub fn is_both_edges0(&self) -> bool {
86        **self == EDGESEL_A::BOTH_EDGES0
87    }
88    #[doc = "Checks if the value of the field is `BOTH_EDGES1`"]
89    #[inline(always)]
90    pub fn is_both_edges1(&self) -> bool {
91        **self == EDGESEL_A::BOTH_EDGES1
92    }
93}
94impl core::ops::Deref for EDGESEL_R {
95    type Target = crate::FieldReader<u8, EDGESEL_A>;
96    #[inline(always)]
97    fn deref(&self) -> &Self::Target {
98        &self.0
99    }
100}
101#[doc = "Field `EDGESEL` writer - This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below):"]
102pub struct EDGESEL_W<'a> {
103    w: &'a mut W,
104}
105impl<'a> EDGESEL_W<'a> {
106    #[doc = r"Writes `variant` to the field"]
107    #[inline(always)]
108    pub fn variant(self, variant: EDGESEL_A) -> &'a mut W {
109        self.bits(variant.into())
110    }
111    #[doc = "Falling edges"]
112    #[inline(always)]
113    pub fn falling_edges(self) -> &'a mut W {
114        self.variant(EDGESEL_A::FALLING_EDGES)
115    }
116    #[doc = "Rising edges"]
117    #[inline(always)]
118    pub fn rising_edges(self) -> &'a mut W {
119        self.variant(EDGESEL_A::RISING_EDGES)
120    }
121    #[doc = "Both edges"]
122    #[inline(always)]
123    pub fn both_edges0(self) -> &'a mut W {
124        self.variant(EDGESEL_A::BOTH_EDGES0)
125    }
126    #[doc = "Both edges"]
127    #[inline(always)]
128    pub fn both_edges1(self) -> &'a mut W {
129        self.variant(EDGESEL_A::BOTH_EDGES1)
130    }
131    #[doc = r"Writes raw bits to the field"]
132    #[inline(always)]
133    pub fn bits(self, value: u8) -> &'a mut W {
134        self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3);
135        self.w
136    }
137}
138#[doc = "Comparator output control\n\nValue on reset: 0"]
139#[derive(Clone, Copy, Debug, PartialEq)]
140pub enum COMPSA_A {
141    #[doc = "0: Comparator output is used directly."]
142    COMPSA_0 = 0,
143    #[doc = "1: Comparator output is synchronized to the bus clock for output to other modules."]
144    COMPSA_1 = 1,
145}
146impl From<COMPSA_A> for bool {
147    #[inline(always)]
148    fn from(variant: COMPSA_A) -> Self {
149        variant as u8 != 0
150    }
151}
152#[doc = "Field `COMPSA` reader - Comparator output control"]
153pub struct COMPSA_R(crate::FieldReader<bool, COMPSA_A>);
154impl COMPSA_R {
155    pub(crate) fn new(bits: bool) -> Self {
156        COMPSA_R(crate::FieldReader::new(bits))
157    }
158    #[doc = r"Get enumerated values variant"]
159    #[inline(always)]
160    pub fn variant(&self) -> COMPSA_A {
161        match self.bits {
162            false => COMPSA_A::COMPSA_0,
163            true => COMPSA_A::COMPSA_1,
164        }
165    }
166    #[doc = "Checks if the value of the field is `COMPSA_0`"]
167    #[inline(always)]
168    pub fn is_compsa_0(&self) -> bool {
169        **self == COMPSA_A::COMPSA_0
170    }
171    #[doc = "Checks if the value of the field is `COMPSA_1`"]
172    #[inline(always)]
173    pub fn is_compsa_1(&self) -> bool {
174        **self == COMPSA_A::COMPSA_1
175    }
176}
177impl core::ops::Deref for COMPSA_R {
178    type Target = crate::FieldReader<bool, COMPSA_A>;
179    #[inline(always)]
180    fn deref(&self) -> &Self::Target {
181        &self.0
182    }
183}
184#[doc = "Field `COMPSA` writer - Comparator output control"]
185pub struct COMPSA_W<'a> {
186    w: &'a mut W,
187}
188impl<'a> COMPSA_W<'a> {
189    #[doc = r"Writes `variant` to the field"]
190    #[inline(always)]
191    pub fn variant(self, variant: COMPSA_A) -> &'a mut W {
192        self.bit(variant.into())
193    }
194    #[doc = "Comparator output is used directly."]
195    #[inline(always)]
196    pub fn compsa_0(self) -> &'a mut W {
197        self.variant(COMPSA_A::COMPSA_0)
198    }
199    #[doc = "Comparator output is synchronized to the bus clock for output to other modules."]
200    #[inline(always)]
201    pub fn compsa_1(self) -> &'a mut W {
202        self.variant(COMPSA_A::COMPSA_1)
203    }
204    #[doc = r"Sets the field bit"]
205    #[inline(always)]
206    pub fn set_bit(self) -> &'a mut W {
207        self.bit(true)
208    }
209    #[doc = r"Clears the field bit"]
210    #[inline(always)]
211    pub fn clear_bit(self) -> &'a mut W {
212        self.bit(false)
213    }
214    #[doc = r"Writes raw bits to the field"]
215    #[inline(always)]
216    pub fn bit(self, value: bool) -> &'a mut W {
217        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
218        self.w
219    }
220}
221#[doc = "Selects positive voltage input\n\nValue on reset: 0"]
222#[derive(Clone, Copy, Debug, PartialEq)]
223#[repr(u8)]
224pub enum COMP_VP_SEL_A {
225    #[doc = "0: VOLTAGE_LADDER_OUTPUT"]
226    VOLTAGE_LADDER_OUTPUT = 0,
227    #[doc = "1: ACMP_I1"]
228    ACMP_I1 = 1,
229    #[doc = "2: ACMP_I2"]
230    ACMP_I2 = 2,
231    #[doc = "3: ACMP_I3"]
232    ACMP_I3 = 3,
233    #[doc = "4: ACMP_I4"]
234    ACMP_I4 = 4,
235    #[doc = "5: Band gap. Internal reference voltage."]
236    BAND_GAP = 5,
237    #[doc = "6: ADC channel 0 input"]
238    ADC_0 = 6,
239}
240impl From<COMP_VP_SEL_A> for u8 {
241    #[inline(always)]
242    fn from(variant: COMP_VP_SEL_A) -> Self {
243        variant as _
244    }
245}
246#[doc = "Field `COMP_VP_SEL` reader - Selects positive voltage input"]
247pub struct COMP_VP_SEL_R(crate::FieldReader<u8, COMP_VP_SEL_A>);
248impl COMP_VP_SEL_R {
249    pub(crate) fn new(bits: u8) -> Self {
250        COMP_VP_SEL_R(crate::FieldReader::new(bits))
251    }
252    #[doc = r"Get enumerated values variant"]
253    #[inline(always)]
254    pub fn variant(&self) -> Option<COMP_VP_SEL_A> {
255        match self.bits {
256            0 => Some(COMP_VP_SEL_A::VOLTAGE_LADDER_OUTPUT),
257            1 => Some(COMP_VP_SEL_A::ACMP_I1),
258            2 => Some(COMP_VP_SEL_A::ACMP_I2),
259            3 => Some(COMP_VP_SEL_A::ACMP_I3),
260            4 => Some(COMP_VP_SEL_A::ACMP_I4),
261            5 => Some(COMP_VP_SEL_A::BAND_GAP),
262            6 => Some(COMP_VP_SEL_A::ADC_0),
263            _ => None,
264        }
265    }
266    #[doc = "Checks if the value of the field is `VOLTAGE_LADDER_OUTPUT`"]
267    #[inline(always)]
268    pub fn is_voltage_ladder_output(&self) -> bool {
269        **self == COMP_VP_SEL_A::VOLTAGE_LADDER_OUTPUT
270    }
271    #[doc = "Checks if the value of the field is `ACMP_I1`"]
272    #[inline(always)]
273    pub fn is_acmp_i1(&self) -> bool {
274        **self == COMP_VP_SEL_A::ACMP_I1
275    }
276    #[doc = "Checks if the value of the field is `ACMP_I2`"]
277    #[inline(always)]
278    pub fn is_acmp_i2(&self) -> bool {
279        **self == COMP_VP_SEL_A::ACMP_I2
280    }
281    #[doc = "Checks if the value of the field is `ACMP_I3`"]
282    #[inline(always)]
283    pub fn is_acmp_i3(&self) -> bool {
284        **self == COMP_VP_SEL_A::ACMP_I3
285    }
286    #[doc = "Checks if the value of the field is `ACMP_I4`"]
287    #[inline(always)]
288    pub fn is_acmp_i4(&self) -> bool {
289        **self == COMP_VP_SEL_A::ACMP_I4
290    }
291    #[doc = "Checks if the value of the field is `BAND_GAP`"]
292    #[inline(always)]
293    pub fn is_band_gap(&self) -> bool {
294        **self == COMP_VP_SEL_A::BAND_GAP
295    }
296    #[doc = "Checks if the value of the field is `ADC_0`"]
297    #[inline(always)]
298    pub fn is_adc_0(&self) -> bool {
299        **self == COMP_VP_SEL_A::ADC_0
300    }
301}
302impl core::ops::Deref for COMP_VP_SEL_R {
303    type Target = crate::FieldReader<u8, COMP_VP_SEL_A>;
304    #[inline(always)]
305    fn deref(&self) -> &Self::Target {
306        &self.0
307    }
308}
309#[doc = "Field `COMP_VP_SEL` writer - Selects positive voltage input"]
310pub struct COMP_VP_SEL_W<'a> {
311    w: &'a mut W,
312}
313impl<'a> COMP_VP_SEL_W<'a> {
314    #[doc = r"Writes `variant` to the field"]
315    #[inline(always)]
316    pub fn variant(self, variant: COMP_VP_SEL_A) -> &'a mut W {
317        unsafe { self.bits(variant.into()) }
318    }
319    #[doc = "VOLTAGE_LADDER_OUTPUT"]
320    #[inline(always)]
321    pub fn voltage_ladder_output(self) -> &'a mut W {
322        self.variant(COMP_VP_SEL_A::VOLTAGE_LADDER_OUTPUT)
323    }
324    #[doc = "ACMP_I1"]
325    #[inline(always)]
326    pub fn acmp_i1(self) -> &'a mut W {
327        self.variant(COMP_VP_SEL_A::ACMP_I1)
328    }
329    #[doc = "ACMP_I2"]
330    #[inline(always)]
331    pub fn acmp_i2(self) -> &'a mut W {
332        self.variant(COMP_VP_SEL_A::ACMP_I2)
333    }
334    #[doc = "ACMP_I3"]
335    #[inline(always)]
336    pub fn acmp_i3(self) -> &'a mut W {
337        self.variant(COMP_VP_SEL_A::ACMP_I3)
338    }
339    #[doc = "ACMP_I4"]
340    #[inline(always)]
341    pub fn acmp_i4(self) -> &'a mut W {
342        self.variant(COMP_VP_SEL_A::ACMP_I4)
343    }
344    #[doc = "Band gap. Internal reference voltage."]
345    #[inline(always)]
346    pub fn band_gap(self) -> &'a mut W {
347        self.variant(COMP_VP_SEL_A::BAND_GAP)
348    }
349    #[doc = "ADC channel 0 input"]
350    #[inline(always)]
351    pub fn adc_0(self) -> &'a mut W {
352        self.variant(COMP_VP_SEL_A::ADC_0)
353    }
354    #[doc = r"Writes raw bits to the field"]
355    #[inline(always)]
356    pub unsafe fn bits(self, value: u8) -> &'a mut W {
357        self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8);
358        self.w
359    }
360}
361#[doc = "Selects negative voltage input\n\nValue on reset: 0"]
362#[derive(Clone, Copy, Debug, PartialEq)]
363#[repr(u8)]
364pub enum COMP_VM_SEL_A {
365    #[doc = "0: VOLTAGE_LADDER_OUTPUT"]
366    VOLTAGE_LADDER_OUTPUT = 0,
367    #[doc = "1: ACMP_I1"]
368    ACMP_I1 = 1,
369    #[doc = "2: ACMP_I2"]
370    ACMP_I2 = 2,
371    #[doc = "3: ACMP_I3"]
372    ACMP_I3 = 3,
373    #[doc = "4: ACMP_I4"]
374    ACMP_I4 = 4,
375    #[doc = "5: Band gap. Internal reference voltage."]
376    BAND_GAP = 5,
377    #[doc = "6: ADC channel 0 input"]
378    ADC_0 = 6,
379}
380impl From<COMP_VM_SEL_A> for u8 {
381    #[inline(always)]
382    fn from(variant: COMP_VM_SEL_A) -> Self {
383        variant as _
384    }
385}
386#[doc = "Field `COMP_VM_SEL` reader - Selects negative voltage input"]
387pub struct COMP_VM_SEL_R(crate::FieldReader<u8, COMP_VM_SEL_A>);
388impl COMP_VM_SEL_R {
389    pub(crate) fn new(bits: u8) -> Self {
390        COMP_VM_SEL_R(crate::FieldReader::new(bits))
391    }
392    #[doc = r"Get enumerated values variant"]
393    #[inline(always)]
394    pub fn variant(&self) -> Option<COMP_VM_SEL_A> {
395        match self.bits {
396            0 => Some(COMP_VM_SEL_A::VOLTAGE_LADDER_OUTPUT),
397            1 => Some(COMP_VM_SEL_A::ACMP_I1),
398            2 => Some(COMP_VM_SEL_A::ACMP_I2),
399            3 => Some(COMP_VM_SEL_A::ACMP_I3),
400            4 => Some(COMP_VM_SEL_A::ACMP_I4),
401            5 => Some(COMP_VM_SEL_A::BAND_GAP),
402            6 => Some(COMP_VM_SEL_A::ADC_0),
403            _ => None,
404        }
405    }
406    #[doc = "Checks if the value of the field is `VOLTAGE_LADDER_OUTPUT`"]
407    #[inline(always)]
408    pub fn is_voltage_ladder_output(&self) -> bool {
409        **self == COMP_VM_SEL_A::VOLTAGE_LADDER_OUTPUT
410    }
411    #[doc = "Checks if the value of the field is `ACMP_I1`"]
412    #[inline(always)]
413    pub fn is_acmp_i1(&self) -> bool {
414        **self == COMP_VM_SEL_A::ACMP_I1
415    }
416    #[doc = "Checks if the value of the field is `ACMP_I2`"]
417    #[inline(always)]
418    pub fn is_acmp_i2(&self) -> bool {
419        **self == COMP_VM_SEL_A::ACMP_I2
420    }
421    #[doc = "Checks if the value of the field is `ACMP_I3`"]
422    #[inline(always)]
423    pub fn is_acmp_i3(&self) -> bool {
424        **self == COMP_VM_SEL_A::ACMP_I3
425    }
426    #[doc = "Checks if the value of the field is `ACMP_I4`"]
427    #[inline(always)]
428    pub fn is_acmp_i4(&self) -> bool {
429        **self == COMP_VM_SEL_A::ACMP_I4
430    }
431    #[doc = "Checks if the value of the field is `BAND_GAP`"]
432    #[inline(always)]
433    pub fn is_band_gap(&self) -> bool {
434        **self == COMP_VM_SEL_A::BAND_GAP
435    }
436    #[doc = "Checks if the value of the field is `ADC_0`"]
437    #[inline(always)]
438    pub fn is_adc_0(&self) -> bool {
439        **self == COMP_VM_SEL_A::ADC_0
440    }
441}
442impl core::ops::Deref for COMP_VM_SEL_R {
443    type Target = crate::FieldReader<u8, COMP_VM_SEL_A>;
444    #[inline(always)]
445    fn deref(&self) -> &Self::Target {
446        &self.0
447    }
448}
449#[doc = "Field `COMP_VM_SEL` writer - Selects negative voltage input"]
450pub struct COMP_VM_SEL_W<'a> {
451    w: &'a mut W,
452}
453impl<'a> COMP_VM_SEL_W<'a> {
454    #[doc = r"Writes `variant` to the field"]
455    #[inline(always)]
456    pub fn variant(self, variant: COMP_VM_SEL_A) -> &'a mut W {
457        unsafe { self.bits(variant.into()) }
458    }
459    #[doc = "VOLTAGE_LADDER_OUTPUT"]
460    #[inline(always)]
461    pub fn voltage_ladder_output(self) -> &'a mut W {
462        self.variant(COMP_VM_SEL_A::VOLTAGE_LADDER_OUTPUT)
463    }
464    #[doc = "ACMP_I1"]
465    #[inline(always)]
466    pub fn acmp_i1(self) -> &'a mut W {
467        self.variant(COMP_VM_SEL_A::ACMP_I1)
468    }
469    #[doc = "ACMP_I2"]
470    #[inline(always)]
471    pub fn acmp_i2(self) -> &'a mut W {
472        self.variant(COMP_VM_SEL_A::ACMP_I2)
473    }
474    #[doc = "ACMP_I3"]
475    #[inline(always)]
476    pub fn acmp_i3(self) -> &'a mut W {
477        self.variant(COMP_VM_SEL_A::ACMP_I3)
478    }
479    #[doc = "ACMP_I4"]
480    #[inline(always)]
481    pub fn acmp_i4(self) -> &'a mut W {
482        self.variant(COMP_VM_SEL_A::ACMP_I4)
483    }
484    #[doc = "Band gap. Internal reference voltage."]
485    #[inline(always)]
486    pub fn band_gap(self) -> &'a mut W {
487        self.variant(COMP_VM_SEL_A::BAND_GAP)
488    }
489    #[doc = "ADC channel 0 input"]
490    #[inline(always)]
491    pub fn adc_0(self) -> &'a mut W {
492        self.variant(COMP_VM_SEL_A::ADC_0)
493    }
494    #[doc = r"Writes raw bits to the field"]
495    #[inline(always)]
496    pub unsafe fn bits(self, value: u8) -> &'a mut W {
497        self.w.bits = (self.w.bits & !(0x07 << 11)) | ((value as u32 & 0x07) << 11);
498        self.w
499    }
500}
501#[doc = "Field `EDGECLR` reader - Interrupt clear bit. To clear the COMPEDGE bit and thus negate the interrupt request, toggle the EDGECLR bit by first writing a 1 and then a 0."]
502pub struct EDGECLR_R(crate::FieldReader<bool, bool>);
503impl EDGECLR_R {
504    pub(crate) fn new(bits: bool) -> Self {
505        EDGECLR_R(crate::FieldReader::new(bits))
506    }
507}
508impl core::ops::Deref for EDGECLR_R {
509    type Target = crate::FieldReader<bool, bool>;
510    #[inline(always)]
511    fn deref(&self) -> &Self::Target {
512        &self.0
513    }
514}
515#[doc = "Field `EDGECLR` writer - Interrupt clear bit. To clear the COMPEDGE bit and thus negate the interrupt request, toggle the EDGECLR bit by first writing a 1 and then a 0."]
516pub struct EDGECLR_W<'a> {
517    w: &'a mut W,
518}
519impl<'a> EDGECLR_W<'a> {
520    #[doc = r"Sets the field bit"]
521    #[inline(always)]
522    pub fn set_bit(self) -> &'a mut W {
523        self.bit(true)
524    }
525    #[doc = r"Clears the field bit"]
526    #[inline(always)]
527    pub fn clear_bit(self) -> &'a mut W {
528        self.bit(false)
529    }
530    #[doc = r"Writes raw bits to the field"]
531    #[inline(always)]
532    pub fn bit(self, value: bool) -> &'a mut W {
533        self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20);
534        self.w
535    }
536}
537#[doc = "Field `COMPSTAT` reader - Comparator status. This bit reflects the state of the comparator output."]
538pub struct COMPSTAT_R(crate::FieldReader<bool, bool>);
539impl COMPSTAT_R {
540    pub(crate) fn new(bits: bool) -> Self {
541        COMPSTAT_R(crate::FieldReader::new(bits))
542    }
543}
544impl core::ops::Deref for COMPSTAT_R {
545    type Target = crate::FieldReader<bool, bool>;
546    #[inline(always)]
547    fn deref(&self) -> &Self::Target {
548        &self.0
549    }
550}
551#[doc = "Field `COMPSTAT` writer - Comparator status. This bit reflects the state of the comparator output."]
552pub struct COMPSTAT_W<'a> {
553    w: &'a mut W,
554}
555impl<'a> COMPSTAT_W<'a> {
556    #[doc = r"Sets the field bit"]
557    #[inline(always)]
558    pub fn set_bit(self) -> &'a mut W {
559        self.bit(true)
560    }
561    #[doc = r"Clears the field bit"]
562    #[inline(always)]
563    pub fn clear_bit(self) -> &'a mut W {
564        self.bit(false)
565    }
566    #[doc = r"Writes raw bits to the field"]
567    #[inline(always)]
568    pub fn bit(self, value: bool) -> &'a mut W {
569        self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21);
570        self.w
571    }
572}
573#[doc = "Field `COMPEDGE` reader - Comparator edge-detect status."]
574pub struct COMPEDGE_R(crate::FieldReader<bool, bool>);
575impl COMPEDGE_R {
576    pub(crate) fn new(bits: bool) -> Self {
577        COMPEDGE_R(crate::FieldReader::new(bits))
578    }
579}
580impl core::ops::Deref for COMPEDGE_R {
581    type Target = crate::FieldReader<bool, bool>;
582    #[inline(always)]
583    fn deref(&self) -> &Self::Target {
584        &self.0
585    }
586}
587#[doc = "Field `COMPEDGE` writer - Comparator edge-detect status."]
588pub struct COMPEDGE_W<'a> {
589    w: &'a mut W,
590}
591impl<'a> COMPEDGE_W<'a> {
592    #[doc = r"Sets the field bit"]
593    #[inline(always)]
594    pub fn set_bit(self) -> &'a mut W {
595        self.bit(true)
596    }
597    #[doc = r"Clears the field bit"]
598    #[inline(always)]
599    pub fn clear_bit(self) -> &'a mut W {
600        self.bit(false)
601    }
602    #[doc = r"Writes raw bits to the field"]
603    #[inline(always)]
604    pub fn bit(self, value: bool) -> &'a mut W {
605        self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23);
606        self.w
607    }
608}
609#[doc = "Controls the hysteresis of the comparator. When the comparator is outputting a certain state, this is the difference between the selected signals, in the opposite direction from the state being output, that will switch the output.\n\nValue on reset: 0"]
610#[derive(Clone, Copy, Debug, PartialEq)]
611#[repr(u8)]
612pub enum HYS_A {
613    #[doc = "0: None (the output will switch as the voltages cross)"]
614    HYS_0 = 0,
615    #[doc = "1: 5 mv"]
616    HYS_1 = 1,
617    #[doc = "2: 10 mv"]
618    HYS_2 = 2,
619    #[doc = "3: 20 mv"]
620    HYS_3 = 3,
621}
622impl From<HYS_A> for u8 {
623    #[inline(always)]
624    fn from(variant: HYS_A) -> Self {
625        variant as _
626    }
627}
628#[doc = "Field `HYS` reader - Controls the hysteresis of the comparator. When the comparator is outputting a certain state, this is the difference between the selected signals, in the opposite direction from the state being output, that will switch the output."]
629pub struct HYS_R(crate::FieldReader<u8, HYS_A>);
630impl HYS_R {
631    pub(crate) fn new(bits: u8) -> Self {
632        HYS_R(crate::FieldReader::new(bits))
633    }
634    #[doc = r"Get enumerated values variant"]
635    #[inline(always)]
636    pub fn variant(&self) -> HYS_A {
637        match self.bits {
638            0 => HYS_A::HYS_0,
639            1 => HYS_A::HYS_1,
640            2 => HYS_A::HYS_2,
641            3 => HYS_A::HYS_3,
642            _ => unreachable!(),
643        }
644    }
645    #[doc = "Checks if the value of the field is `HYS_0`"]
646    #[inline(always)]
647    pub fn is_hys_0(&self) -> bool {
648        **self == HYS_A::HYS_0
649    }
650    #[doc = "Checks if the value of the field is `HYS_1`"]
651    #[inline(always)]
652    pub fn is_hys_1(&self) -> bool {
653        **self == HYS_A::HYS_1
654    }
655    #[doc = "Checks if the value of the field is `HYS_2`"]
656    #[inline(always)]
657    pub fn is_hys_2(&self) -> bool {
658        **self == HYS_A::HYS_2
659    }
660    #[doc = "Checks if the value of the field is `HYS_3`"]
661    #[inline(always)]
662    pub fn is_hys_3(&self) -> bool {
663        **self == HYS_A::HYS_3
664    }
665}
666impl core::ops::Deref for HYS_R {
667    type Target = crate::FieldReader<u8, HYS_A>;
668    #[inline(always)]
669    fn deref(&self) -> &Self::Target {
670        &self.0
671    }
672}
673#[doc = "Field `HYS` writer - Controls the hysteresis of the comparator. When the comparator is outputting a certain state, this is the difference between the selected signals, in the opposite direction from the state being output, that will switch the output."]
674pub struct HYS_W<'a> {
675    w: &'a mut W,
676}
677impl<'a> HYS_W<'a> {
678    #[doc = r"Writes `variant` to the field"]
679    #[inline(always)]
680    pub fn variant(self, variant: HYS_A) -> &'a mut W {
681        self.bits(variant.into())
682    }
683    #[doc = "None (the output will switch as the voltages cross)"]
684    #[inline(always)]
685    pub fn hys_0(self) -> &'a mut W {
686        self.variant(HYS_A::HYS_0)
687    }
688    #[doc = "5 mv"]
689    #[inline(always)]
690    pub fn hys_1(self) -> &'a mut W {
691        self.variant(HYS_A::HYS_1)
692    }
693    #[doc = "10 mv"]
694    #[inline(always)]
695    pub fn hys_2(self) -> &'a mut W {
696        self.variant(HYS_A::HYS_2)
697    }
698    #[doc = "20 mv"]
699    #[inline(always)]
700    pub fn hys_3(self) -> &'a mut W {
701        self.variant(HYS_A::HYS_3)
702    }
703    #[doc = r"Writes raw bits to the field"]
704    #[inline(always)]
705    pub fn bits(self, value: u8) -> &'a mut W {
706        self.w.bits = (self.w.bits & !(0x03 << 25)) | ((value as u32 & 0x03) << 25);
707        self.w
708    }
709}
710impl R {
711    #[doc = "Bits 3:4 - This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below):"]
712    #[inline(always)]
713    pub fn edgesel(&self) -> EDGESEL_R {
714        EDGESEL_R::new(((self.bits >> 3) & 0x03) as u8)
715    }
716    #[doc = "Bit 6 - Comparator output control"]
717    #[inline(always)]
718    pub fn compsa(&self) -> COMPSA_R {
719        COMPSA_R::new(((self.bits >> 6) & 0x01) != 0)
720    }
721    #[doc = "Bits 8:10 - Selects positive voltage input"]
722    #[inline(always)]
723    pub fn comp_vp_sel(&self) -> COMP_VP_SEL_R {
724        COMP_VP_SEL_R::new(((self.bits >> 8) & 0x07) as u8)
725    }
726    #[doc = "Bits 11:13 - Selects negative voltage input"]
727    #[inline(always)]
728    pub fn comp_vm_sel(&self) -> COMP_VM_SEL_R {
729        COMP_VM_SEL_R::new(((self.bits >> 11) & 0x07) as u8)
730    }
731    #[doc = "Bit 20 - Interrupt clear bit. To clear the COMPEDGE bit and thus negate the interrupt request, toggle the EDGECLR bit by first writing a 1 and then a 0."]
732    #[inline(always)]
733    pub fn edgeclr(&self) -> EDGECLR_R {
734        EDGECLR_R::new(((self.bits >> 20) & 0x01) != 0)
735    }
736    #[doc = "Bit 21 - Comparator status. This bit reflects the state of the comparator output."]
737    #[inline(always)]
738    pub fn compstat(&self) -> COMPSTAT_R {
739        COMPSTAT_R::new(((self.bits >> 21) & 0x01) != 0)
740    }
741    #[doc = "Bit 23 - Comparator edge-detect status."]
742    #[inline(always)]
743    pub fn compedge(&self) -> COMPEDGE_R {
744        COMPEDGE_R::new(((self.bits >> 23) & 0x01) != 0)
745    }
746    #[doc = "Bits 25:26 - Controls the hysteresis of the comparator. When the comparator is outputting a certain state, this is the difference between the selected signals, in the opposite direction from the state being output, that will switch the output."]
747    #[inline(always)]
748    pub fn hys(&self) -> HYS_R {
749        HYS_R::new(((self.bits >> 25) & 0x03) as u8)
750    }
751}
752impl W {
753    #[doc = "Bits 3:4 - This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below):"]
754    #[inline(always)]
755    pub fn edgesel(&mut self) -> EDGESEL_W {
756        EDGESEL_W { w: self }
757    }
758    #[doc = "Bit 6 - Comparator output control"]
759    #[inline(always)]
760    pub fn compsa(&mut self) -> COMPSA_W {
761        COMPSA_W { w: self }
762    }
763    #[doc = "Bits 8:10 - Selects positive voltage input"]
764    #[inline(always)]
765    pub fn comp_vp_sel(&mut self) -> COMP_VP_SEL_W {
766        COMP_VP_SEL_W { w: self }
767    }
768    #[doc = "Bits 11:13 - Selects negative voltage input"]
769    #[inline(always)]
770    pub fn comp_vm_sel(&mut self) -> COMP_VM_SEL_W {
771        COMP_VM_SEL_W { w: self }
772    }
773    #[doc = "Bit 20 - Interrupt clear bit. To clear the COMPEDGE bit and thus negate the interrupt request, toggle the EDGECLR bit by first writing a 1 and then a 0."]
774    #[inline(always)]
775    pub fn edgeclr(&mut self) -> EDGECLR_W {
776        EDGECLR_W { w: self }
777    }
778    #[doc = "Bit 21 - Comparator status. This bit reflects the state of the comparator output."]
779    #[inline(always)]
780    pub fn compstat(&mut self) -> COMPSTAT_W {
781        COMPSTAT_W { w: self }
782    }
783    #[doc = "Bit 23 - Comparator edge-detect status."]
784    #[inline(always)]
785    pub fn compedge(&mut self) -> COMPEDGE_W {
786        COMPEDGE_W { w: self }
787    }
788    #[doc = "Bits 25:26 - Controls the hysteresis of the comparator. When the comparator is outputting a certain state, this is the difference between the selected signals, in the opposite direction from the state being output, that will switch the output."]
789    #[inline(always)]
790    pub fn hys(&mut self) -> HYS_W {
791        HYS_W { w: self }
792    }
793    #[doc = "Writes raw bits to the register."]
794    #[inline(always)]
795    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
796        self.0.bits(bits);
797        self
798    }
799}
800#[doc = "Comparator control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
801pub struct CTRL_SPEC;
802impl crate::RegisterSpec for CTRL_SPEC {
803    type Ux = u32;
804}
805#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
806impl crate::Readable for CTRL_SPEC {
807    type Reader = R;
808}
809#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
810impl crate::Writable for CTRL_SPEC {
811    type Writer = W;
812}
813#[doc = "`reset()` method sets CTRL to value 0"]
814impl crate::Resettable for CTRL_SPEC {
815    #[inline(always)]
816    fn reset_value() -> Self::Ux {
817        0
818    }
819}
lpc82x_pac/acomp/ctrl.rs

lpc82x_pac/acomp/
ctrl.rs
