lpc82x_pac/usart0/
cfg.rs

1#[doc = "Register `CFG` reader"]
2pub struct R(crate::R<CFG_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CFG_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CFG_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CFG_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CFG` writer"]
17pub struct W(crate::W<CFG_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CFG_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CFG_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CFG_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "USART Enable.\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum ENABLE_A {
40    #[doc = "0: Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available."]
41    DISABLED = 0,
42    #[doc = "1: Enabled. The USART is enabled for operation."]
43    ENABLED = 1,
44}
45impl From<ENABLE_A> for bool {
46    #[inline(always)]
47    fn from(variant: ENABLE_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `ENABLE` reader - USART Enable."]
52pub struct ENABLE_R(crate::FieldReader<bool, ENABLE_A>);
53impl ENABLE_R {
54    pub(crate) fn new(bits: bool) -> Self {
55        ENABLE_R(crate::FieldReader::new(bits))
56    }
57    #[doc = r"Get enumerated values variant"]
58    #[inline(always)]
59    pub fn variant(&self) -> ENABLE_A {
60        match self.bits {
61            false => ENABLE_A::DISABLED,
62            true => ENABLE_A::ENABLED,
63        }
64    }
65    #[doc = "Checks if the value of the field is `DISABLED`"]
66    #[inline(always)]
67    pub fn is_disabled(&self) -> bool {
68        **self == ENABLE_A::DISABLED
69    }
70    #[doc = "Checks if the value of the field is `ENABLED`"]
71    #[inline(always)]
72    pub fn is_enabled(&self) -> bool {
73        **self == ENABLE_A::ENABLED
74    }
75}
76impl core::ops::Deref for ENABLE_R {
77    type Target = crate::FieldReader<bool, ENABLE_A>;
78    #[inline(always)]
79    fn deref(&self) -> &Self::Target {
80        &self.0
81    }
82}
83#[doc = "Field `ENABLE` writer - USART Enable."]
84pub struct ENABLE_W<'a> {
85    w: &'a mut W,
86}
87impl<'a> ENABLE_W<'a> {
88    #[doc = r"Writes `variant` to the field"]
89    #[inline(always)]
90    pub fn variant(self, variant: ENABLE_A) -> &'a mut W {
91        self.bit(variant.into())
92    }
93    #[doc = "Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available."]
94    #[inline(always)]
95    pub fn disabled(self) -> &'a mut W {
96        self.variant(ENABLE_A::DISABLED)
97    }
98    #[doc = "Enabled. The USART is enabled for operation."]
99    #[inline(always)]
100    pub fn enabled(self) -> &'a mut W {
101        self.variant(ENABLE_A::ENABLED)
102    }
103    #[doc = r"Sets the field bit"]
104    #[inline(always)]
105    pub fn set_bit(self) -> &'a mut W {
106        self.bit(true)
107    }
108    #[doc = r"Clears the field bit"]
109    #[inline(always)]
110    pub fn clear_bit(self) -> &'a mut W {
111        self.bit(false)
112    }
113    #[doc = r"Writes raw bits to the field"]
114    #[inline(always)]
115    pub fn bit(self, value: bool) -> &'a mut W {
116        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
117        self.w
118    }
119}
120#[doc = "Selects the data size for the USART.\n\nValue on reset: 0"]
121#[derive(Clone, Copy, Debug, PartialEq)]
122#[repr(u8)]
123pub enum DATALEN_A {
124    #[doc = "0: 7 bit Data length."]
125    BIT_7 = 0,
126    #[doc = "1: 8 bit Data length."]
127    BIT_8 = 1,
128    #[doc = "2: 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register."]
129    BIT_9 = 2,
130}
131impl From<DATALEN_A> for u8 {
132    #[inline(always)]
133    fn from(variant: DATALEN_A) -> Self {
134        variant as _
135    }
136}
137#[doc = "Field `DATALEN` reader - Selects the data size for the USART."]
138pub struct DATALEN_R(crate::FieldReader<u8, DATALEN_A>);
139impl DATALEN_R {
140    pub(crate) fn new(bits: u8) -> Self {
141        DATALEN_R(crate::FieldReader::new(bits))
142    }
143    #[doc = r"Get enumerated values variant"]
144    #[inline(always)]
145    pub fn variant(&self) -> Option<DATALEN_A> {
146        match self.bits {
147            0 => Some(DATALEN_A::BIT_7),
148            1 => Some(DATALEN_A::BIT_8),
149            2 => Some(DATALEN_A::BIT_9),
150            _ => None,
151        }
152    }
153    #[doc = "Checks if the value of the field is `BIT_7`"]
154    #[inline(always)]
155    pub fn is_bit_7(&self) -> bool {
156        **self == DATALEN_A::BIT_7
157    }
158    #[doc = "Checks if the value of the field is `BIT_8`"]
159    #[inline(always)]
160    pub fn is_bit_8(&self) -> bool {
161        **self == DATALEN_A::BIT_8
162    }
163    #[doc = "Checks if the value of the field is `BIT_9`"]
164    #[inline(always)]
165    pub fn is_bit_9(&self) -> bool {
166        **self == DATALEN_A::BIT_9
167    }
168}
169impl core::ops::Deref for DATALEN_R {
170    type Target = crate::FieldReader<u8, DATALEN_A>;
171    #[inline(always)]
172    fn deref(&self) -> &Self::Target {
173        &self.0
174    }
175}
176#[doc = "Field `DATALEN` writer - Selects the data size for the USART."]
177pub struct DATALEN_W<'a> {
178    w: &'a mut W,
179}
180impl<'a> DATALEN_W<'a> {
181    #[doc = r"Writes `variant` to the field"]
182    #[inline(always)]
183    pub fn variant(self, variant: DATALEN_A) -> &'a mut W {
184        unsafe { self.bits(variant.into()) }
185    }
186    #[doc = "7 bit Data length."]
187    #[inline(always)]
188    pub fn bit_7(self) -> &'a mut W {
189        self.variant(DATALEN_A::BIT_7)
190    }
191    #[doc = "8 bit Data length."]
192    #[inline(always)]
193    pub fn bit_8(self) -> &'a mut W {
194        self.variant(DATALEN_A::BIT_8)
195    }
196    #[doc = "9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register."]
197    #[inline(always)]
198    pub fn bit_9(self) -> &'a mut W {
199        self.variant(DATALEN_A::BIT_9)
200    }
201    #[doc = r"Writes raw bits to the field"]
202    #[inline(always)]
203    pub unsafe fn bits(self, value: u8) -> &'a mut W {
204        self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2);
205        self.w
206    }
207}
208#[doc = "Selects what type of parity is used by the USART.\n\nValue on reset: 0"]
209#[derive(Clone, Copy, Debug, PartialEq)]
210#[repr(u8)]
211pub enum PARITYSEL_A {
212    #[doc = "0: No parity."]
213    NO_PARITY = 0,
214    #[doc = "2: Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even."]
215    EVEN_PARITY = 2,
216    #[doc = "3: Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd."]
217    ODD_PARITY = 3,
218}
219impl From<PARITYSEL_A> for u8 {
220    #[inline(always)]
221    fn from(variant: PARITYSEL_A) -> Self {
222        variant as _
223    }
224}
225#[doc = "Field `PARITYSEL` reader - Selects what type of parity is used by the USART."]
226pub struct PARITYSEL_R(crate::FieldReader<u8, PARITYSEL_A>);
227impl PARITYSEL_R {
228    pub(crate) fn new(bits: u8) -> Self {
229        PARITYSEL_R(crate::FieldReader::new(bits))
230    }
231    #[doc = r"Get enumerated values variant"]
232    #[inline(always)]
233    pub fn variant(&self) -> Option<PARITYSEL_A> {
234        match self.bits {
235            0 => Some(PARITYSEL_A::NO_PARITY),
236            2 => Some(PARITYSEL_A::EVEN_PARITY),
237            3 => Some(PARITYSEL_A::ODD_PARITY),
238            _ => None,
239        }
240    }
241    #[doc = "Checks if the value of the field is `NO_PARITY`"]
242    #[inline(always)]
243    pub fn is_no_parity(&self) -> bool {
244        **self == PARITYSEL_A::NO_PARITY
245    }
246    #[doc = "Checks if the value of the field is `EVEN_PARITY`"]
247    #[inline(always)]
248    pub fn is_even_parity(&self) -> bool {
249        **self == PARITYSEL_A::EVEN_PARITY
250    }
251    #[doc = "Checks if the value of the field is `ODD_PARITY`"]
252    #[inline(always)]
253    pub fn is_odd_parity(&self) -> bool {
254        **self == PARITYSEL_A::ODD_PARITY
255    }
256}
257impl core::ops::Deref for PARITYSEL_R {
258    type Target = crate::FieldReader<u8, PARITYSEL_A>;
259    #[inline(always)]
260    fn deref(&self) -> &Self::Target {
261        &self.0
262    }
263}
264#[doc = "Field `PARITYSEL` writer - Selects what type of parity is used by the USART."]
265pub struct PARITYSEL_W<'a> {
266    w: &'a mut W,
267}
268impl<'a> PARITYSEL_W<'a> {
269    #[doc = r"Writes `variant` to the field"]
270    #[inline(always)]
271    pub fn variant(self, variant: PARITYSEL_A) -> &'a mut W {
272        unsafe { self.bits(variant.into()) }
273    }
274    #[doc = "No parity."]
275    #[inline(always)]
276    pub fn no_parity(self) -> &'a mut W {
277        self.variant(PARITYSEL_A::NO_PARITY)
278    }
279    #[doc = "Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even."]
280    #[inline(always)]
281    pub fn even_parity(self) -> &'a mut W {
282        self.variant(PARITYSEL_A::EVEN_PARITY)
283    }
284    #[doc = "Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd."]
285    #[inline(always)]
286    pub fn odd_parity(self) -> &'a mut W {
287        self.variant(PARITYSEL_A::ODD_PARITY)
288    }
289    #[doc = r"Writes raw bits to the field"]
290    #[inline(always)]
291    pub unsafe fn bits(self, value: u8) -> &'a mut W {
292        self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4);
293        self.w
294    }
295}
296#[doc = "Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.\n\nValue on reset: 0"]
297#[derive(Clone, Copy, Debug, PartialEq)]
298pub enum STOPLEN_A {
299    #[doc = "0: 1 stop bit."]
300    BIT_1 = 0,
301    #[doc = "1: 2 stop bits. This setting should only be used for asynchronous communication."]
302    BITS_2 = 1,
303}
304impl From<STOPLEN_A> for bool {
305    #[inline(always)]
306    fn from(variant: STOPLEN_A) -> Self {
307        variant as u8 != 0
308    }
309}
310#[doc = "Field `STOPLEN` reader - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data."]
311pub struct STOPLEN_R(crate::FieldReader<bool, STOPLEN_A>);
312impl STOPLEN_R {
313    pub(crate) fn new(bits: bool) -> Self {
314        STOPLEN_R(crate::FieldReader::new(bits))
315    }
316    #[doc = r"Get enumerated values variant"]
317    #[inline(always)]
318    pub fn variant(&self) -> STOPLEN_A {
319        match self.bits {
320            false => STOPLEN_A::BIT_1,
321            true => STOPLEN_A::BITS_2,
322        }
323    }
324    #[doc = "Checks if the value of the field is `BIT_1`"]
325    #[inline(always)]
326    pub fn is_bit_1(&self) -> bool {
327        **self == STOPLEN_A::BIT_1
328    }
329    #[doc = "Checks if the value of the field is `BITS_2`"]
330    #[inline(always)]
331    pub fn is_bits_2(&self) -> bool {
332        **self == STOPLEN_A::BITS_2
333    }
334}
335impl core::ops::Deref for STOPLEN_R {
336    type Target = crate::FieldReader<bool, STOPLEN_A>;
337    #[inline(always)]
338    fn deref(&self) -> &Self::Target {
339        &self.0
340    }
341}
342#[doc = "Field `STOPLEN` writer - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data."]
343pub struct STOPLEN_W<'a> {
344    w: &'a mut W,
345}
346impl<'a> STOPLEN_W<'a> {
347    #[doc = r"Writes `variant` to the field"]
348    #[inline(always)]
349    pub fn variant(self, variant: STOPLEN_A) -> &'a mut W {
350        self.bit(variant.into())
351    }
352    #[doc = "1 stop bit."]
353    #[inline(always)]
354    pub fn bit_1(self) -> &'a mut W {
355        self.variant(STOPLEN_A::BIT_1)
356    }
357    #[doc = "2 stop bits. This setting should only be used for asynchronous communication."]
358    #[inline(always)]
359    pub fn bits_2(self) -> &'a mut W {
360        self.variant(STOPLEN_A::BITS_2)
361    }
362    #[doc = r"Sets the field bit"]
363    #[inline(always)]
364    pub fn set_bit(self) -> &'a mut W {
365        self.bit(true)
366    }
367    #[doc = r"Clears the field bit"]
368    #[inline(always)]
369    pub fn clear_bit(self) -> &'a mut W {
370        self.bit(false)
371    }
372    #[doc = r"Writes raw bits to the field"]
373    #[inline(always)]
374    pub fn bit(self, value: bool) -> &'a mut W {
375        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
376        self.w
377    }
378}
379#[doc = "CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled.\n\nValue on reset: 0"]
380#[derive(Clone, Copy, Debug, PartialEq)]
381pub enum CTSEN_A {
382    #[doc = "0: No flow control. The transmitter does not receive any automatic flow control signal."]
383    DISABLED = 0,
384    #[doc = "1: Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes."]
385    ENABLED = 1,
386}
387impl From<CTSEN_A> for bool {
388    #[inline(always)]
389    fn from(variant: CTSEN_A) -> Self {
390        variant as u8 != 0
391    }
392}
393#[doc = "Field `CTSEN` reader - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled."]
394pub struct CTSEN_R(crate::FieldReader<bool, CTSEN_A>);
395impl CTSEN_R {
396    pub(crate) fn new(bits: bool) -> Self {
397        CTSEN_R(crate::FieldReader::new(bits))
398    }
399    #[doc = r"Get enumerated values variant"]
400    #[inline(always)]
401    pub fn variant(&self) -> CTSEN_A {
402        match self.bits {
403            false => CTSEN_A::DISABLED,
404            true => CTSEN_A::ENABLED,
405        }
406    }
407    #[doc = "Checks if the value of the field is `DISABLED`"]
408    #[inline(always)]
409    pub fn is_disabled(&self) -> bool {
410        **self == CTSEN_A::DISABLED
411    }
412    #[doc = "Checks if the value of the field is `ENABLED`"]
413    #[inline(always)]
414    pub fn is_enabled(&self) -> bool {
415        **self == CTSEN_A::ENABLED
416    }
417}
418impl core::ops::Deref for CTSEN_R {
419    type Target = crate::FieldReader<bool, CTSEN_A>;
420    #[inline(always)]
421    fn deref(&self) -> &Self::Target {
422        &self.0
423    }
424}
425#[doc = "Field `CTSEN` writer - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled."]
426pub struct CTSEN_W<'a> {
427    w: &'a mut W,
428}
429impl<'a> CTSEN_W<'a> {
430    #[doc = r"Writes `variant` to the field"]
431    #[inline(always)]
432    pub fn variant(self, variant: CTSEN_A) -> &'a mut W {
433        self.bit(variant.into())
434    }
435    #[doc = "No flow control. The transmitter does not receive any automatic flow control signal."]
436    #[inline(always)]
437    pub fn disabled(self) -> &'a mut W {
438        self.variant(CTSEN_A::DISABLED)
439    }
440    #[doc = "Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes."]
441    #[inline(always)]
442    pub fn enabled(self) -> &'a mut W {
443        self.variant(CTSEN_A::ENABLED)
444    }
445    #[doc = r"Sets the field bit"]
446    #[inline(always)]
447    pub fn set_bit(self) -> &'a mut W {
448        self.bit(true)
449    }
450    #[doc = r"Clears the field bit"]
451    #[inline(always)]
452    pub fn clear_bit(self) -> &'a mut W {
453        self.bit(false)
454    }
455    #[doc = r"Writes raw bits to the field"]
456    #[inline(always)]
457    pub fn bit(self, value: bool) -> &'a mut W {
458        self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
459        self.w
460    }
461}
462#[doc = "Selects synchronous or asynchronous operation.\n\nValue on reset: 0"]
463#[derive(Clone, Copy, Debug, PartialEq)]
464pub enum SYNCEN_A {
465    #[doc = "0: Asynchronous mode."]
466    ASYNCHRONOUS_MODE = 0,
467    #[doc = "1: Synchronous mode."]
468    SYNCHRONOUS_MODE = 1,
469}
470impl From<SYNCEN_A> for bool {
471    #[inline(always)]
472    fn from(variant: SYNCEN_A) -> Self {
473        variant as u8 != 0
474    }
475}
476#[doc = "Field `SYNCEN` reader - Selects synchronous or asynchronous operation."]
477pub struct SYNCEN_R(crate::FieldReader<bool, SYNCEN_A>);
478impl SYNCEN_R {
479    pub(crate) fn new(bits: bool) -> Self {
480        SYNCEN_R(crate::FieldReader::new(bits))
481    }
482    #[doc = r"Get enumerated values variant"]
483    #[inline(always)]
484    pub fn variant(&self) -> SYNCEN_A {
485        match self.bits {
486            false => SYNCEN_A::ASYNCHRONOUS_MODE,
487            true => SYNCEN_A::SYNCHRONOUS_MODE,
488        }
489    }
490    #[doc = "Checks if the value of the field is `ASYNCHRONOUS_MODE`"]
491    #[inline(always)]
492    pub fn is_asynchronous_mode(&self) -> bool {
493        **self == SYNCEN_A::ASYNCHRONOUS_MODE
494    }
495    #[doc = "Checks if the value of the field is `SYNCHRONOUS_MODE`"]
496    #[inline(always)]
497    pub fn is_synchronous_mode(&self) -> bool {
498        **self == SYNCEN_A::SYNCHRONOUS_MODE
499    }
500}
501impl core::ops::Deref for SYNCEN_R {
502    type Target = crate::FieldReader<bool, SYNCEN_A>;
503    #[inline(always)]
504    fn deref(&self) -> &Self::Target {
505        &self.0
506    }
507}
508#[doc = "Field `SYNCEN` writer - Selects synchronous or asynchronous operation."]
509pub struct SYNCEN_W<'a> {
510    w: &'a mut W,
511}
512impl<'a> SYNCEN_W<'a> {
513    #[doc = r"Writes `variant` to the field"]
514    #[inline(always)]
515    pub fn variant(self, variant: SYNCEN_A) -> &'a mut W {
516        self.bit(variant.into())
517    }
518    #[doc = "Asynchronous mode."]
519    #[inline(always)]
520    pub fn asynchronous_mode(self) -> &'a mut W {
521        self.variant(SYNCEN_A::ASYNCHRONOUS_MODE)
522    }
523    #[doc = "Synchronous mode."]
524    #[inline(always)]
525    pub fn synchronous_mode(self) -> &'a mut W {
526        self.variant(SYNCEN_A::SYNCHRONOUS_MODE)
527    }
528    #[doc = r"Sets the field bit"]
529    #[inline(always)]
530    pub fn set_bit(self) -> &'a mut W {
531        self.bit(true)
532    }
533    #[doc = r"Clears the field bit"]
534    #[inline(always)]
535    pub fn clear_bit(self) -> &'a mut W {
536        self.bit(false)
537    }
538    #[doc = r"Writes raw bits to the field"]
539    #[inline(always)]
540    pub fn bit(self, value: bool) -> &'a mut W {
541        self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
542        self.w
543    }
544}
545#[doc = "Selects the clock polarity and sampling edge of received data in synchronous mode.\n\nValue on reset: 0"]
546#[derive(Clone, Copy, Debug, PartialEq)]
547pub enum CLKPOL_A {
548    #[doc = "0: Falling edge. Un_RXD is sampled on the falling edge of SCLK."]
549    FALLING_EDGE = 0,
550    #[doc = "1: Rising edge. Un_RXD is sampled on the rising edge of SCLK."]
551    RISING_EDGE = 1,
552}
553impl From<CLKPOL_A> for bool {
554    #[inline(always)]
555    fn from(variant: CLKPOL_A) -> Self {
556        variant as u8 != 0
557    }
558}
559#[doc = "Field `CLKPOL` reader - Selects the clock polarity and sampling edge of received data in synchronous mode."]
560pub struct CLKPOL_R(crate::FieldReader<bool, CLKPOL_A>);
561impl CLKPOL_R {
562    pub(crate) fn new(bits: bool) -> Self {
563        CLKPOL_R(crate::FieldReader::new(bits))
564    }
565    #[doc = r"Get enumerated values variant"]
566    #[inline(always)]
567    pub fn variant(&self) -> CLKPOL_A {
568        match self.bits {
569            false => CLKPOL_A::FALLING_EDGE,
570            true => CLKPOL_A::RISING_EDGE,
571        }
572    }
573    #[doc = "Checks if the value of the field is `FALLING_EDGE`"]
574    #[inline(always)]
575    pub fn is_falling_edge(&self) -> bool {
576        **self == CLKPOL_A::FALLING_EDGE
577    }
578    #[doc = "Checks if the value of the field is `RISING_EDGE`"]
579    #[inline(always)]
580    pub fn is_rising_edge(&self) -> bool {
581        **self == CLKPOL_A::RISING_EDGE
582    }
583}
584impl core::ops::Deref for CLKPOL_R {
585    type Target = crate::FieldReader<bool, CLKPOL_A>;
586    #[inline(always)]
587    fn deref(&self) -> &Self::Target {
588        &self.0
589    }
590}
591#[doc = "Field `CLKPOL` writer - Selects the clock polarity and sampling edge of received data in synchronous mode."]
592pub struct CLKPOL_W<'a> {
593    w: &'a mut W,
594}
595impl<'a> CLKPOL_W<'a> {
596    #[doc = r"Writes `variant` to the field"]
597    #[inline(always)]
598    pub fn variant(self, variant: CLKPOL_A) -> &'a mut W {
599        self.bit(variant.into())
600    }
601    #[doc = "Falling edge. Un_RXD is sampled on the falling edge of SCLK."]
602    #[inline(always)]
603    pub fn falling_edge(self) -> &'a mut W {
604        self.variant(CLKPOL_A::FALLING_EDGE)
605    }
606    #[doc = "Rising edge. Un_RXD is sampled on the rising edge of SCLK."]
607    #[inline(always)]
608    pub fn rising_edge(self) -> &'a mut W {
609        self.variant(CLKPOL_A::RISING_EDGE)
610    }
611    #[doc = r"Sets the field bit"]
612    #[inline(always)]
613    pub fn set_bit(self) -> &'a mut W {
614        self.bit(true)
615    }
616    #[doc = r"Clears the field bit"]
617    #[inline(always)]
618    pub fn clear_bit(self) -> &'a mut W {
619        self.bit(false)
620    }
621    #[doc = r"Writes raw bits to the field"]
622    #[inline(always)]
623    pub fn bit(self, value: bool) -> &'a mut W {
624        self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
625        self.w
626    }
627}
628#[doc = "Synchronous mode Master select.\n\nValue on reset: 0"]
629#[derive(Clone, Copy, Debug, PartialEq)]
630pub enum SYNCMST_A {
631    #[doc = "0: Slave. When synchronous mode is enabled, the USART is a slave."]
632    SLAVE = 0,
633    #[doc = "1: Master. When synchronous mode is enabled, the USART is a master."]
634    MASTER = 1,
635}
636impl From<SYNCMST_A> for bool {
637    #[inline(always)]
638    fn from(variant: SYNCMST_A) -> Self {
639        variant as u8 != 0
640    }
641}
642#[doc = "Field `SYNCMST` reader - Synchronous mode Master select."]
643pub struct SYNCMST_R(crate::FieldReader<bool, SYNCMST_A>);
644impl SYNCMST_R {
645    pub(crate) fn new(bits: bool) -> Self {
646        SYNCMST_R(crate::FieldReader::new(bits))
647    }
648    #[doc = r"Get enumerated values variant"]
649    #[inline(always)]
650    pub fn variant(&self) -> SYNCMST_A {
651        match self.bits {
652            false => SYNCMST_A::SLAVE,
653            true => SYNCMST_A::MASTER,
654        }
655    }
656    #[doc = "Checks if the value of the field is `SLAVE`"]
657    #[inline(always)]
658    pub fn is_slave(&self) -> bool {
659        **self == SYNCMST_A::SLAVE
660    }
661    #[doc = "Checks if the value of the field is `MASTER`"]
662    #[inline(always)]
663    pub fn is_master(&self) -> bool {
664        **self == SYNCMST_A::MASTER
665    }
666}
667impl core::ops::Deref for SYNCMST_R {
668    type Target = crate::FieldReader<bool, SYNCMST_A>;
669    #[inline(always)]
670    fn deref(&self) -> &Self::Target {
671        &self.0
672    }
673}
674#[doc = "Field `SYNCMST` writer - Synchronous mode Master select."]
675pub struct SYNCMST_W<'a> {
676    w: &'a mut W,
677}
678impl<'a> SYNCMST_W<'a> {
679    #[doc = r"Writes `variant` to the field"]
680    #[inline(always)]
681    pub fn variant(self, variant: SYNCMST_A) -> &'a mut W {
682        self.bit(variant.into())
683    }
684    #[doc = "Slave. When synchronous mode is enabled, the USART is a slave."]
685    #[inline(always)]
686    pub fn slave(self) -> &'a mut W {
687        self.variant(SYNCMST_A::SLAVE)
688    }
689    #[doc = "Master. When synchronous mode is enabled, the USART is a master."]
690    #[inline(always)]
691    pub fn master(self) -> &'a mut W {
692        self.variant(SYNCMST_A::MASTER)
693    }
694    #[doc = r"Sets the field bit"]
695    #[inline(always)]
696    pub fn set_bit(self) -> &'a mut W {
697        self.bit(true)
698    }
699    #[doc = r"Clears the field bit"]
700    #[inline(always)]
701    pub fn clear_bit(self) -> &'a mut W {
702        self.bit(false)
703    }
704    #[doc = r"Writes raw bits to the field"]
705    #[inline(always)]
706    pub fn bit(self, value: bool) -> &'a mut W {
707        self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14);
708        self.w
709    }
710}
711#[doc = "Selects data loopback mode.\n\nValue on reset: 0"]
712#[derive(Clone, Copy, Debug, PartialEq)]
713pub enum LOOP_A {
714    #[doc = "0: Normal operation."]
715    NORMAL = 0,
716    #[doc = "1: Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN."]
717    LOOPBACK = 1,
718}
719impl From<LOOP_A> for bool {
720    #[inline(always)]
721    fn from(variant: LOOP_A) -> Self {
722        variant as u8 != 0
723    }
724}
725#[doc = "Field `LOOP` reader - Selects data loopback mode."]
726pub struct LOOP_R(crate::FieldReader<bool, LOOP_A>);
727impl LOOP_R {
728    pub(crate) fn new(bits: bool) -> Self {
729        LOOP_R(crate::FieldReader::new(bits))
730    }
731    #[doc = r"Get enumerated values variant"]
732    #[inline(always)]
733    pub fn variant(&self) -> LOOP_A {
734        match self.bits {
735            false => LOOP_A::NORMAL,
736            true => LOOP_A::LOOPBACK,
737        }
738    }
739    #[doc = "Checks if the value of the field is `NORMAL`"]
740    #[inline(always)]
741    pub fn is_normal(&self) -> bool {
742        **self == LOOP_A::NORMAL
743    }
744    #[doc = "Checks if the value of the field is `LOOPBACK`"]
745    #[inline(always)]
746    pub fn is_loopback(&self) -> bool {
747        **self == LOOP_A::LOOPBACK
748    }
749}
750impl core::ops::Deref for LOOP_R {
751    type Target = crate::FieldReader<bool, LOOP_A>;
752    #[inline(always)]
753    fn deref(&self) -> &Self::Target {
754        &self.0
755    }
756}
757#[doc = "Field `LOOP` writer - Selects data loopback mode."]
758pub struct LOOP_W<'a> {
759    w: &'a mut W,
760}
761impl<'a> LOOP_W<'a> {
762    #[doc = r"Writes `variant` to the field"]
763    #[inline(always)]
764    pub fn variant(self, variant: LOOP_A) -> &'a mut W {
765        self.bit(variant.into())
766    }
767    #[doc = "Normal operation."]
768    #[inline(always)]
769    pub fn normal(self) -> &'a mut W {
770        self.variant(LOOP_A::NORMAL)
771    }
772    #[doc = "Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN."]
773    #[inline(always)]
774    pub fn loopback(self) -> &'a mut W {
775        self.variant(LOOP_A::LOOPBACK)
776    }
777    #[doc = r"Sets the field bit"]
778    #[inline(always)]
779    pub fn set_bit(self) -> &'a mut W {
780        self.bit(true)
781    }
782    #[doc = r"Clears the field bit"]
783    #[inline(always)]
784    pub fn clear_bit(self) -> &'a mut W {
785        self.bit(false)
786    }
787    #[doc = r"Writes raw bits to the field"]
788    #[inline(always)]
789    pub fn bit(self, value: bool) -> &'a mut W {
790        self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15);
791        self.w
792    }
793}
794#[doc = "Output Enable Turnaround time enable for RS-485 operation.\n\nValue on reset: 0"]
795#[derive(Clone, Copy, Debug, PartialEq)]
796pub enum OETA_A {
797    #[doc = "0: Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission."]
798    DISABLED = 0,
799    #[doc = "1: Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted."]
800    ENABLED = 1,
801}
802impl From<OETA_A> for bool {
803    #[inline(always)]
804    fn from(variant: OETA_A) -> Self {
805        variant as u8 != 0
806    }
807}
808#[doc = "Field `OETA` reader - Output Enable Turnaround time enable for RS-485 operation."]
809pub struct OETA_R(crate::FieldReader<bool, OETA_A>);
810impl OETA_R {
811    pub(crate) fn new(bits: bool) -> Self {
812        OETA_R(crate::FieldReader::new(bits))
813    }
814    #[doc = r"Get enumerated values variant"]
815    #[inline(always)]
816    pub fn variant(&self) -> OETA_A {
817        match self.bits {
818            false => OETA_A::DISABLED,
819            true => OETA_A::ENABLED,
820        }
821    }
822    #[doc = "Checks if the value of the field is `DISABLED`"]
823    #[inline(always)]
824    pub fn is_disabled(&self) -> bool {
825        **self == OETA_A::DISABLED
826    }
827    #[doc = "Checks if the value of the field is `ENABLED`"]
828    #[inline(always)]
829    pub fn is_enabled(&self) -> bool {
830        **self == OETA_A::ENABLED
831    }
832}
833impl core::ops::Deref for OETA_R {
834    type Target = crate::FieldReader<bool, OETA_A>;
835    #[inline(always)]
836    fn deref(&self) -> &Self::Target {
837        &self.0
838    }
839}
840#[doc = "Field `OETA` writer - Output Enable Turnaround time enable for RS-485 operation."]
841pub struct OETA_W<'a> {
842    w: &'a mut W,
843}
844impl<'a> OETA_W<'a> {
845    #[doc = r"Writes `variant` to the field"]
846    #[inline(always)]
847    pub fn variant(self, variant: OETA_A) -> &'a mut W {
848        self.bit(variant.into())
849    }
850    #[doc = "Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission."]
851    #[inline(always)]
852    pub fn disabled(self) -> &'a mut W {
853        self.variant(OETA_A::DISABLED)
854    }
855    #[doc = "Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted."]
856    #[inline(always)]
857    pub fn enabled(self) -> &'a mut W {
858        self.variant(OETA_A::ENABLED)
859    }
860    #[doc = r"Sets the field bit"]
861    #[inline(always)]
862    pub fn set_bit(self) -> &'a mut W {
863        self.bit(true)
864    }
865    #[doc = r"Clears the field bit"]
866    #[inline(always)]
867    pub fn clear_bit(self) -> &'a mut W {
868        self.bit(false)
869    }
870    #[doc = r"Writes raw bits to the field"]
871    #[inline(always)]
872    pub fn bit(self, value: bool) -> &'a mut W {
873        self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18);
874        self.w
875    }
876}
877#[doc = "Automatic Address matching enable.\n\nValue on reset: 0"]
878#[derive(Clone, Copy, Debug, PartialEq)]
879pub enum AUTOADDR_A {
880    #[doc = "0: Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address)."]
881    DISABLED = 0,
882    #[doc = "1: Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match."]
883    ENABLED = 1,
884}
885impl From<AUTOADDR_A> for bool {
886    #[inline(always)]
887    fn from(variant: AUTOADDR_A) -> Self {
888        variant as u8 != 0
889    }
890}
891#[doc = "Field `AUTOADDR` reader - Automatic Address matching enable."]
892pub struct AUTOADDR_R(crate::FieldReader<bool, AUTOADDR_A>);
893impl AUTOADDR_R {
894    pub(crate) fn new(bits: bool) -> Self {
895        AUTOADDR_R(crate::FieldReader::new(bits))
896    }
897    #[doc = r"Get enumerated values variant"]
898    #[inline(always)]
899    pub fn variant(&self) -> AUTOADDR_A {
900        match self.bits {
901            false => AUTOADDR_A::DISABLED,
902            true => AUTOADDR_A::ENABLED,
903        }
904    }
905    #[doc = "Checks if the value of the field is `DISABLED`"]
906    #[inline(always)]
907    pub fn is_disabled(&self) -> bool {
908        **self == AUTOADDR_A::DISABLED
909    }
910    #[doc = "Checks if the value of the field is `ENABLED`"]
911    #[inline(always)]
912    pub fn is_enabled(&self) -> bool {
913        **self == AUTOADDR_A::ENABLED
914    }
915}
916impl core::ops::Deref for AUTOADDR_R {
917    type Target = crate::FieldReader<bool, AUTOADDR_A>;
918    #[inline(always)]
919    fn deref(&self) -> &Self::Target {
920        &self.0
921    }
922}
923#[doc = "Field `AUTOADDR` writer - Automatic Address matching enable."]
924pub struct AUTOADDR_W<'a> {
925    w: &'a mut W,
926}
927impl<'a> AUTOADDR_W<'a> {
928    #[doc = r"Writes `variant` to the field"]
929    #[inline(always)]
930    pub fn variant(self, variant: AUTOADDR_A) -> &'a mut W {
931        self.bit(variant.into())
932    }
933    #[doc = "Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address)."]
934    #[inline(always)]
935    pub fn disabled(self) -> &'a mut W {
936        self.variant(AUTOADDR_A::DISABLED)
937    }
938    #[doc = "Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match."]
939    #[inline(always)]
940    pub fn enabled(self) -> &'a mut W {
941        self.variant(AUTOADDR_A::ENABLED)
942    }
943    #[doc = r"Sets the field bit"]
944    #[inline(always)]
945    pub fn set_bit(self) -> &'a mut W {
946        self.bit(true)
947    }
948    #[doc = r"Clears the field bit"]
949    #[inline(always)]
950    pub fn clear_bit(self) -> &'a mut W {
951        self.bit(false)
952    }
953    #[doc = r"Writes raw bits to the field"]
954    #[inline(always)]
955    pub fn bit(self, value: bool) -> &'a mut W {
956        self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19);
957        self.w
958    }
959}
960#[doc = "Output Enable Select.\n\nValue on reset: 0"]
961#[derive(Clone, Copy, Debug, PartialEq)]
962pub enum OESEL_A {
963    #[doc = "0: Standard. The RTS signal is used as the standard flow control function."]
964    STANDARD = 0,
965    #[doc = "1: RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver."]
966    RS_485 = 1,
967}
968impl From<OESEL_A> for bool {
969    #[inline(always)]
970    fn from(variant: OESEL_A) -> Self {
971        variant as u8 != 0
972    }
973}
974#[doc = "Field `OESEL` reader - Output Enable Select."]
975pub struct OESEL_R(crate::FieldReader<bool, OESEL_A>);
976impl OESEL_R {
977    pub(crate) fn new(bits: bool) -> Self {
978        OESEL_R(crate::FieldReader::new(bits))
979    }
980    #[doc = r"Get enumerated values variant"]
981    #[inline(always)]
982    pub fn variant(&self) -> OESEL_A {
983        match self.bits {
984            false => OESEL_A::STANDARD,
985            true => OESEL_A::RS_485,
986        }
987    }
988    #[doc = "Checks if the value of the field is `STANDARD`"]
989    #[inline(always)]
990    pub fn is_standard(&self) -> bool {
991        **self == OESEL_A::STANDARD
992    }
993    #[doc = "Checks if the value of the field is `RS_485`"]
994    #[inline(always)]
995    pub fn is_rs_485(&self) -> bool {
996        **self == OESEL_A::RS_485
997    }
998}
999impl core::ops::Deref for OESEL_R {
1000    type Target = crate::FieldReader<bool, OESEL_A>;
1001    #[inline(always)]
1002    fn deref(&self) -> &Self::Target {
1003        &self.0
1004    }
1005}
1006#[doc = "Field `OESEL` writer - Output Enable Select."]
1007pub struct OESEL_W<'a> {
1008    w: &'a mut W,
1009}
1010impl<'a> OESEL_W<'a> {
1011    #[doc = r"Writes `variant` to the field"]
1012    #[inline(always)]
1013    pub fn variant(self, variant: OESEL_A) -> &'a mut W {
1014        self.bit(variant.into())
1015    }
1016    #[doc = "Standard. The RTS signal is used as the standard flow control function."]
1017    #[inline(always)]
1018    pub fn standard(self) -> &'a mut W {
1019        self.variant(OESEL_A::STANDARD)
1020    }
1021    #[doc = "RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver."]
1022    #[inline(always)]
1023    pub fn rs_485(self) -> &'a mut W {
1024        self.variant(OESEL_A::RS_485)
1025    }
1026    #[doc = r"Sets the field bit"]
1027    #[inline(always)]
1028    pub fn set_bit(self) -> &'a mut W {
1029        self.bit(true)
1030    }
1031    #[doc = r"Clears the field bit"]
1032    #[inline(always)]
1033    pub fn clear_bit(self) -> &'a mut W {
1034        self.bit(false)
1035    }
1036    #[doc = r"Writes raw bits to the field"]
1037    #[inline(always)]
1038    pub fn bit(self, value: bool) -> &'a mut W {
1039        self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20);
1040        self.w
1041    }
1042}
1043#[doc = "Output Enable Polarity.\n\nValue on reset: 0"]
1044#[derive(Clone, Copy, Debug, PartialEq)]
1045pub enum OEPOL_A {
1046    #[doc = "0: Low. If selected by OESEL, the output enable is active low."]
1047    LOW = 0,
1048    #[doc = "1: High. If selected by OESEL, the output enable is active high."]
1049    HIGH = 1,
1050}
1051impl From<OEPOL_A> for bool {
1052    #[inline(always)]
1053    fn from(variant: OEPOL_A) -> Self {
1054        variant as u8 != 0
1055    }
1056}
1057#[doc = "Field `OEPOL` reader - Output Enable Polarity."]
1058pub struct OEPOL_R(crate::FieldReader<bool, OEPOL_A>);
1059impl OEPOL_R {
1060    pub(crate) fn new(bits: bool) -> Self {
1061        OEPOL_R(crate::FieldReader::new(bits))
1062    }
1063    #[doc = r"Get enumerated values variant"]
1064    #[inline(always)]
1065    pub fn variant(&self) -> OEPOL_A {
1066        match self.bits {
1067            false => OEPOL_A::LOW,
1068            true => OEPOL_A::HIGH,
1069        }
1070    }
1071    #[doc = "Checks if the value of the field is `LOW`"]
1072    #[inline(always)]
1073    pub fn is_low(&self) -> bool {
1074        **self == OEPOL_A::LOW
1075    }
1076    #[doc = "Checks if the value of the field is `HIGH`"]
1077    #[inline(always)]
1078    pub fn is_high(&self) -> bool {
1079        **self == OEPOL_A::HIGH
1080    }
1081}
1082impl core::ops::Deref for OEPOL_R {
1083    type Target = crate::FieldReader<bool, OEPOL_A>;
1084    #[inline(always)]
1085    fn deref(&self) -> &Self::Target {
1086        &self.0
1087    }
1088}
1089#[doc = "Field `OEPOL` writer - Output Enable Polarity."]
1090pub struct OEPOL_W<'a> {
1091    w: &'a mut W,
1092}
1093impl<'a> OEPOL_W<'a> {
1094    #[doc = r"Writes `variant` to the field"]
1095    #[inline(always)]
1096    pub fn variant(self, variant: OEPOL_A) -> &'a mut W {
1097        self.bit(variant.into())
1098    }
1099    #[doc = "Low. If selected by OESEL, the output enable is active low."]
1100    #[inline(always)]
1101    pub fn low(self) -> &'a mut W {
1102        self.variant(OEPOL_A::LOW)
1103    }
1104    #[doc = "High. If selected by OESEL, the output enable is active high."]
1105    #[inline(always)]
1106    pub fn high(self) -> &'a mut W {
1107        self.variant(OEPOL_A::HIGH)
1108    }
1109    #[doc = r"Sets the field bit"]
1110    #[inline(always)]
1111    pub fn set_bit(self) -> &'a mut W {
1112        self.bit(true)
1113    }
1114    #[doc = r"Clears the field bit"]
1115    #[inline(always)]
1116    pub fn clear_bit(self) -> &'a mut W {
1117        self.bit(false)
1118    }
1119    #[doc = r"Writes raw bits to the field"]
1120    #[inline(always)]
1121    pub fn bit(self, value: bool) -> &'a mut W {
1122        self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21);
1123        self.w
1124    }
1125}
1126#[doc = "Receive data polarity.\n\nValue on reset: 0"]
1127#[derive(Clone, Copy, Debug, PartialEq)]
1128pub enum RXPOL_A {
1129    #[doc = "0: Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1."]
1130    STANDARD = 0,
1131    #[doc = "1: Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0."]
1132    INVERTED = 1,
1133}
1134impl From<RXPOL_A> for bool {
1135    #[inline(always)]
1136    fn from(variant: RXPOL_A) -> Self {
1137        variant as u8 != 0
1138    }
1139}
1140#[doc = "Field `RXPOL` reader - Receive data polarity."]
1141pub struct RXPOL_R(crate::FieldReader<bool, RXPOL_A>);
1142impl RXPOL_R {
1143    pub(crate) fn new(bits: bool) -> Self {
1144        RXPOL_R(crate::FieldReader::new(bits))
1145    }
1146    #[doc = r"Get enumerated values variant"]
1147    #[inline(always)]
1148    pub fn variant(&self) -> RXPOL_A {
1149        match self.bits {
1150            false => RXPOL_A::STANDARD,
1151            true => RXPOL_A::INVERTED,
1152        }
1153    }
1154    #[doc = "Checks if the value of the field is `STANDARD`"]
1155    #[inline(always)]
1156    pub fn is_standard(&self) -> bool {
1157        **self == RXPOL_A::STANDARD
1158    }
1159    #[doc = "Checks if the value of the field is `INVERTED`"]
1160    #[inline(always)]
1161    pub fn is_inverted(&self) -> bool {
1162        **self == RXPOL_A::INVERTED
1163    }
1164}
1165impl core::ops::Deref for RXPOL_R {
1166    type Target = crate::FieldReader<bool, RXPOL_A>;
1167    #[inline(always)]
1168    fn deref(&self) -> &Self::Target {
1169        &self.0
1170    }
1171}
1172#[doc = "Field `RXPOL` writer - Receive data polarity."]
1173pub struct RXPOL_W<'a> {
1174    w: &'a mut W,
1175}
1176impl<'a> RXPOL_W<'a> {
1177    #[doc = r"Writes `variant` to the field"]
1178    #[inline(always)]
1179    pub fn variant(self, variant: RXPOL_A) -> &'a mut W {
1180        self.bit(variant.into())
1181    }
1182    #[doc = "Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1."]
1183    #[inline(always)]
1184    pub fn standard(self) -> &'a mut W {
1185        self.variant(RXPOL_A::STANDARD)
1186    }
1187    #[doc = "Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0."]
1188    #[inline(always)]
1189    pub fn inverted(self) -> &'a mut W {
1190        self.variant(RXPOL_A::INVERTED)
1191    }
1192    #[doc = r"Sets the field bit"]
1193    #[inline(always)]
1194    pub fn set_bit(self) -> &'a mut W {
1195        self.bit(true)
1196    }
1197    #[doc = r"Clears the field bit"]
1198    #[inline(always)]
1199    pub fn clear_bit(self) -> &'a mut W {
1200        self.bit(false)
1201    }
1202    #[doc = r"Writes raw bits to the field"]
1203    #[inline(always)]
1204    pub fn bit(self, value: bool) -> &'a mut W {
1205        self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22);
1206        self.w
1207    }
1208}
1209#[doc = "Transmit data polarity.\n\nValue on reset: 0"]
1210#[derive(Clone, Copy, Debug, PartialEq)]
1211pub enum TXPOL_A {
1212    #[doc = "0: Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1."]
1213    STANDARD = 0,
1214    #[doc = "1: Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0."]
1215    INVERTED = 1,
1216}
1217impl From<TXPOL_A> for bool {
1218    #[inline(always)]
1219    fn from(variant: TXPOL_A) -> Self {
1220        variant as u8 != 0
1221    }
1222}
1223#[doc = "Field `TXPOL` reader - Transmit data polarity."]
1224pub struct TXPOL_R(crate::FieldReader<bool, TXPOL_A>);
1225impl TXPOL_R {
1226    pub(crate) fn new(bits: bool) -> Self {
1227        TXPOL_R(crate::FieldReader::new(bits))
1228    }
1229    #[doc = r"Get enumerated values variant"]
1230    #[inline(always)]
1231    pub fn variant(&self) -> TXPOL_A {
1232        match self.bits {
1233            false => TXPOL_A::STANDARD,
1234            true => TXPOL_A::INVERTED,
1235        }
1236    }
1237    #[doc = "Checks if the value of the field is `STANDARD`"]
1238    #[inline(always)]
1239    pub fn is_standard(&self) -> bool {
1240        **self == TXPOL_A::STANDARD
1241    }
1242    #[doc = "Checks if the value of the field is `INVERTED`"]
1243    #[inline(always)]
1244    pub fn is_inverted(&self) -> bool {
1245        **self == TXPOL_A::INVERTED
1246    }
1247}
1248impl core::ops::Deref for TXPOL_R {
1249    type Target = crate::FieldReader<bool, TXPOL_A>;
1250    #[inline(always)]
1251    fn deref(&self) -> &Self::Target {
1252        &self.0
1253    }
1254}
1255#[doc = "Field `TXPOL` writer - Transmit data polarity."]
1256pub struct TXPOL_W<'a> {
1257    w: &'a mut W,
1258}
1259impl<'a> TXPOL_W<'a> {
1260    #[doc = r"Writes `variant` to the field"]
1261    #[inline(always)]
1262    pub fn variant(self, variant: TXPOL_A) -> &'a mut W {
1263        self.bit(variant.into())
1264    }
1265    #[doc = "Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1."]
1266    #[inline(always)]
1267    pub fn standard(self) -> &'a mut W {
1268        self.variant(TXPOL_A::STANDARD)
1269    }
1270    #[doc = "Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0."]
1271    #[inline(always)]
1272    pub fn inverted(self) -> &'a mut W {
1273        self.variant(TXPOL_A::INVERTED)
1274    }
1275    #[doc = r"Sets the field bit"]
1276    #[inline(always)]
1277    pub fn set_bit(self) -> &'a mut W {
1278        self.bit(true)
1279    }
1280    #[doc = r"Clears the field bit"]
1281    #[inline(always)]
1282    pub fn clear_bit(self) -> &'a mut W {
1283        self.bit(false)
1284    }
1285    #[doc = r"Writes raw bits to the field"]
1286    #[inline(always)]
1287    pub fn bit(self, value: bool) -> &'a mut W {
1288        self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23);
1289        self.w
1290    }
1291}
1292impl R {
1293    #[doc = "Bit 0 - USART Enable."]
1294    #[inline(always)]
1295    pub fn enable(&self) -> ENABLE_R {
1296        ENABLE_R::new((self.bits & 0x01) != 0)
1297    }
1298    #[doc = "Bits 2:3 - Selects the data size for the USART."]
1299    #[inline(always)]
1300    pub fn datalen(&self) -> DATALEN_R {
1301        DATALEN_R::new(((self.bits >> 2) & 0x03) as u8)
1302    }
1303    #[doc = "Bits 4:5 - Selects what type of parity is used by the USART."]
1304    #[inline(always)]
1305    pub fn paritysel(&self) -> PARITYSEL_R {
1306        PARITYSEL_R::new(((self.bits >> 4) & 0x03) as u8)
1307    }
1308    #[doc = "Bit 6 - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data."]
1309    #[inline(always)]
1310    pub fn stoplen(&self) -> STOPLEN_R {
1311        STOPLEN_R::new(((self.bits >> 6) & 0x01) != 0)
1312    }
1313    #[doc = "Bit 9 - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled."]
1314    #[inline(always)]
1315    pub fn ctsen(&self) -> CTSEN_R {
1316        CTSEN_R::new(((self.bits >> 9) & 0x01) != 0)
1317    }
1318    #[doc = "Bit 11 - Selects synchronous or asynchronous operation."]
1319    #[inline(always)]
1320    pub fn syncen(&self) -> SYNCEN_R {
1321        SYNCEN_R::new(((self.bits >> 11) & 0x01) != 0)
1322    }
1323    #[doc = "Bit 12 - Selects the clock polarity and sampling edge of received data in synchronous mode."]
1324    #[inline(always)]
1325    pub fn clkpol(&self) -> CLKPOL_R {
1326        CLKPOL_R::new(((self.bits >> 12) & 0x01) != 0)
1327    }
1328    #[doc = "Bit 14 - Synchronous mode Master select."]
1329    #[inline(always)]
1330    pub fn syncmst(&self) -> SYNCMST_R {
1331        SYNCMST_R::new(((self.bits >> 14) & 0x01) != 0)
1332    }
1333    #[doc = "Bit 15 - Selects data loopback mode."]
1334    #[inline(always)]
1335    pub fn loop_(&self) -> LOOP_R {
1336        LOOP_R::new(((self.bits >> 15) & 0x01) != 0)
1337    }
1338    #[doc = "Bit 18 - Output Enable Turnaround time enable for RS-485 operation."]
1339    #[inline(always)]
1340    pub fn oeta(&self) -> OETA_R {
1341        OETA_R::new(((self.bits >> 18) & 0x01) != 0)
1342    }
1343    #[doc = "Bit 19 - Automatic Address matching enable."]
1344    #[inline(always)]
1345    pub fn autoaddr(&self) -> AUTOADDR_R {
1346        AUTOADDR_R::new(((self.bits >> 19) & 0x01) != 0)
1347    }
1348    #[doc = "Bit 20 - Output Enable Select."]
1349    #[inline(always)]
1350    pub fn oesel(&self) -> OESEL_R {
1351        OESEL_R::new(((self.bits >> 20) & 0x01) != 0)
1352    }
1353    #[doc = "Bit 21 - Output Enable Polarity."]
1354    #[inline(always)]
1355    pub fn oepol(&self) -> OEPOL_R {
1356        OEPOL_R::new(((self.bits >> 21) & 0x01) != 0)
1357    }
1358    #[doc = "Bit 22 - Receive data polarity."]
1359    #[inline(always)]
1360    pub fn rxpol(&self) -> RXPOL_R {
1361        RXPOL_R::new(((self.bits >> 22) & 0x01) != 0)
1362    }
1363    #[doc = "Bit 23 - Transmit data polarity."]
1364    #[inline(always)]
1365    pub fn txpol(&self) -> TXPOL_R {
1366        TXPOL_R::new(((self.bits >> 23) & 0x01) != 0)
1367    }
1368}
1369impl W {
1370    #[doc = "Bit 0 - USART Enable."]
1371    #[inline(always)]
1372    pub fn enable(&mut self) -> ENABLE_W {
1373        ENABLE_W { w: self }
1374    }
1375    #[doc = "Bits 2:3 - Selects the data size for the USART."]
1376    #[inline(always)]
1377    pub fn datalen(&mut self) -> DATALEN_W {
1378        DATALEN_W { w: self }
1379    }
1380    #[doc = "Bits 4:5 - Selects what type of parity is used by the USART."]
1381    #[inline(always)]
1382    pub fn paritysel(&mut self) -> PARITYSEL_W {
1383        PARITYSEL_W { w: self }
1384    }
1385    #[doc = "Bit 6 - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data."]
1386    #[inline(always)]
1387    pub fn stoplen(&mut self) -> STOPLEN_W {
1388        STOPLEN_W { w: self }
1389    }
1390    #[doc = "Bit 9 - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled."]
1391    #[inline(always)]
1392    pub fn ctsen(&mut self) -> CTSEN_W {
1393        CTSEN_W { w: self }
1394    }
1395    #[doc = "Bit 11 - Selects synchronous or asynchronous operation."]
1396    #[inline(always)]
1397    pub fn syncen(&mut self) -> SYNCEN_W {
1398        SYNCEN_W { w: self }
1399    }
1400    #[doc = "Bit 12 - Selects the clock polarity and sampling edge of received data in synchronous mode."]
1401    #[inline(always)]
1402    pub fn clkpol(&mut self) -> CLKPOL_W {
1403        CLKPOL_W { w: self }
1404    }
1405    #[doc = "Bit 14 - Synchronous mode Master select."]
1406    #[inline(always)]
1407    pub fn syncmst(&mut self) -> SYNCMST_W {
1408        SYNCMST_W { w: self }
1409    }
1410    #[doc = "Bit 15 - Selects data loopback mode."]
1411    #[inline(always)]
1412    pub fn loop_(&mut self) -> LOOP_W {
1413        LOOP_W { w: self }
1414    }
1415    #[doc = "Bit 18 - Output Enable Turnaround time enable for RS-485 operation."]
1416    #[inline(always)]
1417    pub fn oeta(&mut self) -> OETA_W {
1418        OETA_W { w: self }
1419    }
1420    #[doc = "Bit 19 - Automatic Address matching enable."]
1421    #[inline(always)]
1422    pub fn autoaddr(&mut self) -> AUTOADDR_W {
1423        AUTOADDR_W { w: self }
1424    }
1425    #[doc = "Bit 20 - Output Enable Select."]
1426    #[inline(always)]
1427    pub fn oesel(&mut self) -> OESEL_W {
1428        OESEL_W { w: self }
1429    }
1430    #[doc = "Bit 21 - Output Enable Polarity."]
1431    #[inline(always)]
1432    pub fn oepol(&mut self) -> OEPOL_W {
1433        OEPOL_W { w: self }
1434    }
1435    #[doc = "Bit 22 - Receive data polarity."]
1436    #[inline(always)]
1437    pub fn rxpol(&mut self) -> RXPOL_W {
1438        RXPOL_W { w: self }
1439    }
1440    #[doc = "Bit 23 - Transmit data polarity."]
1441    #[inline(always)]
1442    pub fn txpol(&mut self) -> TXPOL_W {
1443        TXPOL_W { w: self }
1444    }
1445    #[doc = "Writes raw bits to the register."]
1446    #[inline(always)]
1447    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1448        self.0.bits(bits);
1449        self
1450    }
1451}
1452#[doc = "USART Configuration register. Basic USART configuration settings that typically are not changed during operation.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1453pub struct CFG_SPEC;
1454impl crate::RegisterSpec for CFG_SPEC {
1455    type Ux = u32;
1456}
1457#[doc = "`read()` method returns [cfg::R](R) reader structure"]
1458impl crate::Readable for CFG_SPEC {
1459    type Reader = R;
1460}
1461#[doc = "`write(|w| ..)` method takes [cfg::W](W) writer structure"]
1462impl crate::Writable for CFG_SPEC {
1463    type Writer = W;
1464}
1465#[doc = "`reset()` method sets CFG to value 0"]
1466impl crate::Resettable for CFG_SPEC {
1467    #[inline(always)]
1468    fn reset_value() -> Self::Ux {
1469        0
1470    }
1471}
lpc82x_pac/usart0/cfg.rs

lpc82x_pac/usart0/
cfg.rs
