lpc82x_pac/syscon/
wdtoscctrl.rs

1#[doc = "Register `WDTOSCCTRL` reader"]
2pub struct R(crate::R<WDTOSCCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<WDTOSCCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<WDTOSCCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<WDTOSCCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `WDTOSCCTRL` writer"]
17pub struct W(crate::W<WDTOSCCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<WDTOSCCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<WDTOSCCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<WDTOSCCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `DIVSEL` reader - Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64"]
38pub struct DIVSEL_R(crate::FieldReader<u8, u8>);
39impl DIVSEL_R {
40    pub(crate) fn new(bits: u8) -> Self {
41        DIVSEL_R(crate::FieldReader::new(bits))
42    }
43}
44impl core::ops::Deref for DIVSEL_R {
45    type Target = crate::FieldReader<u8, u8>;
46    #[inline(always)]
47    fn deref(&self) -> &Self::Target {
48        &self.0
49    }
50}
51#[doc = "Field `DIVSEL` writer - Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64"]
52pub struct DIVSEL_W<'a> {
53    w: &'a mut W,
54}
55impl<'a> DIVSEL_W<'a> {
56    #[doc = r"Writes raw bits to the field"]
57    #[inline(always)]
58    pub unsafe fn bits(self, value: u8) -> &'a mut W {
59        self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f);
60        self.w
61    }
62}
63#[doc = "Field `FREQSEL` reader - Frequency select. Selects the frequency of the oscillator. 0x00 = invalid setting when watchdog oscillator is running 0x1 = 0.6 MHz 0x2 = 1.05 MHz 0x3 = 1.4 MHz 0x4 = 1.75 MHz 0x5 = 2.1 MHz 0x6 = 2.4 MHz 0x7 = 2.7 MHz 0x8 = 3.0 MHz 0x9 = 3.25 MHz 0xA = 3.5 MHz 0xB = 3.75 MHz 0xC = 4.0 MHz 0xD = 4.2 MHz 0xE = 4.4 MHz 0xF = 4.6 MHz"]
64pub struct FREQSEL_R(crate::FieldReader<u8, u8>);
65impl FREQSEL_R {
66    pub(crate) fn new(bits: u8) -> Self {
67        FREQSEL_R(crate::FieldReader::new(bits))
68    }
69}
70impl core::ops::Deref for FREQSEL_R {
71    type Target = crate::FieldReader<u8, u8>;
72    #[inline(always)]
73    fn deref(&self) -> &Self::Target {
74        &self.0
75    }
76}
77#[doc = "Field `FREQSEL` writer - Frequency select. Selects the frequency of the oscillator. 0x00 = invalid setting when watchdog oscillator is running 0x1 = 0.6 MHz 0x2 = 1.05 MHz 0x3 = 1.4 MHz 0x4 = 1.75 MHz 0x5 = 2.1 MHz 0x6 = 2.4 MHz 0x7 = 2.7 MHz 0x8 = 3.0 MHz 0x9 = 3.25 MHz 0xA = 3.5 MHz 0xB = 3.75 MHz 0xC = 4.0 MHz 0xD = 4.2 MHz 0xE = 4.4 MHz 0xF = 4.6 MHz"]
78pub struct FREQSEL_W<'a> {
79    w: &'a mut W,
80}
81impl<'a> FREQSEL_W<'a> {
82    #[doc = r"Writes raw bits to the field"]
83    #[inline(always)]
84    pub unsafe fn bits(self, value: u8) -> &'a mut W {
85        self.w.bits = (self.w.bits & !(0x0f << 5)) | ((value as u32 & 0x0f) << 5);
86        self.w
87    }
88}
89impl R {
90    #[doc = "Bits 0:4 - Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64"]
91    #[inline(always)]
92    pub fn divsel(&self) -> DIVSEL_R {
93        DIVSEL_R::new((self.bits & 0x1f) as u8)
94    }
95    #[doc = "Bits 5:8 - Frequency select. Selects the frequency of the oscillator. 0x00 = invalid setting when watchdog oscillator is running 0x1 = 0.6 MHz 0x2 = 1.05 MHz 0x3 = 1.4 MHz 0x4 = 1.75 MHz 0x5 = 2.1 MHz 0x6 = 2.4 MHz 0x7 = 2.7 MHz 0x8 = 3.0 MHz 0x9 = 3.25 MHz 0xA = 3.5 MHz 0xB = 3.75 MHz 0xC = 4.0 MHz 0xD = 4.2 MHz 0xE = 4.4 MHz 0xF = 4.6 MHz"]
96    #[inline(always)]
97    pub fn freqsel(&self) -> FREQSEL_R {
98        FREQSEL_R::new(((self.bits >> 5) & 0x0f) as u8)
99    }
100}
101impl W {
102    #[doc = "Bits 0:4 - Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64"]
103    #[inline(always)]
104    pub fn divsel(&mut self) -> DIVSEL_W {
105        DIVSEL_W { w: self }
106    }
107    #[doc = "Bits 5:8 - Frequency select. Selects the frequency of the oscillator. 0x00 = invalid setting when watchdog oscillator is running 0x1 = 0.6 MHz 0x2 = 1.05 MHz 0x3 = 1.4 MHz 0x4 = 1.75 MHz 0x5 = 2.1 MHz 0x6 = 2.4 MHz 0x7 = 2.7 MHz 0x8 = 3.0 MHz 0x9 = 3.25 MHz 0xA = 3.5 MHz 0xB = 3.75 MHz 0xC = 4.0 MHz 0xD = 4.2 MHz 0xE = 4.4 MHz 0xF = 4.6 MHz"]
108    #[inline(always)]
109    pub fn freqsel(&mut self) -> FREQSEL_W {
110        FREQSEL_W { w: self }
111    }
112    #[doc = "Writes raw bits to the register."]
113    #[inline(always)]
114    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
115        self.0.bits(bits);
116        self
117    }
118}
119#[doc = "Watchdog oscillator control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wdtoscctrl](index.html) module"]
120pub struct WDTOSCCTRL_SPEC;
121impl crate::RegisterSpec for WDTOSCCTRL_SPEC {
122    type Ux = u32;
123}
124#[doc = "`read()` method returns [wdtoscctrl::R](R) reader structure"]
125impl crate::Readable for WDTOSCCTRL_SPEC {
126    type Reader = R;
127}
128#[doc = "`write(|w| ..)` method takes [wdtoscctrl::W](W) writer structure"]
129impl crate::Writable for WDTOSCCTRL_SPEC {
130    type Writer = W;
131}
132#[doc = "`reset()` method sets WDTOSCCTRL to value 0"]
133impl crate::Resettable for WDTOSCCTRL_SPEC {
134    #[inline(always)]
135    fn reset_value() -> Self::Ux {
136        0
137    }
138}
lpc82x_pac/syscon/wdtoscctrl.rs

lpc82x_pac/syscon/
wdtoscctrl.rs
