lpc82x_pac/syscon/
nmisrc.rs

1#[doc = "Register `NMISRC` reader"]
2pub struct R(crate::R<NMISRC_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<NMISRC_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<NMISRC_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<NMISRC_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `NMISRC` writer"]
17pub struct W(crate::W<NMISRC_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<NMISRC_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<NMISRC_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<NMISRC_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `IRQN` reader - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1"]
38pub struct IRQN_R(crate::FieldReader<u8, u8>);
39impl IRQN_R {
40    pub(crate) fn new(bits: u8) -> Self {
41        IRQN_R(crate::FieldReader::new(bits))
42    }
43}
44impl core::ops::Deref for IRQN_R {
45    type Target = crate::FieldReader<u8, u8>;
46    #[inline(always)]
47    fn deref(&self) -> &Self::Target {
48        &self.0
49    }
50}
51#[doc = "Field `IRQN` writer - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1"]
52pub struct IRQN_W<'a> {
53    w: &'a mut W,
54}
55impl<'a> IRQN_W<'a> {
56    #[doc = r"Writes raw bits to the field"]
57    #[inline(always)]
58    pub unsafe fn bits(self, value: u8) -> &'a mut W {
59        self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f);
60        self.w
61    }
62}
63#[doc = "Field `NMIEN` reader - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0."]
64pub struct NMIEN_R(crate::FieldReader<bool, bool>);
65impl NMIEN_R {
66    pub(crate) fn new(bits: bool) -> Self {
67        NMIEN_R(crate::FieldReader::new(bits))
68    }
69}
70impl core::ops::Deref for NMIEN_R {
71    type Target = crate::FieldReader<bool, bool>;
72    #[inline(always)]
73    fn deref(&self) -> &Self::Target {
74        &self.0
75    }
76}
77#[doc = "Field `NMIEN` writer - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0."]
78pub struct NMIEN_W<'a> {
79    w: &'a mut W,
80}
81impl<'a> NMIEN_W<'a> {
82    #[doc = r"Sets the field bit"]
83    #[inline(always)]
84    pub fn set_bit(self) -> &'a mut W {
85        self.bit(true)
86    }
87    #[doc = r"Clears the field bit"]
88    #[inline(always)]
89    pub fn clear_bit(self) -> &'a mut W {
90        self.bit(false)
91    }
92    #[doc = r"Writes raw bits to the field"]
93    #[inline(always)]
94    pub fn bit(self, value: bool) -> &'a mut W {
95        self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
96        self.w
97    }
98}
99impl R {
100    #[doc = "Bits 0:4 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1"]
101    #[inline(always)]
102    pub fn irqn(&self) -> IRQN_R {
103        IRQN_R::new((self.bits & 0x1f) as u8)
104    }
105    #[doc = "Bit 31 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0."]
106    #[inline(always)]
107    pub fn nmien(&self) -> NMIEN_R {
108        NMIEN_R::new(((self.bits >> 31) & 0x01) != 0)
109    }
110}
111impl W {
112    #[doc = "Bits 0:4 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1"]
113    #[inline(always)]
114    pub fn irqn(&mut self) -> IRQN_W {
115        IRQN_W { w: self }
116    }
117    #[doc = "Bit 31 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0."]
118    #[inline(always)]
119    pub fn nmien(&mut self) -> NMIEN_W {
120        NMIEN_W { w: self }
121    }
122    #[doc = "Writes raw bits to the register."]
123    #[inline(always)]
124    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
125        self.0.bits(bits);
126        self
127    }
128}
129#[doc = "NMI source selection register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmisrc](index.html) module"]
130pub struct NMISRC_SPEC;
131impl crate::RegisterSpec for NMISRC_SPEC {
132    type Ux = u32;
133}
134#[doc = "`read()` method returns [nmisrc::R](R) reader structure"]
135impl crate::Readable for NMISRC_SPEC {
136    type Reader = R;
137}
138#[doc = "`write(|w| ..)` method takes [nmisrc::W](W) writer structure"]
139impl crate::Writable for NMISRC_SPEC {
140    type Writer = W;
141}
142#[doc = "`reset()` method sets NMISRC to value 0"]
143impl crate::Resettable for NMISRC_SPEC {
144    #[inline(always)]
145    fn reset_value() -> Self::Ux {
146        0
147    }
148}
lpc82x_pac/syscon/nmisrc.rs

lpc82x_pac/syscon/
nmisrc.rs
