lpc82x_pac/syscon/
mainclksel.rs

1#[doc = "Register `MAINCLKSEL` reader"]
2pub struct R(crate::R<MAINCLKSEL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<MAINCLKSEL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<MAINCLKSEL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<MAINCLKSEL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `MAINCLKSEL` writer"]
17pub struct W(crate::W<MAINCLKSEL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<MAINCLKSEL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<MAINCLKSEL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<MAINCLKSEL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Clock source for main clock.\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum SEL_A {
41    #[doc = "0: IRC Oscillator."]
42    IRC_OSC = 0,
43    #[doc = "1: PLL input."]
44    PLL_IN = 1,
45    #[doc = "2: Watchdog oscillator."]
46    WDTOSC = 2,
47    #[doc = "3: PLL output."]
48    PLL_OUT = 3,
49}
50impl From<SEL_A> for u8 {
51    #[inline(always)]
52    fn from(variant: SEL_A) -> Self {
53        variant as _
54    }
55}
56#[doc = "Field `SEL` reader - Clock source for main clock."]
57pub struct SEL_R(crate::FieldReader<u8, SEL_A>);
58impl SEL_R {
59    pub(crate) fn new(bits: u8) -> Self {
60        SEL_R(crate::FieldReader::new(bits))
61    }
62    #[doc = r"Get enumerated values variant"]
63    #[inline(always)]
64    pub fn variant(&self) -> SEL_A {
65        match self.bits {
66            0 => SEL_A::IRC_OSC,
67            1 => SEL_A::PLL_IN,
68            2 => SEL_A::WDTOSC,
69            3 => SEL_A::PLL_OUT,
70            _ => unreachable!(),
71        }
72    }
73    #[doc = "Checks if the value of the field is `IRC_OSC`"]
74    #[inline(always)]
75    pub fn is_irc_osc(&self) -> bool {
76        **self == SEL_A::IRC_OSC
77    }
78    #[doc = "Checks if the value of the field is `PLL_IN`"]
79    #[inline(always)]
80    pub fn is_pll_in(&self) -> bool {
81        **self == SEL_A::PLL_IN
82    }
83    #[doc = "Checks if the value of the field is `WDTOSC`"]
84    #[inline(always)]
85    pub fn is_wdtosc(&self) -> bool {
86        **self == SEL_A::WDTOSC
87    }
88    #[doc = "Checks if the value of the field is `PLL_OUT`"]
89    #[inline(always)]
90    pub fn is_pll_out(&self) -> bool {
91        **self == SEL_A::PLL_OUT
92    }
93}
94impl core::ops::Deref for SEL_R {
95    type Target = crate::FieldReader<u8, SEL_A>;
96    #[inline(always)]
97    fn deref(&self) -> &Self::Target {
98        &self.0
99    }
100}
101#[doc = "Field `SEL` writer - Clock source for main clock."]
102pub struct SEL_W<'a> {
103    w: &'a mut W,
104}
105impl<'a> SEL_W<'a> {
106    #[doc = r"Writes `variant` to the field"]
107    #[inline(always)]
108    pub fn variant(self, variant: SEL_A) -> &'a mut W {
109        self.bits(variant.into())
110    }
111    #[doc = "IRC Oscillator."]
112    #[inline(always)]
113    pub fn irc_osc(self) -> &'a mut W {
114        self.variant(SEL_A::IRC_OSC)
115    }
116    #[doc = "PLL input."]
117    #[inline(always)]
118    pub fn pll_in(self) -> &'a mut W {
119        self.variant(SEL_A::PLL_IN)
120    }
121    #[doc = "Watchdog oscillator."]
122    #[inline(always)]
123    pub fn wdtosc(self) -> &'a mut W {
124        self.variant(SEL_A::WDTOSC)
125    }
126    #[doc = "PLL output."]
127    #[inline(always)]
128    pub fn pll_out(self) -> &'a mut W {
129        self.variant(SEL_A::PLL_OUT)
130    }
131    #[doc = r"Writes raw bits to the field"]
132    #[inline(always)]
133    pub fn bits(self, value: u8) -> &'a mut W {
134        self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03);
135        self.w
136    }
137}
138impl R {
139    #[doc = "Bits 0:1 - Clock source for main clock."]
140    #[inline(always)]
141    pub fn sel(&self) -> SEL_R {
142        SEL_R::new((self.bits & 0x03) as u8)
143    }
144}
145impl W {
146    #[doc = "Bits 0:1 - Clock source for main clock."]
147    #[inline(always)]
148    pub fn sel(&mut self) -> SEL_W {
149        SEL_W { w: self }
150    }
151    #[doc = "Writes raw bits to the register."]
152    #[inline(always)]
153    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
154        self.0.bits(bits);
155        self
156    }
157}
158#[doc = "Main clock source select\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mainclksel](index.html) module"]
159pub struct MAINCLKSEL_SPEC;
160impl crate::RegisterSpec for MAINCLKSEL_SPEC {
161    type Ux = u32;
162}
163#[doc = "`read()` method returns [mainclksel::R](R) reader structure"]
164impl crate::Readable for MAINCLKSEL_SPEC {
165    type Reader = R;
166}
167#[doc = "`write(|w| ..)` method takes [mainclksel::W](W) writer structure"]
168impl crate::Writable for MAINCLKSEL_SPEC {
169    type Writer = W;
170}
171#[doc = "`reset()` method sets MAINCLKSEL to value 0"]
172impl crate::Resettable for MAINCLKSEL_SPEC {
173    #[inline(always)]
174    fn reset_value() -> Self::Ux {
175        0
176    }
177}
lpc82x_pac/syscon/mainclksel.rs

lpc82x_pac/syscon/
mainclksel.rs
