lpc82x_pac/syscon/
ioconclkdiv0.rs

1#[doc = "Register `IOCONCLKDIV0` reader"]
2pub struct R(crate::R<IOCONCLKDIV0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<IOCONCLKDIV0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<IOCONCLKDIV0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<IOCONCLKDIV0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `IOCONCLKDIV0` writer"]
17pub struct W(crate::W<IOCONCLKDIV0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<IOCONCLKDIV0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<IOCONCLKDIV0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<IOCONCLKDIV0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `DIV` reader - IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255."]
38pub struct DIV_R(crate::FieldReader<u8, u8>);
39impl DIV_R {
40    pub(crate) fn new(bits: u8) -> Self {
41        DIV_R(crate::FieldReader::new(bits))
42    }
43}
44impl core::ops::Deref for DIV_R {
45    type Target = crate::FieldReader<u8, u8>;
46    #[inline(always)]
47    fn deref(&self) -> &Self::Target {
48        &self.0
49    }
50}
51#[doc = "Field `DIV` writer - IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255."]
52pub struct DIV_W<'a> {
53    w: &'a mut W,
54}
55impl<'a> DIV_W<'a> {
56    #[doc = r"Writes raw bits to the field"]
57    #[inline(always)]
58    pub unsafe fn bits(self, value: u8) -> &'a mut W {
59        self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff);
60        self.w
61    }
62}
63impl R {
64    #[doc = "Bits 0:7 - IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255."]
65    #[inline(always)]
66    pub fn div(&self) -> DIV_R {
67        DIV_R::new((self.bits & 0xff) as u8)
68    }
69}
70impl W {
71    #[doc = "Bits 0:7 - IOCON glitch filter clock divider values 0: Disable IOCONFILTR_PCLK. 1: Divide by 1. to 255: Divide by 255."]
72    #[inline(always)]
73    pub fn div(&mut self) -> DIV_W {
74        DIV_W { w: self }
75    }
76    #[doc = "Writes raw bits to the register."]
77    #[inline(always)]
78    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
79        self.0.bits(bits);
80        self
81    }
82}
83#[doc = "Peripheral clock 0 to the IOCON block for programmable glitch filter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ioconclkdiv0](index.html) module"]
84pub struct IOCONCLKDIV0_SPEC;
85impl crate::RegisterSpec for IOCONCLKDIV0_SPEC {
86    type Ux = u32;
87}
88#[doc = "`read()` method returns [ioconclkdiv0::R](R) reader structure"]
89impl crate::Readable for IOCONCLKDIV0_SPEC {
90    type Reader = R;
91}
92#[doc = "`write(|w| ..)` method takes [ioconclkdiv0::W](W) writer structure"]
93impl crate::Writable for IOCONCLKDIV0_SPEC {
94    type Writer = W;
95}
96#[doc = "`reset()` method sets IOCONCLKDIV0 to value 0"]
97impl crate::Resettable for IOCONCLKDIV0_SPEC {
98    #[inline(always)]
99    fn reset_value() -> Self::Ux {
100        0
101    }
102}
lpc82x_pac/syscon/ioconclkdiv0.rs

lpc82x_pac/syscon/
ioconclkdiv0.rs
