1#[doc = "Register `STAT` reader"]
2pub struct R(crate::R<STAT_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<STAT_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<STAT_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<STAT_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `STAT` writer"]
17pub struct W(crate::W<STAT_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<STAT_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<STAT_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<STAT_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `RXRDY` reader - Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register."]
38pub struct RXRDY_R(crate::FieldReader<bool, bool>);
39impl RXRDY_R {
40 pub(crate) fn new(bits: bool) -> Self {
41 RXRDY_R(crate::FieldReader::new(bits))
42 }
43}
44impl core::ops::Deref for RXRDY_R {
45 type Target = crate::FieldReader<bool, bool>;
46 #[inline(always)]
47 fn deref(&self) -> &Self::Target {
48 &self.0
49 }
50}
51#[doc = "Field `TXRDY` reader - Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register."]
52pub struct TXRDY_R(crate::FieldReader<bool, bool>);
53impl TXRDY_R {
54 pub(crate) fn new(bits: bool) -> Self {
55 TXRDY_R(crate::FieldReader::new(bits))
56 }
57}
58impl core::ops::Deref for TXRDY_R {
59 type Target = crate::FieldReader<bool, bool>;
60 #[inline(always)]
61 fn deref(&self) -> &Self::Target {
62 &self.0
63 }
64}
65#[doc = "Field `RXOV` writer - Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs, the receiver buffer contents are preserved, and the incoming data is lost. Data received by the SPI should be considered undefined if RxOv is set."]
66pub struct RXOV_W<'a> {
67 w: &'a mut W,
68}
69impl<'a> RXOV_W<'a> {
70 #[doc = r"Sets the field bit"]
71 #[inline(always)]
72 pub fn set_bit(self) -> &'a mut W {
73 self.bit(true)
74 }
75 #[doc = r"Clears the field bit"]
76 #[inline(always)]
77 pub fn clear_bit(self) -> &'a mut W {
78 self.bit(false)
79 }
80 #[doc = r"Writes raw bits to the field"]
81 #[inline(always)]
82 pub fn bit(self, value: bool) -> &'a mut W {
83 self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
84 self.w
85 }
86}
87#[doc = "Field `TXUR` writer - Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case, the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter holding register at that point, there is no data to transmit and the TXUR flag is set. Data transmitted by the SPI should be considered undefined if TXUR is set."]
88pub struct TXUR_W<'a> {
89 w: &'a mut W,
90}
91impl<'a> TXUR_W<'a> {
92 #[doc = r"Sets the field bit"]
93 #[inline(always)]
94 pub fn set_bit(self) -> &'a mut W {
95 self.bit(true)
96 }
97 #[doc = r"Clears the field bit"]
98 #[inline(always)]
99 pub fn clear_bit(self) -> &'a mut W {
100 self.bit(false)
101 }
102 #[doc = r"Writes raw bits to the field"]
103 #[inline(always)]
104 pub fn bit(self, value: bool) -> &'a mut W {
105 self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
106 self.w
107 }
108}
109#[doc = "Field `SSA` writer - Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software."]
110pub struct SSA_W<'a> {
111 w: &'a mut W,
112}
113impl<'a> SSA_W<'a> {
114 #[doc = r"Sets the field bit"]
115 #[inline(always)]
116 pub fn set_bit(self) -> &'a mut W {
117 self.bit(true)
118 }
119 #[doc = r"Clears the field bit"]
120 #[inline(always)]
121 pub fn clear_bit(self) -> &'a mut W {
122 self.bit(false)
123 }
124 #[doc = r"Writes raw bits to the field"]
125 #[inline(always)]
126 pub fn bit(self, value: bool) -> &'a mut W {
127 self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
128 self.w
129 }
130}
131#[doc = "Field `SSD` writer - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software."]
132pub struct SSD_W<'a> {
133 w: &'a mut W,
134}
135impl<'a> SSD_W<'a> {
136 #[doc = r"Sets the field bit"]
137 #[inline(always)]
138 pub fn set_bit(self) -> &'a mut W {
139 self.bit(true)
140 }
141 #[doc = r"Clears the field bit"]
142 #[inline(always)]
143 pub fn clear_bit(self) -> &'a mut W {
144 self.bit(false)
145 }
146 #[doc = r"Writes raw bits to the field"]
147 #[inline(always)]
148 pub fn bit(self, value: bool) -> &'a mut W {
149 self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
150 self.w
151 }
152}
153#[doc = "Field `STALLED` reader - Stalled status flag. This indicates whether the SPI is currently in a stall condition."]
154pub struct STALLED_R(crate::FieldReader<bool, bool>);
155impl STALLED_R {
156 pub(crate) fn new(bits: bool) -> Self {
157 STALLED_R(crate::FieldReader::new(bits))
158 }
159}
160impl core::ops::Deref for STALLED_R {
161 type Target = crate::FieldReader<bool, bool>;
162 #[inline(always)]
163 fn deref(&self) -> &Self::Target {
164 &self.0
165 }
166}
167#[doc = "Field `ENDTRANSFER` reader - End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted."]
168pub struct ENDTRANSFER_R(crate::FieldReader<bool, bool>);
169impl ENDTRANSFER_R {
170 pub(crate) fn new(bits: bool) -> Self {
171 ENDTRANSFER_R(crate::FieldReader::new(bits))
172 }
173}
174impl core::ops::Deref for ENDTRANSFER_R {
175 type Target = crate::FieldReader<bool, bool>;
176 #[inline(always)]
177 fn deref(&self) -> &Self::Target {
178 &self.0
179 }
180}
181#[doc = "Field `ENDTRANSFER` writer - End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted."]
182pub struct ENDTRANSFER_W<'a> {
183 w: &'a mut W,
184}
185impl<'a> ENDTRANSFER_W<'a> {
186 #[doc = r"Sets the field bit"]
187 #[inline(always)]
188 pub fn set_bit(self) -> &'a mut W {
189 self.bit(true)
190 }
191 #[doc = r"Clears the field bit"]
192 #[inline(always)]
193 pub fn clear_bit(self) -> &'a mut W {
194 self.bit(false)
195 }
196 #[doc = r"Writes raw bits to the field"]
197 #[inline(always)]
198 pub fn bit(self, value: bool) -> &'a mut W {
199 self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
200 self.w
201 }
202}
203#[doc = "Field `MSTIDLE` reader - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data."]
204pub struct MSTIDLE_R(crate::FieldReader<bool, bool>);
205impl MSTIDLE_R {
206 pub(crate) fn new(bits: bool) -> Self {
207 MSTIDLE_R(crate::FieldReader::new(bits))
208 }
209}
210impl core::ops::Deref for MSTIDLE_R {
211 type Target = crate::FieldReader<bool, bool>;
212 #[inline(always)]
213 fn deref(&self) -> &Self::Target {
214 &self.0
215 }
216}
217impl R {
218 #[doc = "Bit 0 - Receiver Ready flag. When 1, indicates that data is available to be read from the receiver buffer. Cleared after a read of the RXDAT register."]
219 #[inline(always)]
220 pub fn rxrdy(&self) -> RXRDY_R {
221 RXRDY_R::new((self.bits & 0x01) != 0)
222 }
223 #[doc = "Bit 1 - Transmitter Ready flag. When 1, this bit indicates that data may be written to the transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register."]
224 #[inline(always)]
225 pub fn txrdy(&self) -> TXRDY_R {
226 TXRDY_R::new(((self.bits >> 1) & 0x01) != 0)
227 }
228 #[doc = "Bit 6 - Stalled status flag. This indicates whether the SPI is currently in a stall condition."]
229 #[inline(always)]
230 pub fn stalled(&self) -> STALLED_R {
231 STALLED_R::new(((self.bits >> 6) & 0x01) != 0)
232 }
233 #[doc = "Bit 7 - End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted."]
234 #[inline(always)]
235 pub fn endtransfer(&self) -> ENDTRANSFER_R {
236 ENDTRANSFER_R::new(((self.bits >> 7) & 0x01) != 0)
237 }
238 #[doc = "Bit 8 - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This means that the transmit holding register is empty and the transmitter is not in the process of sending data."]
239 #[inline(always)]
240 pub fn mstidle(&self) -> MSTIDLE_R {
241 MSTIDLE_R::new(((self.bits >> 8) & 0x01) != 0)
242 }
243}
244impl W {
245 #[doc = "Bit 2 - Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This flag is set when the beginning of a received character is detected while the receiver buffer is still in use. If this occurs, the receiver buffer contents are preserved, and the incoming data is lost. Data received by the SPI should be considered undefined if RxOv is set."]
246 #[inline(always)]
247 pub fn rxov(&mut self) -> RXOV_W {
248 RXOV_W { w: self }
249 }
250 #[doc = "Bit 3 - Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). In this case, the transmitter must begin sending new data on the next input clock if the transmitter is idle. If that data is not available in the transmitter holding register at that point, there is no data to transmit and the TXUR flag is set. Data transmitted by the SPI should be considered undefined if TXUR is set."]
251 #[inline(always)]
252 pub fn txur(&mut self) -> TXUR_W {
253 TXUR_W { w: self }
254 }
255 #[doc = "Bit 4 - Slave Select Assert. This flag is set whenever any slave select transitions from deasserted to asserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become busy, and allows waking up the device from reduced power modes when a slave mode access begins. This flag is cleared by software."]
256 #[inline(always)]
257 pub fn ssa(&mut self) -> SSA_W {
258 SSA_W { w: self }
259 }
260 #[doc = "Bit 5 - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to deasserted, in both master and slave modes. This allows determining when the SPI transmit/receive functions become idle. This flag is cleared by software."]
261 #[inline(always)]
262 pub fn ssd(&mut self) -> SSD_W {
263 SSD_W { w: self }
264 }
265 #[doc = "Bit 7 - End Transfer control bit. Software can set this bit to force an end to the current transfer when the transmitter finishes any activity already in progress, as if the EOT flag had been set prior to the last transmission. This capability is included to support cases where it is not known when transmit data is written that it will be the end of a transfer. The bit is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted."]
266 #[inline(always)]
267 pub fn endtransfer(&mut self) -> ENDTRANSFER_W {
268 ENDTRANSFER_W { w: self }
269 }
270 #[doc = "Writes raw bits to the register."]
271 #[inline(always)]
272 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
273 self.0.bits(bits);
274 self
275 }
276}
277#[doc = "SPI Status. Some status flags can be cleared by writing a 1 to that bit position\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stat](index.html) module"]
278pub struct STAT_SPEC;
279impl crate::RegisterSpec for STAT_SPEC {
280 type Ux = u32;
281}
282#[doc = "`read()` method returns [stat::R](R) reader structure"]
283impl crate::Readable for STAT_SPEC {
284 type Reader = R;
285}
286#[doc = "`write(|w| ..)` method takes [stat::W](W) writer structure"]
287impl crate::Writable for STAT_SPEC {
288 type Writer = W;
289}
290#[doc = "`reset()` method sets STAT to value 0x0102"]
291impl crate::Resettable for STAT_SPEC {
292 #[inline(always)]
293 fn reset_value() -> Self::Ux {
294 0x0102
295 }
296}