lpc82x_pac/spi0/
intenset.rs

1#[doc = "Register `INTENSET` reader"]
2pub struct R(crate::R<INTENSET_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<INTENSET_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<INTENSET_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<INTENSET_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `INTENSET` writer"]
17pub struct W(crate::W<INTENSET_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<INTENSET_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<INTENSET_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<INTENSET_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Determines whether an interrupt occurs when receiver data is available.\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum RXRDYEN_A {
40    #[doc = "0: No interrupt will be generated when receiver data is available."]
41    RXRDYEN_0 = 0,
42    #[doc = "1: An interrupt will be generated when receiver data is available in the RXDAT register."]
43    RXRDYEN_1 = 1,
44}
45impl From<RXRDYEN_A> for bool {
46    #[inline(always)]
47    fn from(variant: RXRDYEN_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `RXRDYEN` reader - Determines whether an interrupt occurs when receiver data is available."]
52pub struct RXRDYEN_R(crate::FieldReader<bool, RXRDYEN_A>);
53impl RXRDYEN_R {
54    pub(crate) fn new(bits: bool) -> Self {
55        RXRDYEN_R(crate::FieldReader::new(bits))
56    }
57    #[doc = r"Get enumerated values variant"]
58    #[inline(always)]
59    pub fn variant(&self) -> RXRDYEN_A {
60        match self.bits {
61            false => RXRDYEN_A::RXRDYEN_0,
62            true => RXRDYEN_A::RXRDYEN_1,
63        }
64    }
65    #[doc = "Checks if the value of the field is `RXRDYEN_0`"]
66    #[inline(always)]
67    pub fn is_rxrdyen_0(&self) -> bool {
68        **self == RXRDYEN_A::RXRDYEN_0
69    }
70    #[doc = "Checks if the value of the field is `RXRDYEN_1`"]
71    #[inline(always)]
72    pub fn is_rxrdyen_1(&self) -> bool {
73        **self == RXRDYEN_A::RXRDYEN_1
74    }
75}
76impl core::ops::Deref for RXRDYEN_R {
77    type Target = crate::FieldReader<bool, RXRDYEN_A>;
78    #[inline(always)]
79    fn deref(&self) -> &Self::Target {
80        &self.0
81    }
82}
83#[doc = "Field `RXRDYEN` writer - Determines whether an interrupt occurs when receiver data is available."]
84pub struct RXRDYEN_W<'a> {
85    w: &'a mut W,
86}
87impl<'a> RXRDYEN_W<'a> {
88    #[doc = r"Writes `variant` to the field"]
89    #[inline(always)]
90    pub fn variant(self, variant: RXRDYEN_A) -> &'a mut W {
91        self.bit(variant.into())
92    }
93    #[doc = "No interrupt will be generated when receiver data is available."]
94    #[inline(always)]
95    pub fn rxrdyen_0(self) -> &'a mut W {
96        self.variant(RXRDYEN_A::RXRDYEN_0)
97    }
98    #[doc = "An interrupt will be generated when receiver data is available in the RXDAT register."]
99    #[inline(always)]
100    pub fn rxrdyen_1(self) -> &'a mut W {
101        self.variant(RXRDYEN_A::RXRDYEN_1)
102    }
103    #[doc = r"Sets the field bit"]
104    #[inline(always)]
105    pub fn set_bit(self) -> &'a mut W {
106        self.bit(true)
107    }
108    #[doc = r"Clears the field bit"]
109    #[inline(always)]
110    pub fn clear_bit(self) -> &'a mut W {
111        self.bit(false)
112    }
113    #[doc = r"Writes raw bits to the field"]
114    #[inline(always)]
115    pub fn bit(self, value: bool) -> &'a mut W {
116        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
117        self.w
118    }
119}
120#[doc = "Determines whether an interrupt occurs when the transmitter holding register is available.\n\nValue on reset: 0"]
121#[derive(Clone, Copy, Debug, PartialEq)]
122pub enum TXRDYEN_A {
123    #[doc = "0: No interrupt will be generated when the transmitter holding register is available."]
124    TXRDYEN_0 = 0,
125    #[doc = "1: An interrupt will be generated when data may be written to TXDAT."]
126    TXRDYEN_1 = 1,
127}
128impl From<TXRDYEN_A> for bool {
129    #[inline(always)]
130    fn from(variant: TXRDYEN_A) -> Self {
131        variant as u8 != 0
132    }
133}
134#[doc = "Field `TXRDYEN` reader - Determines whether an interrupt occurs when the transmitter holding register is available."]
135pub struct TXRDYEN_R(crate::FieldReader<bool, TXRDYEN_A>);
136impl TXRDYEN_R {
137    pub(crate) fn new(bits: bool) -> Self {
138        TXRDYEN_R(crate::FieldReader::new(bits))
139    }
140    #[doc = r"Get enumerated values variant"]
141    #[inline(always)]
142    pub fn variant(&self) -> TXRDYEN_A {
143        match self.bits {
144            false => TXRDYEN_A::TXRDYEN_0,
145            true => TXRDYEN_A::TXRDYEN_1,
146        }
147    }
148    #[doc = "Checks if the value of the field is `TXRDYEN_0`"]
149    #[inline(always)]
150    pub fn is_txrdyen_0(&self) -> bool {
151        **self == TXRDYEN_A::TXRDYEN_0
152    }
153    #[doc = "Checks if the value of the field is `TXRDYEN_1`"]
154    #[inline(always)]
155    pub fn is_txrdyen_1(&self) -> bool {
156        **self == TXRDYEN_A::TXRDYEN_1
157    }
158}
159impl core::ops::Deref for TXRDYEN_R {
160    type Target = crate::FieldReader<bool, TXRDYEN_A>;
161    #[inline(always)]
162    fn deref(&self) -> &Self::Target {
163        &self.0
164    }
165}
166#[doc = "Field `TXRDYEN` writer - Determines whether an interrupt occurs when the transmitter holding register is available."]
167pub struct TXRDYEN_W<'a> {
168    w: &'a mut W,
169}
170impl<'a> TXRDYEN_W<'a> {
171    #[doc = r"Writes `variant` to the field"]
172    #[inline(always)]
173    pub fn variant(self, variant: TXRDYEN_A) -> &'a mut W {
174        self.bit(variant.into())
175    }
176    #[doc = "No interrupt will be generated when the transmitter holding register is available."]
177    #[inline(always)]
178    pub fn txrdyen_0(self) -> &'a mut W {
179        self.variant(TXRDYEN_A::TXRDYEN_0)
180    }
181    #[doc = "An interrupt will be generated when data may be written to TXDAT."]
182    #[inline(always)]
183    pub fn txrdyen_1(self) -> &'a mut W {
184        self.variant(TXRDYEN_A::TXRDYEN_1)
185    }
186    #[doc = r"Sets the field bit"]
187    #[inline(always)]
188    pub fn set_bit(self) -> &'a mut W {
189        self.bit(true)
190    }
191    #[doc = r"Clears the field bit"]
192    #[inline(always)]
193    pub fn clear_bit(self) -> &'a mut W {
194        self.bit(false)
195    }
196    #[doc = r"Writes raw bits to the field"]
197    #[inline(always)]
198    pub fn bit(self, value: bool) -> &'a mut W {
199        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
200        self.w
201    }
202}
203#[doc = "Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur.\n\nValue on reset: 0"]
204#[derive(Clone, Copy, Debug, PartialEq)]
205pub enum RXOVEN_A {
206    #[doc = "0: No interrupt will be generated when a receiver overrun occurs."]
207    RXOVEN_0 = 0,
208    #[doc = "1: An interrupt will be generated if a receiver overrun occurs."]
209    RXOVEN_1 = 1,
210}
211impl From<RXOVEN_A> for bool {
212    #[inline(always)]
213    fn from(variant: RXOVEN_A) -> Self {
214        variant as u8 != 0
215    }
216}
217#[doc = "Field `RXOVEN` reader - Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur."]
218pub struct RXOVEN_R(crate::FieldReader<bool, RXOVEN_A>);
219impl RXOVEN_R {
220    pub(crate) fn new(bits: bool) -> Self {
221        RXOVEN_R(crate::FieldReader::new(bits))
222    }
223    #[doc = r"Get enumerated values variant"]
224    #[inline(always)]
225    pub fn variant(&self) -> RXOVEN_A {
226        match self.bits {
227            false => RXOVEN_A::RXOVEN_0,
228            true => RXOVEN_A::RXOVEN_1,
229        }
230    }
231    #[doc = "Checks if the value of the field is `RXOVEN_0`"]
232    #[inline(always)]
233    pub fn is_rxoven_0(&self) -> bool {
234        **self == RXOVEN_A::RXOVEN_0
235    }
236    #[doc = "Checks if the value of the field is `RXOVEN_1`"]
237    #[inline(always)]
238    pub fn is_rxoven_1(&self) -> bool {
239        **self == RXOVEN_A::RXOVEN_1
240    }
241}
242impl core::ops::Deref for RXOVEN_R {
243    type Target = crate::FieldReader<bool, RXOVEN_A>;
244    #[inline(always)]
245    fn deref(&self) -> &Self::Target {
246        &self.0
247    }
248}
249#[doc = "Field `RXOVEN` writer - Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur."]
250pub struct RXOVEN_W<'a> {
251    w: &'a mut W,
252}
253impl<'a> RXOVEN_W<'a> {
254    #[doc = r"Writes `variant` to the field"]
255    #[inline(always)]
256    pub fn variant(self, variant: RXOVEN_A) -> &'a mut W {
257        self.bit(variant.into())
258    }
259    #[doc = "No interrupt will be generated when a receiver overrun occurs."]
260    #[inline(always)]
261    pub fn rxoven_0(self) -> &'a mut W {
262        self.variant(RXOVEN_A::RXOVEN_0)
263    }
264    #[doc = "An interrupt will be generated if a receiver overrun occurs."]
265    #[inline(always)]
266    pub fn rxoven_1(self) -> &'a mut W {
267        self.variant(RXOVEN_A::RXOVEN_1)
268    }
269    #[doc = r"Sets the field bit"]
270    #[inline(always)]
271    pub fn set_bit(self) -> &'a mut W {
272        self.bit(true)
273    }
274    #[doc = r"Clears the field bit"]
275    #[inline(always)]
276    pub fn clear_bit(self) -> &'a mut W {
277        self.bit(false)
278    }
279    #[doc = r"Writes raw bits to the field"]
280    #[inline(always)]
281    pub fn bit(self, value: bool) -> &'a mut W {
282        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
283        self.w
284    }
285}
286#[doc = "Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available.\n\nValue on reset: 0"]
287#[derive(Clone, Copy, Debug, PartialEq)]
288pub enum TXUREN_A {
289    #[doc = "0: No interrupt will be generated when the transmitter underruns."]
290    TXUREN_0 = 0,
291    #[doc = "1: An interrupt will be generated if the transmitter underruns."]
292    TXUREN_1 = 1,
293}
294impl From<TXUREN_A> for bool {
295    #[inline(always)]
296    fn from(variant: TXUREN_A) -> Self {
297        variant as u8 != 0
298    }
299}
300#[doc = "Field `TXUREN` reader - Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available."]
301pub struct TXUREN_R(crate::FieldReader<bool, TXUREN_A>);
302impl TXUREN_R {
303    pub(crate) fn new(bits: bool) -> Self {
304        TXUREN_R(crate::FieldReader::new(bits))
305    }
306    #[doc = r"Get enumerated values variant"]
307    #[inline(always)]
308    pub fn variant(&self) -> TXUREN_A {
309        match self.bits {
310            false => TXUREN_A::TXUREN_0,
311            true => TXUREN_A::TXUREN_1,
312        }
313    }
314    #[doc = "Checks if the value of the field is `TXUREN_0`"]
315    #[inline(always)]
316    pub fn is_txuren_0(&self) -> bool {
317        **self == TXUREN_A::TXUREN_0
318    }
319    #[doc = "Checks if the value of the field is `TXUREN_1`"]
320    #[inline(always)]
321    pub fn is_txuren_1(&self) -> bool {
322        **self == TXUREN_A::TXUREN_1
323    }
324}
325impl core::ops::Deref for TXUREN_R {
326    type Target = crate::FieldReader<bool, TXUREN_A>;
327    #[inline(always)]
328    fn deref(&self) -> &Self::Target {
329        &self.0
330    }
331}
332#[doc = "Field `TXUREN` writer - Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available."]
333pub struct TXUREN_W<'a> {
334    w: &'a mut W,
335}
336impl<'a> TXUREN_W<'a> {
337    #[doc = r"Writes `variant` to the field"]
338    #[inline(always)]
339    pub fn variant(self, variant: TXUREN_A) -> &'a mut W {
340        self.bit(variant.into())
341    }
342    #[doc = "No interrupt will be generated when the transmitter underruns."]
343    #[inline(always)]
344    pub fn txuren_0(self) -> &'a mut W {
345        self.variant(TXUREN_A::TXUREN_0)
346    }
347    #[doc = "An interrupt will be generated if the transmitter underruns."]
348    #[inline(always)]
349    pub fn txuren_1(self) -> &'a mut W {
350        self.variant(TXUREN_A::TXUREN_1)
351    }
352    #[doc = r"Sets the field bit"]
353    #[inline(always)]
354    pub fn set_bit(self) -> &'a mut W {
355        self.bit(true)
356    }
357    #[doc = r"Clears the field bit"]
358    #[inline(always)]
359    pub fn clear_bit(self) -> &'a mut W {
360        self.bit(false)
361    }
362    #[doc = r"Writes raw bits to the field"]
363    #[inline(always)]
364    pub fn bit(self, value: bool) -> &'a mut W {
365        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
366        self.w
367    }
368}
369#[doc = "Determines whether an interrupt occurs when the Slave Select is asserted.\n\nValue on reset: 0"]
370#[derive(Clone, Copy, Debug, PartialEq)]
371pub enum SSAEN_A {
372    #[doc = "0: No interrupt will be generated when any Slave Select transitions from deasserted to asserted."]
373    SSAEN_0 = 0,
374    #[doc = "1: An interrupt will be generated when any Slave Select transitions from deasserted to asserted."]
375    SSAEN_1 = 1,
376}
377impl From<SSAEN_A> for bool {
378    #[inline(always)]
379    fn from(variant: SSAEN_A) -> Self {
380        variant as u8 != 0
381    }
382}
383#[doc = "Field `SSAEN` reader - Determines whether an interrupt occurs when the Slave Select is asserted."]
384pub struct SSAEN_R(crate::FieldReader<bool, SSAEN_A>);
385impl SSAEN_R {
386    pub(crate) fn new(bits: bool) -> Self {
387        SSAEN_R(crate::FieldReader::new(bits))
388    }
389    #[doc = r"Get enumerated values variant"]
390    #[inline(always)]
391    pub fn variant(&self) -> SSAEN_A {
392        match self.bits {
393            false => SSAEN_A::SSAEN_0,
394            true => SSAEN_A::SSAEN_1,
395        }
396    }
397    #[doc = "Checks if the value of the field is `SSAEN_0`"]
398    #[inline(always)]
399    pub fn is_ssaen_0(&self) -> bool {
400        **self == SSAEN_A::SSAEN_0
401    }
402    #[doc = "Checks if the value of the field is `SSAEN_1`"]
403    #[inline(always)]
404    pub fn is_ssaen_1(&self) -> bool {
405        **self == SSAEN_A::SSAEN_1
406    }
407}
408impl core::ops::Deref for SSAEN_R {
409    type Target = crate::FieldReader<bool, SSAEN_A>;
410    #[inline(always)]
411    fn deref(&self) -> &Self::Target {
412        &self.0
413    }
414}
415#[doc = "Field `SSAEN` writer - Determines whether an interrupt occurs when the Slave Select is asserted."]
416pub struct SSAEN_W<'a> {
417    w: &'a mut W,
418}
419impl<'a> SSAEN_W<'a> {
420    #[doc = r"Writes `variant` to the field"]
421    #[inline(always)]
422    pub fn variant(self, variant: SSAEN_A) -> &'a mut W {
423        self.bit(variant.into())
424    }
425    #[doc = "No interrupt will be generated when any Slave Select transitions from deasserted to asserted."]
426    #[inline(always)]
427    pub fn ssaen_0(self) -> &'a mut W {
428        self.variant(SSAEN_A::SSAEN_0)
429    }
430    #[doc = "An interrupt will be generated when any Slave Select transitions from deasserted to asserted."]
431    #[inline(always)]
432    pub fn ssaen_1(self) -> &'a mut W {
433        self.variant(SSAEN_A::SSAEN_1)
434    }
435    #[doc = r"Sets the field bit"]
436    #[inline(always)]
437    pub fn set_bit(self) -> &'a mut W {
438        self.bit(true)
439    }
440    #[doc = r"Clears the field bit"]
441    #[inline(always)]
442    pub fn clear_bit(self) -> &'a mut W {
443        self.bit(false)
444    }
445    #[doc = r"Writes raw bits to the field"]
446    #[inline(always)]
447    pub fn bit(self, value: bool) -> &'a mut W {
448        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
449        self.w
450    }
451}
452#[doc = "Determines whether an interrupt occurs when the Slave Select is deasserted.\n\nValue on reset: 0"]
453#[derive(Clone, Copy, Debug, PartialEq)]
454pub enum SSDEN_A {
455    #[doc = "0: No interrupt will be generated when all asserted Slave Selects transition to deasserted."]
456    SSDEN_0 = 0,
457    #[doc = "1: An interrupt will be generated when all asserted Slave Selects transition to deasserted."]
458    SSDEN_1 = 1,
459}
460impl From<SSDEN_A> for bool {
461    #[inline(always)]
462    fn from(variant: SSDEN_A) -> Self {
463        variant as u8 != 0
464    }
465}
466#[doc = "Field `SSDEN` reader - Determines whether an interrupt occurs when the Slave Select is deasserted."]
467pub struct SSDEN_R(crate::FieldReader<bool, SSDEN_A>);
468impl SSDEN_R {
469    pub(crate) fn new(bits: bool) -> Self {
470        SSDEN_R(crate::FieldReader::new(bits))
471    }
472    #[doc = r"Get enumerated values variant"]
473    #[inline(always)]
474    pub fn variant(&self) -> SSDEN_A {
475        match self.bits {
476            false => SSDEN_A::SSDEN_0,
477            true => SSDEN_A::SSDEN_1,
478        }
479    }
480    #[doc = "Checks if the value of the field is `SSDEN_0`"]
481    #[inline(always)]
482    pub fn is_ssden_0(&self) -> bool {
483        **self == SSDEN_A::SSDEN_0
484    }
485    #[doc = "Checks if the value of the field is `SSDEN_1`"]
486    #[inline(always)]
487    pub fn is_ssden_1(&self) -> bool {
488        **self == SSDEN_A::SSDEN_1
489    }
490}
491impl core::ops::Deref for SSDEN_R {
492    type Target = crate::FieldReader<bool, SSDEN_A>;
493    #[inline(always)]
494    fn deref(&self) -> &Self::Target {
495        &self.0
496    }
497}
498#[doc = "Field `SSDEN` writer - Determines whether an interrupt occurs when the Slave Select is deasserted."]
499pub struct SSDEN_W<'a> {
500    w: &'a mut W,
501}
502impl<'a> SSDEN_W<'a> {
503    #[doc = r"Writes `variant` to the field"]
504    #[inline(always)]
505    pub fn variant(self, variant: SSDEN_A) -> &'a mut W {
506        self.bit(variant.into())
507    }
508    #[doc = "No interrupt will be generated when all asserted Slave Selects transition to deasserted."]
509    #[inline(always)]
510    pub fn ssden_0(self) -> &'a mut W {
511        self.variant(SSDEN_A::SSDEN_0)
512    }
513    #[doc = "An interrupt will be generated when all asserted Slave Selects transition to deasserted."]
514    #[inline(always)]
515    pub fn ssden_1(self) -> &'a mut W {
516        self.variant(SSDEN_A::SSDEN_1)
517    }
518    #[doc = r"Sets the field bit"]
519    #[inline(always)]
520    pub fn set_bit(self) -> &'a mut W {
521        self.bit(true)
522    }
523    #[doc = r"Clears the field bit"]
524    #[inline(always)]
525    pub fn clear_bit(self) -> &'a mut W {
526        self.bit(false)
527    }
528    #[doc = r"Writes raw bits to the field"]
529    #[inline(always)]
530    pub fn bit(self, value: bool) -> &'a mut W {
531        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
532        self.w
533    }
534}
535#[doc = "Determines whether an interrupt occurs when the MSTIDLE enable\n\nValue on reset: 0"]
536#[derive(Clone, Copy, Debug, PartialEq)]
537pub enum MSTIDLEEN_A {
538    #[doc = "0: No interrupt will be generated when MSTIDLE enabled."]
539    MSTIDLEEN_0 = 0,
540    #[doc = "1: An interrupt will be generated when MSTIDLE enabled."]
541    MSTIDLEEN_1 = 1,
542}
543impl From<MSTIDLEEN_A> for bool {
544    #[inline(always)]
545    fn from(variant: MSTIDLEEN_A) -> Self {
546        variant as u8 != 0
547    }
548}
549#[doc = "Field `MSTIDLEEN` reader - Determines whether an interrupt occurs when the MSTIDLE enable"]
550pub struct MSTIDLEEN_R(crate::FieldReader<bool, MSTIDLEEN_A>);
551impl MSTIDLEEN_R {
552    pub(crate) fn new(bits: bool) -> Self {
553        MSTIDLEEN_R(crate::FieldReader::new(bits))
554    }
555    #[doc = r"Get enumerated values variant"]
556    #[inline(always)]
557    pub fn variant(&self) -> MSTIDLEEN_A {
558        match self.bits {
559            false => MSTIDLEEN_A::MSTIDLEEN_0,
560            true => MSTIDLEEN_A::MSTIDLEEN_1,
561        }
562    }
563    #[doc = "Checks if the value of the field is `MSTIDLEEN_0`"]
564    #[inline(always)]
565    pub fn is_mstidleen_0(&self) -> bool {
566        **self == MSTIDLEEN_A::MSTIDLEEN_0
567    }
568    #[doc = "Checks if the value of the field is `MSTIDLEEN_1`"]
569    #[inline(always)]
570    pub fn is_mstidleen_1(&self) -> bool {
571        **self == MSTIDLEEN_A::MSTIDLEEN_1
572    }
573}
574impl core::ops::Deref for MSTIDLEEN_R {
575    type Target = crate::FieldReader<bool, MSTIDLEEN_A>;
576    #[inline(always)]
577    fn deref(&self) -> &Self::Target {
578        &self.0
579    }
580}
581#[doc = "Field `MSTIDLEEN` writer - Determines whether an interrupt occurs when the MSTIDLE enable"]
582pub struct MSTIDLEEN_W<'a> {
583    w: &'a mut W,
584}
585impl<'a> MSTIDLEEN_W<'a> {
586    #[doc = r"Writes `variant` to the field"]
587    #[inline(always)]
588    pub fn variant(self, variant: MSTIDLEEN_A) -> &'a mut W {
589        self.bit(variant.into())
590    }
591    #[doc = "No interrupt will be generated when MSTIDLE enabled."]
592    #[inline(always)]
593    pub fn mstidleen_0(self) -> &'a mut W {
594        self.variant(MSTIDLEEN_A::MSTIDLEEN_0)
595    }
596    #[doc = "An interrupt will be generated when MSTIDLE enabled."]
597    #[inline(always)]
598    pub fn mstidleen_1(self) -> &'a mut W {
599        self.variant(MSTIDLEEN_A::MSTIDLEEN_1)
600    }
601    #[doc = r"Sets the field bit"]
602    #[inline(always)]
603    pub fn set_bit(self) -> &'a mut W {
604        self.bit(true)
605    }
606    #[doc = r"Clears the field bit"]
607    #[inline(always)]
608    pub fn clear_bit(self) -> &'a mut W {
609        self.bit(false)
610    }
611    #[doc = r"Writes raw bits to the field"]
612    #[inline(always)]
613    pub fn bit(self, value: bool) -> &'a mut W {
614        self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
615        self.w
616    }
617}
618impl R {
619    #[doc = "Bit 0 - Determines whether an interrupt occurs when receiver data is available."]
620    #[inline(always)]
621    pub fn rxrdyen(&self) -> RXRDYEN_R {
622        RXRDYEN_R::new((self.bits & 0x01) != 0)
623    }
624    #[doc = "Bit 1 - Determines whether an interrupt occurs when the transmitter holding register is available."]
625    #[inline(always)]
626    pub fn txrdyen(&self) -> TXRDYEN_R {
627        TXRDYEN_R::new(((self.bits >> 1) & 0x01) != 0)
628    }
629    #[doc = "Bit 2 - Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur."]
630    #[inline(always)]
631    pub fn rxoven(&self) -> RXOVEN_R {
632        RXOVEN_R::new(((self.bits >> 2) & 0x01) != 0)
633    }
634    #[doc = "Bit 3 - Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available."]
635    #[inline(always)]
636    pub fn txuren(&self) -> TXUREN_R {
637        TXUREN_R::new(((self.bits >> 3) & 0x01) != 0)
638    }
639    #[doc = "Bit 4 - Determines whether an interrupt occurs when the Slave Select is asserted."]
640    #[inline(always)]
641    pub fn ssaen(&self) -> SSAEN_R {
642        SSAEN_R::new(((self.bits >> 4) & 0x01) != 0)
643    }
644    #[doc = "Bit 5 - Determines whether an interrupt occurs when the Slave Select is deasserted."]
645    #[inline(always)]
646    pub fn ssden(&self) -> SSDEN_R {
647        SSDEN_R::new(((self.bits >> 5) & 0x01) != 0)
648    }
649    #[doc = "Bit 8 - Determines whether an interrupt occurs when the MSTIDLE enable"]
650    #[inline(always)]
651    pub fn mstidleen(&self) -> MSTIDLEEN_R {
652        MSTIDLEEN_R::new(((self.bits >> 8) & 0x01) != 0)
653    }
654}
655impl W {
656    #[doc = "Bit 0 - Determines whether an interrupt occurs when receiver data is available."]
657    #[inline(always)]
658    pub fn rxrdyen(&mut self) -> RXRDYEN_W {
659        RXRDYEN_W { w: self }
660    }
661    #[doc = "Bit 1 - Determines whether an interrupt occurs when the transmitter holding register is available."]
662    #[inline(always)]
663    pub fn txrdyen(&mut self) -> TXRDYEN_W {
664        TXRDYEN_W { w: self }
665    }
666    #[doc = "Bit 2 - Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur."]
667    #[inline(always)]
668    pub fn rxoven(&mut self) -> RXOVEN_W {
669        RXOVEN_W { w: self }
670    }
671    #[doc = "Bit 3 - Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available."]
672    #[inline(always)]
673    pub fn txuren(&mut self) -> TXUREN_W {
674        TXUREN_W { w: self }
675    }
676    #[doc = "Bit 4 - Determines whether an interrupt occurs when the Slave Select is asserted."]
677    #[inline(always)]
678    pub fn ssaen(&mut self) -> SSAEN_W {
679        SSAEN_W { w: self }
680    }
681    #[doc = "Bit 5 - Determines whether an interrupt occurs when the Slave Select is deasserted."]
682    #[inline(always)]
683    pub fn ssden(&mut self) -> SSDEN_W {
684        SSDEN_W { w: self }
685    }
686    #[doc = "Bit 8 - Determines whether an interrupt occurs when the MSTIDLE enable"]
687    #[inline(always)]
688    pub fn mstidleen(&mut self) -> MSTIDLEEN_W {
689        MSTIDLEEN_W { w: self }
690    }
691    #[doc = "Writes raw bits to the register."]
692    #[inline(always)]
693    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
694        self.0.bits(bits);
695        self
696    }
697}
698#[doc = "SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"]
699pub struct INTENSET_SPEC;
700impl crate::RegisterSpec for INTENSET_SPEC {
701    type Ux = u32;
702}
703#[doc = "`read()` method returns [intenset::R](R) reader structure"]
704impl crate::Readable for INTENSET_SPEC {
705    type Reader = R;
706}
707#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"]
708impl crate::Writable for INTENSET_SPEC {
709    type Writer = W;
710}
711#[doc = "`reset()` method sets INTENSET to value 0"]
712impl crate::Resettable for INTENSET_SPEC {
713    #[inline(always)]
714    fn reset_value() -> Self::Ux {
715        0
716    }
717}
lpc82x_pac/spi0/intenset.rs

lpc82x_pac/spi0/
intenset.rs
