1#[doc = "Register `DLY` reader"]
2pub struct R(crate::R<DLY_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<DLY_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<DLY_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<DLY_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `DLY` writer"]
17pub struct W(crate::W<DLY_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<DLY_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<DLY_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<DLY_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `PRE_DELAY` reader - Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."]
38pub struct PRE_DELAY_R(crate::FieldReader<u8, u8>);
39impl PRE_DELAY_R {
40 pub(crate) fn new(bits: u8) -> Self {
41 PRE_DELAY_R(crate::FieldReader::new(bits))
42 }
43}
44impl core::ops::Deref for PRE_DELAY_R {
45 type Target = crate::FieldReader<u8, u8>;
46 #[inline(always)]
47 fn deref(&self) -> &Self::Target {
48 &self.0
49 }
50}
51#[doc = "Field `PRE_DELAY` writer - Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."]
52pub struct PRE_DELAY_W<'a> {
53 w: &'a mut W,
54}
55impl<'a> PRE_DELAY_W<'a> {
56 #[doc = r"Writes raw bits to the field"]
57 #[inline(always)]
58 pub unsafe fn bits(self, value: u8) -> &'a mut W {
59 self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f);
60 self.w
61 }
62}
63#[doc = "Field `POST_DELAY` reader - Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."]
64pub struct POST_DELAY_R(crate::FieldReader<u8, u8>);
65impl POST_DELAY_R {
66 pub(crate) fn new(bits: u8) -> Self {
67 POST_DELAY_R(crate::FieldReader::new(bits))
68 }
69}
70impl core::ops::Deref for POST_DELAY_R {
71 type Target = crate::FieldReader<u8, u8>;
72 #[inline(always)]
73 fn deref(&self) -> &Self::Target {
74 &self.0
75 }
76}
77#[doc = "Field `POST_DELAY` writer - Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."]
78pub struct POST_DELAY_W<'a> {
79 w: &'a mut W,
80}
81impl<'a> POST_DELAY_W<'a> {
82 #[doc = r"Writes raw bits to the field"]
83 #[inline(always)]
84 pub unsafe fn bits(self, value: u8) -> &'a mut W {
85 self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4);
86 self.w
87 }
88}
89#[doc = "Field `FRAME_DELAY` reader - If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."]
90pub struct FRAME_DELAY_R(crate::FieldReader<u8, u8>);
91impl FRAME_DELAY_R {
92 pub(crate) fn new(bits: u8) -> Self {
93 FRAME_DELAY_R(crate::FieldReader::new(bits))
94 }
95}
96impl core::ops::Deref for FRAME_DELAY_R {
97 type Target = crate::FieldReader<u8, u8>;
98 #[inline(always)]
99 fn deref(&self) -> &Self::Target {
100 &self.0
101 }
102}
103#[doc = "Field `FRAME_DELAY` writer - If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."]
104pub struct FRAME_DELAY_W<'a> {
105 w: &'a mut W,
106}
107impl<'a> FRAME_DELAY_W<'a> {
108 #[doc = r"Writes raw bits to the field"]
109 #[inline(always)]
110 pub unsafe fn bits(self, value: u8) -> &'a mut W {
111 self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8);
112 self.w
113 }
114}
115#[doc = "Field `TRANSFER_DELAY` reader - Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times."]
116pub struct TRANSFER_DELAY_R(crate::FieldReader<u8, u8>);
117impl TRANSFER_DELAY_R {
118 pub(crate) fn new(bits: u8) -> Self {
119 TRANSFER_DELAY_R(crate::FieldReader::new(bits))
120 }
121}
122impl core::ops::Deref for TRANSFER_DELAY_R {
123 type Target = crate::FieldReader<u8, u8>;
124 #[inline(always)]
125 fn deref(&self) -> &Self::Target {
126 &self.0
127 }
128}
129#[doc = "Field `TRANSFER_DELAY` writer - Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times."]
130pub struct TRANSFER_DELAY_W<'a> {
131 w: &'a mut W,
132}
133impl<'a> TRANSFER_DELAY_W<'a> {
134 #[doc = r"Writes raw bits to the field"]
135 #[inline(always)]
136 pub unsafe fn bits(self, value: u8) -> &'a mut W {
137 self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12);
138 self.w
139 }
140}
141impl R {
142 #[doc = "Bits 0:3 - Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."]
143 #[inline(always)]
144 pub fn pre_delay(&self) -> PRE_DELAY_R {
145 PRE_DELAY_R::new((self.bits & 0x0f) as u8)
146 }
147 #[doc = "Bits 4:7 - Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."]
148 #[inline(always)]
149 pub fn post_delay(&self) -> POST_DELAY_R {
150 POST_DELAY_R::new(((self.bits >> 4) & 0x0f) as u8)
151 }
152 #[doc = "Bits 8:11 - If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."]
153 #[inline(always)]
154 pub fn frame_delay(&self) -> FRAME_DELAY_R {
155 FRAME_DELAY_R::new(((self.bits >> 8) & 0x0f) as u8)
156 }
157 #[doc = "Bits 12:15 - Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times."]
158 #[inline(always)]
159 pub fn transfer_delay(&self) -> TRANSFER_DELAY_R {
160 TRANSFER_DELAY_R::new(((self.bits >> 12) & 0x0f) as u8)
161 }
162}
163impl W {
164 #[doc = "Bits 0:3 - Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."]
165 #[inline(always)]
166 pub fn pre_delay(&mut self) -> PRE_DELAY_W {
167 PRE_DELAY_W { w: self }
168 }
169 #[doc = "Bits 4:7 - Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."]
170 #[inline(always)]
171 pub fn post_delay(&mut self) -> POST_DELAY_W {
172 POST_DELAY_W { w: self }
173 }
174 #[doc = "Bits 8:11 - If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."]
175 #[inline(always)]
176 pub fn frame_delay(&mut self) -> FRAME_DELAY_W {
177 FRAME_DELAY_W { w: self }
178 }
179 #[doc = "Bits 12:15 - Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times."]
180 #[inline(always)]
181 pub fn transfer_delay(&mut self) -> TRANSFER_DELAY_W {
182 TRANSFER_DELAY_W { w: self }
183 }
184 #[doc = "Writes raw bits to the register."]
185 #[inline(always)]
186 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
187 self.0.bits(bits);
188 self
189 }
190}
191#[doc = "SPI Delay register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dly](index.html) module"]
192pub struct DLY_SPEC;
193impl crate::RegisterSpec for DLY_SPEC {
194 type Ux = u32;
195}
196#[doc = "`read()` method returns [dly::R](R) reader structure"]
197impl crate::Readable for DLY_SPEC {
198 type Reader = R;
199}
200#[doc = "`write(|w| ..)` method takes [dly::W](W) writer structure"]
201impl crate::Writable for DLY_SPEC {
202 type Writer = W;
203}
204#[doc = "`reset()` method sets DLY to value 0"]
205impl crate::Resettable for DLY_SPEC {
206 #[inline(always)]
207 fn reset_value() -> Self::Ux {
208 0
209 }
210}