lpc82x_pac/sct0/
dma1request.rs

1#[doc = "Register `DMA1REQUEST` reader"]
2pub struct R(crate::R<DMA1REQUEST_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DMA1REQUEST_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DMA1REQUEST_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DMA1REQUEST_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DMA1REQUEST` writer"]
17pub struct W(crate::W<DMA1REQUEST_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DMA1REQUEST_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DMA1REQUEST_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DMA1REQUEST_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `DEV_1` reader - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT."]
38pub struct DEV_1_R(crate::FieldReader<u8, u8>);
39impl DEV_1_R {
40    pub(crate) fn new(bits: u8) -> Self {
41        DEV_1_R(crate::FieldReader::new(bits))
42    }
43}
44impl core::ops::Deref for DEV_1_R {
45    type Target = crate::FieldReader<u8, u8>;
46    #[inline(always)]
47    fn deref(&self) -> &Self::Target {
48        &self.0
49    }
50}
51#[doc = "Field `DEV_1` writer - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT."]
52pub struct DEV_1_W<'a> {
53    w: &'a mut W,
54}
55impl<'a> DEV_1_W<'a> {
56    #[doc = r"Writes raw bits to the field"]
57    #[inline(always)]
58    pub unsafe fn bits(self, value: u8) -> &'a mut W {
59        self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f);
60        self.w
61    }
62}
63#[doc = "Field `DRL1` reader - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers."]
64pub struct DRL1_R(crate::FieldReader<bool, bool>);
65impl DRL1_R {
66    pub(crate) fn new(bits: bool) -> Self {
67        DRL1_R(crate::FieldReader::new(bits))
68    }
69}
70impl core::ops::Deref for DRL1_R {
71    type Target = crate::FieldReader<bool, bool>;
72    #[inline(always)]
73    fn deref(&self) -> &Self::Target {
74        &self.0
75    }
76}
77#[doc = "Field `DRL1` writer - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers."]
78pub struct DRL1_W<'a> {
79    w: &'a mut W,
80}
81impl<'a> DRL1_W<'a> {
82    #[doc = r"Sets the field bit"]
83    #[inline(always)]
84    pub fn set_bit(self) -> &'a mut W {
85        self.bit(true)
86    }
87    #[doc = r"Clears the field bit"]
88    #[inline(always)]
89    pub fn clear_bit(self) -> &'a mut W {
90        self.bit(false)
91    }
92    #[doc = r"Writes raw bits to the field"]
93    #[inline(always)]
94    pub fn bit(self, value: bool) -> &'a mut W {
95        self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30);
96        self.w
97    }
98}
99#[doc = "Field `DRQ1` reader - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup."]
100pub struct DRQ1_R(crate::FieldReader<bool, bool>);
101impl DRQ1_R {
102    pub(crate) fn new(bits: bool) -> Self {
103        DRQ1_R(crate::FieldReader::new(bits))
104    }
105}
106impl core::ops::Deref for DRQ1_R {
107    type Target = crate::FieldReader<bool, bool>;
108    #[inline(always)]
109    fn deref(&self) -> &Self::Target {
110        &self.0
111    }
112}
113#[doc = "Field `DRQ1` writer - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup."]
114pub struct DRQ1_W<'a> {
115    w: &'a mut W,
116}
117impl<'a> DRQ1_W<'a> {
118    #[doc = r"Sets the field bit"]
119    #[inline(always)]
120    pub fn set_bit(self) -> &'a mut W {
121        self.bit(true)
122    }
123    #[doc = r"Clears the field bit"]
124    #[inline(always)]
125    pub fn clear_bit(self) -> &'a mut W {
126        self.bit(false)
127    }
128    #[doc = r"Writes raw bits to the field"]
129    #[inline(always)]
130    pub fn bit(self, value: bool) -> &'a mut W {
131        self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
132        self.w
133    }
134}
135impl R {
136    #[doc = "Bits 0:5 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT."]
137    #[inline(always)]
138    pub fn dev_1(&self) -> DEV_1_R {
139        DEV_1_R::new((self.bits & 0x3f) as u8)
140    }
141    #[doc = "Bit 30 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers."]
142    #[inline(always)]
143    pub fn drl1(&self) -> DRL1_R {
144        DRL1_R::new(((self.bits >> 30) & 0x01) != 0)
145    }
146    #[doc = "Bit 31 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup."]
147    #[inline(always)]
148    pub fn drq1(&self) -> DRQ1_R {
149        DRQ1_R::new(((self.bits >> 31) & 0x01) != 0)
150    }
151}
152impl W {
153    #[doc = "Bits 0:5 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT."]
154    #[inline(always)]
155    pub fn dev_1(&mut self) -> DEV_1_W {
156        DEV_1_W { w: self }
157    }
158    #[doc = "Bit 30 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers."]
159    #[inline(always)]
160    pub fn drl1(&mut self) -> DRL1_W {
161        DRL1_W { w: self }
162    }
163    #[doc = "Bit 31 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup."]
164    #[inline(always)]
165    pub fn drq1(&mut self) -> DRQ1_W {
166        DRQ1_W { w: self }
167    }
168    #[doc = "Writes raw bits to the register."]
169    #[inline(always)]
170    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
171        self.0.bits(bits);
172        self
173    }
174}
175#[doc = "SCT DMA request 1 register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma1request](index.html) module"]
176pub struct DMA1REQUEST_SPEC;
177impl crate::RegisterSpec for DMA1REQUEST_SPEC {
178    type Ux = u32;
179}
180#[doc = "`read()` method returns [dma1request::R](R) reader structure"]
181impl crate::Readable for DMA1REQUEST_SPEC {
182    type Reader = R;
183}
184#[doc = "`write(|w| ..)` method takes [dma1request::W](W) writer structure"]
185impl crate::Writable for DMA1REQUEST_SPEC {
186    type Writer = W;
187}
188#[doc = "`reset()` method sets DMA1REQUEST to value 0"]
189impl crate::Resettable for DMA1REQUEST_SPEC {
190    #[inline(always)]
191    fn reset_value() -> Self::Ux {
192        0
193    }
194}
lpc82x_pac/sct0/dma1request.rs

lpc82x_pac/sct0/
dma1request.rs
