1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CTRL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CTRL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `DOWN_L` reader - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0."]
38pub struct DOWN_L_R(crate::FieldReader<bool, bool>);
39impl DOWN_L_R {
40 pub(crate) fn new(bits: bool) -> Self {
41 DOWN_L_R(crate::FieldReader::new(bits))
42 }
43}
44impl core::ops::Deref for DOWN_L_R {
45 type Target = crate::FieldReader<bool, bool>;
46 #[inline(always)]
47 fn deref(&self) -> &Self::Target {
48 &self.0
49 }
50}
51#[doc = "Field `DOWN_L` writer - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0."]
52pub struct DOWN_L_W<'a> {
53 w: &'a mut W,
54}
55impl<'a> DOWN_L_W<'a> {
56 #[doc = r"Sets the field bit"]
57 #[inline(always)]
58 pub fn set_bit(self) -> &'a mut W {
59 self.bit(true)
60 }
61 #[doc = r"Clears the field bit"]
62 #[inline(always)]
63 pub fn clear_bit(self) -> &'a mut W {
64 self.bit(false)
65 }
66 #[doc = r"Writes raw bits to the field"]
67 #[inline(always)]
68 pub fn bit(self, value: bool) -> &'a mut W {
69 self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
70 self.w
71 }
72}
73#[doc = "Field `STOP_L` reader - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If a designated start event occurs, this bit is cleared and counting resumes."]
74pub struct STOP_L_R(crate::FieldReader<bool, bool>);
75impl STOP_L_R {
76 pub(crate) fn new(bits: bool) -> Self {
77 STOP_L_R(crate::FieldReader::new(bits))
78 }
79}
80impl core::ops::Deref for STOP_L_R {
81 type Target = crate::FieldReader<bool, bool>;
82 #[inline(always)]
83 fn deref(&self) -> &Self::Target {
84 &self.0
85 }
86}
87#[doc = "Field `STOP_L` writer - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If a designated start event occurs, this bit is cleared and counting resumes."]
88pub struct STOP_L_W<'a> {
89 w: &'a mut W,
90}
91impl<'a> STOP_L_W<'a> {
92 #[doc = r"Sets the field bit"]
93 #[inline(always)]
94 pub fn set_bit(self) -> &'a mut W {
95 self.bit(true)
96 }
97 #[doc = r"Clears the field bit"]
98 #[inline(always)]
99 pub fn clear_bit(self) -> &'a mut W {
100 self.bit(false)
101 }
102 #[doc = r"Writes raw bits to the field"]
103 #[inline(always)]
104 pub fn bit(self, value: bool) -> &'a mut W {
105 self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
106 self.w
107 }
108}
109#[doc = "Field `HALT_L` reader - When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset."]
110pub struct HALT_L_R(crate::FieldReader<bool, bool>);
111impl HALT_L_R {
112 pub(crate) fn new(bits: bool) -> Self {
113 HALT_L_R(crate::FieldReader::new(bits))
114 }
115}
116impl core::ops::Deref for HALT_L_R {
117 type Target = crate::FieldReader<bool, bool>;
118 #[inline(always)]
119 fn deref(&self) -> &Self::Target {
120 &self.0
121 }
122}
123#[doc = "Field `HALT_L` writer - When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset."]
124pub struct HALT_L_W<'a> {
125 w: &'a mut W,
126}
127impl<'a> HALT_L_W<'a> {
128 #[doc = r"Sets the field bit"]
129 #[inline(always)]
130 pub fn set_bit(self) -> &'a mut W {
131 self.bit(true)
132 }
133 #[doc = r"Clears the field bit"]
134 #[inline(always)]
135 pub fn clear_bit(self) -> &'a mut W {
136 self.bit(false)
137 }
138 #[doc = r"Writes raw bits to the field"]
139 #[inline(always)]
140 pub fn bit(self, value: bool) -> &'a mut W {
141 self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
142 self.w
143 }
144}
145#[doc = "Field `CLRCTR_L` reader - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0."]
146pub struct CLRCTR_L_R(crate::FieldReader<bool, bool>);
147impl CLRCTR_L_R {
148 pub(crate) fn new(bits: bool) -> Self {
149 CLRCTR_L_R(crate::FieldReader::new(bits))
150 }
151}
152impl core::ops::Deref for CLRCTR_L_R {
153 type Target = crate::FieldReader<bool, bool>;
154 #[inline(always)]
155 fn deref(&self) -> &Self::Target {
156 &self.0
157 }
158}
159#[doc = "Field `CLRCTR_L` writer - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0."]
160pub struct CLRCTR_L_W<'a> {
161 w: &'a mut W,
162}
163impl<'a> CLRCTR_L_W<'a> {
164 #[doc = r"Sets the field bit"]
165 #[inline(always)]
166 pub fn set_bit(self) -> &'a mut W {
167 self.bit(true)
168 }
169 #[doc = r"Clears the field bit"]
170 #[inline(always)]
171 pub fn clear_bit(self) -> &'a mut W {
172 self.bit(false)
173 }
174 #[doc = r"Writes raw bits to the field"]
175 #[inline(always)]
176 pub fn bit(self, value: bool) -> &'a mut W {
177 self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
178 self.w
179 }
180}
181#[doc = "L or unified counter direction select\n\nValue on reset: 0"]
182#[derive(Clone, Copy, Debug, PartialEq)]
183pub enum BIDIR_L_A {
184 #[doc = "0: Up. The counter counts up to a limit condition, then is cleared to zero."]
185 UP = 0,
186 #[doc = "1: Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0."]
187 UP_DOWN = 1,
188}
189impl From<BIDIR_L_A> for bool {
190 #[inline(always)]
191 fn from(variant: BIDIR_L_A) -> Self {
192 variant as u8 != 0
193 }
194}
195#[doc = "Field `BIDIR_L` reader - L or unified counter direction select"]
196pub struct BIDIR_L_R(crate::FieldReader<bool, BIDIR_L_A>);
197impl BIDIR_L_R {
198 pub(crate) fn new(bits: bool) -> Self {
199 BIDIR_L_R(crate::FieldReader::new(bits))
200 }
201 #[doc = r"Get enumerated values variant"]
202 #[inline(always)]
203 pub fn variant(&self) -> BIDIR_L_A {
204 match self.bits {
205 false => BIDIR_L_A::UP,
206 true => BIDIR_L_A::UP_DOWN,
207 }
208 }
209 #[doc = "Checks if the value of the field is `UP`"]
210 #[inline(always)]
211 pub fn is_up(&self) -> bool {
212 **self == BIDIR_L_A::UP
213 }
214 #[doc = "Checks if the value of the field is `UP_DOWN`"]
215 #[inline(always)]
216 pub fn is_up_down(&self) -> bool {
217 **self == BIDIR_L_A::UP_DOWN
218 }
219}
220impl core::ops::Deref for BIDIR_L_R {
221 type Target = crate::FieldReader<bool, BIDIR_L_A>;
222 #[inline(always)]
223 fn deref(&self) -> &Self::Target {
224 &self.0
225 }
226}
227#[doc = "Field `BIDIR_L` writer - L or unified counter direction select"]
228pub struct BIDIR_L_W<'a> {
229 w: &'a mut W,
230}
231impl<'a> BIDIR_L_W<'a> {
232 #[doc = r"Writes `variant` to the field"]
233 #[inline(always)]
234 pub fn variant(self, variant: BIDIR_L_A) -> &'a mut W {
235 self.bit(variant.into())
236 }
237 #[doc = "Up. The counter counts up to a limit condition, then is cleared to zero."]
238 #[inline(always)]
239 pub fn up(self) -> &'a mut W {
240 self.variant(BIDIR_L_A::UP)
241 }
242 #[doc = "Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0."]
243 #[inline(always)]
244 pub fn up_down(self) -> &'a mut W {
245 self.variant(BIDIR_L_A::UP_DOWN)
246 }
247 #[doc = r"Sets the field bit"]
248 #[inline(always)]
249 pub fn set_bit(self) -> &'a mut W {
250 self.bit(true)
251 }
252 #[doc = r"Clears the field bit"]
253 #[inline(always)]
254 pub fn clear_bit(self) -> &'a mut W {
255 self.bit(false)
256 }
257 #[doc = r"Writes raw bits to the field"]
258 #[inline(always)]
259 pub fn bit(self, value: bool) -> &'a mut W {
260 self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
261 self.w
262 }
263}
264#[doc = "Field `PRE_L` reader - Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value."]
265pub struct PRE_L_R(crate::FieldReader<u8, u8>);
266impl PRE_L_R {
267 pub(crate) fn new(bits: u8) -> Self {
268 PRE_L_R(crate::FieldReader::new(bits))
269 }
270}
271impl core::ops::Deref for PRE_L_R {
272 type Target = crate::FieldReader<u8, u8>;
273 #[inline(always)]
274 fn deref(&self) -> &Self::Target {
275 &self.0
276 }
277}
278#[doc = "Field `PRE_L` writer - Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value."]
279pub struct PRE_L_W<'a> {
280 w: &'a mut W,
281}
282impl<'a> PRE_L_W<'a> {
283 #[doc = r"Writes raw bits to the field"]
284 #[inline(always)]
285 pub unsafe fn bits(self, value: u8) -> &'a mut W {
286 self.w.bits = (self.w.bits & !(0xff << 5)) | ((value as u32 & 0xff) << 5);
287 self.w
288 }
289}
290#[doc = "Field `DOWN_H` reader - This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0."]
291pub struct DOWN_H_R(crate::FieldReader<bool, bool>);
292impl DOWN_H_R {
293 pub(crate) fn new(bits: bool) -> Self {
294 DOWN_H_R(crate::FieldReader::new(bits))
295 }
296}
297impl core::ops::Deref for DOWN_H_R {
298 type Target = crate::FieldReader<bool, bool>;
299 #[inline(always)]
300 fn deref(&self) -> &Self::Target {
301 &self.0
302 }
303}
304#[doc = "Field `DOWN_H` writer - This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0."]
305pub struct DOWN_H_W<'a> {
306 w: &'a mut W,
307}
308impl<'a> DOWN_H_W<'a> {
309 #[doc = r"Sets the field bit"]
310 #[inline(always)]
311 pub fn set_bit(self) -> &'a mut W {
312 self.bit(true)
313 }
314 #[doc = r"Clears the field bit"]
315 #[inline(always)]
316 pub fn clear_bit(self) -> &'a mut W {
317 self.bit(false)
318 }
319 #[doc = r"Writes raw bits to the field"]
320 #[inline(always)]
321 pub fn bit(self, value: bool) -> &'a mut W {
322 self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
323 self.w
324 }
325}
326#[doc = "Field `STOP_H` reader - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes."]
327pub struct STOP_H_R(crate::FieldReader<bool, bool>);
328impl STOP_H_R {
329 pub(crate) fn new(bits: bool) -> Self {
330 STOP_H_R(crate::FieldReader::new(bits))
331 }
332}
333impl core::ops::Deref for STOP_H_R {
334 type Target = crate::FieldReader<bool, bool>;
335 #[inline(always)]
336 fn deref(&self) -> &Self::Target {
337 &self.0
338 }
339}
340#[doc = "Field `STOP_H` writer - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes."]
341pub struct STOP_H_W<'a> {
342 w: &'a mut W,
343}
344impl<'a> STOP_H_W<'a> {
345 #[doc = r"Sets the field bit"]
346 #[inline(always)]
347 pub fn set_bit(self) -> &'a mut W {
348 self.bit(true)
349 }
350 #[doc = r"Clears the field bit"]
351 #[inline(always)]
352 pub fn clear_bit(self) -> &'a mut W {
353 self.bit(false)
354 }
355 #[doc = r"Writes raw bits to the field"]
356 #[inline(always)]
357 pub fn bit(self, value: bool) -> &'a mut W {
358 self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17);
359 self.w
360 }
361}
362#[doc = "Field `HALT_H` reader - When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset."]
363pub struct HALT_H_R(crate::FieldReader<bool, bool>);
364impl HALT_H_R {
365 pub(crate) fn new(bits: bool) -> Self {
366 HALT_H_R(crate::FieldReader::new(bits))
367 }
368}
369impl core::ops::Deref for HALT_H_R {
370 type Target = crate::FieldReader<bool, bool>;
371 #[inline(always)]
372 fn deref(&self) -> &Self::Target {
373 &self.0
374 }
375}
376#[doc = "Field `HALT_H` writer - When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset."]
377pub struct HALT_H_W<'a> {
378 w: &'a mut W,
379}
380impl<'a> HALT_H_W<'a> {
381 #[doc = r"Sets the field bit"]
382 #[inline(always)]
383 pub fn set_bit(self) -> &'a mut W {
384 self.bit(true)
385 }
386 #[doc = r"Clears the field bit"]
387 #[inline(always)]
388 pub fn clear_bit(self) -> &'a mut W {
389 self.bit(false)
390 }
391 #[doc = r"Writes raw bits to the field"]
392 #[inline(always)]
393 pub fn bit(self, value: bool) -> &'a mut W {
394 self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18);
395 self.w
396 }
397}
398#[doc = "Field `CLRCTR_H` reader - Writing a 1 to this bit clears the H counter. This bit always reads as 0."]
399pub struct CLRCTR_H_R(crate::FieldReader<bool, bool>);
400impl CLRCTR_H_R {
401 pub(crate) fn new(bits: bool) -> Self {
402 CLRCTR_H_R(crate::FieldReader::new(bits))
403 }
404}
405impl core::ops::Deref for CLRCTR_H_R {
406 type Target = crate::FieldReader<bool, bool>;
407 #[inline(always)]
408 fn deref(&self) -> &Self::Target {
409 &self.0
410 }
411}
412#[doc = "Field `CLRCTR_H` writer - Writing a 1 to this bit clears the H counter. This bit always reads as 0."]
413pub struct CLRCTR_H_W<'a> {
414 w: &'a mut W,
415}
416impl<'a> CLRCTR_H_W<'a> {
417 #[doc = r"Sets the field bit"]
418 #[inline(always)]
419 pub fn set_bit(self) -> &'a mut W {
420 self.bit(true)
421 }
422 #[doc = r"Clears the field bit"]
423 #[inline(always)]
424 pub fn clear_bit(self) -> &'a mut W {
425 self.bit(false)
426 }
427 #[doc = r"Writes raw bits to the field"]
428 #[inline(always)]
429 pub fn bit(self, value: bool) -> &'a mut W {
430 self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19);
431 self.w
432 }
433}
434#[doc = "Direction select\n\nValue on reset: 0"]
435#[derive(Clone, Copy, Debug, PartialEq)]
436pub enum BIDIR_H_A {
437 #[doc = "0: The H counter counts up to its limit condition, then is cleared to zero."]
438 UP = 0,
439 #[doc = "1: The H counter counts up to its limit, then counts down to a limit condition or to 0."]
440 UP_DOWN = 1,
441}
442impl From<BIDIR_H_A> for bool {
443 #[inline(always)]
444 fn from(variant: BIDIR_H_A) -> Self {
445 variant as u8 != 0
446 }
447}
448#[doc = "Field `BIDIR_H` reader - Direction select"]
449pub struct BIDIR_H_R(crate::FieldReader<bool, BIDIR_H_A>);
450impl BIDIR_H_R {
451 pub(crate) fn new(bits: bool) -> Self {
452 BIDIR_H_R(crate::FieldReader::new(bits))
453 }
454 #[doc = r"Get enumerated values variant"]
455 #[inline(always)]
456 pub fn variant(&self) -> BIDIR_H_A {
457 match self.bits {
458 false => BIDIR_H_A::UP,
459 true => BIDIR_H_A::UP_DOWN,
460 }
461 }
462 #[doc = "Checks if the value of the field is `UP`"]
463 #[inline(always)]
464 pub fn is_up(&self) -> bool {
465 **self == BIDIR_H_A::UP
466 }
467 #[doc = "Checks if the value of the field is `UP_DOWN`"]
468 #[inline(always)]
469 pub fn is_up_down(&self) -> bool {
470 **self == BIDIR_H_A::UP_DOWN
471 }
472}
473impl core::ops::Deref for BIDIR_H_R {
474 type Target = crate::FieldReader<bool, BIDIR_H_A>;
475 #[inline(always)]
476 fn deref(&self) -> &Self::Target {
477 &self.0
478 }
479}
480#[doc = "Field `BIDIR_H` writer - Direction select"]
481pub struct BIDIR_H_W<'a> {
482 w: &'a mut W,
483}
484impl<'a> BIDIR_H_W<'a> {
485 #[doc = r"Writes `variant` to the field"]
486 #[inline(always)]
487 pub fn variant(self, variant: BIDIR_H_A) -> &'a mut W {
488 self.bit(variant.into())
489 }
490 #[doc = "The H counter counts up to its limit condition, then is cleared to zero."]
491 #[inline(always)]
492 pub fn up(self) -> &'a mut W {
493 self.variant(BIDIR_H_A::UP)
494 }
495 #[doc = "The H counter counts up to its limit, then counts down to a limit condition or to 0."]
496 #[inline(always)]
497 pub fn up_down(self) -> &'a mut W {
498 self.variant(BIDIR_H_A::UP_DOWN)
499 }
500 #[doc = r"Sets the field bit"]
501 #[inline(always)]
502 pub fn set_bit(self) -> &'a mut W {
503 self.bit(true)
504 }
505 #[doc = r"Clears the field bit"]
506 #[inline(always)]
507 pub fn clear_bit(self) -> &'a mut W {
508 self.bit(false)
509 }
510 #[doc = r"Writes raw bits to the field"]
511 #[inline(always)]
512 pub fn bit(self, value: bool) -> &'a mut W {
513 self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20);
514 self.w
515 }
516}
517#[doc = "Field `PRE_H` reader - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value."]
518pub struct PRE_H_R(crate::FieldReader<u8, u8>);
519impl PRE_H_R {
520 pub(crate) fn new(bits: u8) -> Self {
521 PRE_H_R(crate::FieldReader::new(bits))
522 }
523}
524impl core::ops::Deref for PRE_H_R {
525 type Target = crate::FieldReader<u8, u8>;
526 #[inline(always)]
527 fn deref(&self) -> &Self::Target {
528 &self.0
529 }
530}
531#[doc = "Field `PRE_H` writer - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value."]
532pub struct PRE_H_W<'a> {
533 w: &'a mut W,
534}
535impl<'a> PRE_H_W<'a> {
536 #[doc = r"Writes raw bits to the field"]
537 #[inline(always)]
538 pub unsafe fn bits(self, value: u8) -> &'a mut W {
539 self.w.bits = (self.w.bits & !(0xff << 21)) | ((value as u32 & 0xff) << 21);
540 self.w
541 }
542}
543impl R {
544 #[doc = "Bit 0 - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0."]
545 #[inline(always)]
546 pub fn down_l(&self) -> DOWN_L_R {
547 DOWN_L_R::new((self.bits & 0x01) != 0)
548 }
549 #[doc = "Bit 1 - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If a designated start event occurs, this bit is cleared and counting resumes."]
550 #[inline(always)]
551 pub fn stop_l(&self) -> STOP_L_R {
552 STOP_L_R::new(((self.bits >> 1) & 0x01) != 0)
553 }
554 #[doc = "Bit 2 - When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset."]
555 #[inline(always)]
556 pub fn halt_l(&self) -> HALT_L_R {
557 HALT_L_R::new(((self.bits >> 2) & 0x01) != 0)
558 }
559 #[doc = "Bit 3 - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0."]
560 #[inline(always)]
561 pub fn clrctr_l(&self) -> CLRCTR_L_R {
562 CLRCTR_L_R::new(((self.bits >> 3) & 0x01) != 0)
563 }
564 #[doc = "Bit 4 - L or unified counter direction select"]
565 #[inline(always)]
566 pub fn bidir_l(&self) -> BIDIR_L_R {
567 BIDIR_L_R::new(((self.bits >> 4) & 0x01) != 0)
568 }
569 #[doc = "Bits 5:12 - Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value."]
570 #[inline(always)]
571 pub fn pre_l(&self) -> PRE_L_R {
572 PRE_L_R::new(((self.bits >> 5) & 0xff) as u8)
573 }
574 #[doc = "Bit 16 - This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0."]
575 #[inline(always)]
576 pub fn down_h(&self) -> DOWN_H_R {
577 DOWN_H_R::new(((self.bits >> 16) & 0x01) != 0)
578 }
579 #[doc = "Bit 17 - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes."]
580 #[inline(always)]
581 pub fn stop_h(&self) -> STOP_H_R {
582 STOP_H_R::new(((self.bits >> 17) & 0x01) != 0)
583 }
584 #[doc = "Bit 18 - When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset."]
585 #[inline(always)]
586 pub fn halt_h(&self) -> HALT_H_R {
587 HALT_H_R::new(((self.bits >> 18) & 0x01) != 0)
588 }
589 #[doc = "Bit 19 - Writing a 1 to this bit clears the H counter. This bit always reads as 0."]
590 #[inline(always)]
591 pub fn clrctr_h(&self) -> CLRCTR_H_R {
592 CLRCTR_H_R::new(((self.bits >> 19) & 0x01) != 0)
593 }
594 #[doc = "Bit 20 - Direction select"]
595 #[inline(always)]
596 pub fn bidir_h(&self) -> BIDIR_H_R {
597 BIDIR_H_R::new(((self.bits >> 20) & 0x01) != 0)
598 }
599 #[doc = "Bits 21:28 - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value."]
600 #[inline(always)]
601 pub fn pre_h(&self) -> PRE_H_R {
602 PRE_H_R::new(((self.bits >> 21) & 0xff) as u8)
603 }
604}
605impl W {
606 #[doc = "Bit 0 - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0."]
607 #[inline(always)]
608 pub fn down_l(&mut self) -> DOWN_L_W {
609 DOWN_L_W { w: self }
610 }
611 #[doc = "Bit 1 - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If a designated start event occurs, this bit is cleared and counting resumes."]
612 #[inline(always)]
613 pub fn stop_l(&mut self) -> STOP_L_W {
614 STOP_L_W { w: self }
615 }
616 #[doc = "Bit 2 - When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset."]
617 #[inline(always)]
618 pub fn halt_l(&mut self) -> HALT_L_W {
619 HALT_L_W { w: self }
620 }
621 #[doc = "Bit 3 - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0."]
622 #[inline(always)]
623 pub fn clrctr_l(&mut self) -> CLRCTR_L_W {
624 CLRCTR_L_W { w: self }
625 }
626 #[doc = "Bit 4 - L or unified counter direction select"]
627 #[inline(always)]
628 pub fn bidir_l(&mut self) -> BIDIR_L_W {
629 BIDIR_L_W { w: self }
630 }
631 #[doc = "Bits 5:12 - Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value."]
632 #[inline(always)]
633 pub fn pre_l(&mut self) -> PRE_L_W {
634 PRE_L_W { w: self }
635 }
636 #[doc = "Bit 16 - This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0."]
637 #[inline(always)]
638 pub fn down_h(&mut self) -> DOWN_H_W {
639 DOWN_H_W { w: self }
640 }
641 #[doc = "Bit 17 - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes."]
642 #[inline(always)]
643 pub fn stop_h(&mut self) -> STOP_H_W {
644 STOP_H_W { w: self }
645 }
646 #[doc = "Bit 18 - When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset."]
647 #[inline(always)]
648 pub fn halt_h(&mut self) -> HALT_H_W {
649 HALT_H_W { w: self }
650 }
651 #[doc = "Bit 19 - Writing a 1 to this bit clears the H counter. This bit always reads as 0."]
652 #[inline(always)]
653 pub fn clrctr_h(&mut self) -> CLRCTR_H_W {
654 CLRCTR_H_W { w: self }
655 }
656 #[doc = "Bit 20 - Direction select"]
657 #[inline(always)]
658 pub fn bidir_h(&mut self) -> BIDIR_H_W {
659 BIDIR_H_W { w: self }
660 }
661 #[doc = "Bits 21:28 - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value."]
662 #[inline(always)]
663 pub fn pre_h(&mut self) -> PRE_H_W {
664 PRE_H_W { w: self }
665 }
666 #[doc = "Writes raw bits to the register."]
667 #[inline(always)]
668 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
669 self.0.bits(bits);
670 self
671 }
672}
673#[doc = "SCT control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
674pub struct CTRL_SPEC;
675impl crate::RegisterSpec for CTRL_SPEC {
676 type Ux = u32;
677}
678#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
679impl crate::Readable for CTRL_SPEC {
680 type Reader = R;
681}
682#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
683impl crate::Writable for CTRL_SPEC {
684 type Writer = W;
685}
686#[doc = "`reset()` method sets CTRL to value 0x0004_0004"]
687impl crate::Resettable for CTRL_SPEC {
688 #[inline(always)]
689 fn reset_value() -> Self::Ux {
690 0x0004_0004
691 }
692}