1#[doc = "Register `CONFIG` reader"]
2pub struct R(crate::R<CONFIG_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CONFIG_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CONFIG_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CONFIG_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CONFIG` writer"]
17pub struct W(crate::W<CONFIG_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CONFIG_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CONFIG_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CONFIG_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "SCT operation\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum UNIFY_A {
40 #[doc = "0: The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H."]
41 DUAL_COUNTER = 0,
42 #[doc = "1: The SCT operates as a unified 32-bit counter."]
43 UNIFIED_COUNTER = 1,
44}
45impl From<UNIFY_A> for bool {
46 #[inline(always)]
47 fn from(variant: UNIFY_A) -> Self {
48 variant as u8 != 0
49 }
50}
51#[doc = "Field `UNIFY` reader - SCT operation"]
52pub struct UNIFY_R(crate::FieldReader<bool, UNIFY_A>);
53impl UNIFY_R {
54 pub(crate) fn new(bits: bool) -> Self {
55 UNIFY_R(crate::FieldReader::new(bits))
56 }
57 #[doc = r"Get enumerated values variant"]
58 #[inline(always)]
59 pub fn variant(&self) -> UNIFY_A {
60 match self.bits {
61 false => UNIFY_A::DUAL_COUNTER,
62 true => UNIFY_A::UNIFIED_COUNTER,
63 }
64 }
65 #[doc = "Checks if the value of the field is `DUAL_COUNTER`"]
66 #[inline(always)]
67 pub fn is_dual_counter(&self) -> bool {
68 **self == UNIFY_A::DUAL_COUNTER
69 }
70 #[doc = "Checks if the value of the field is `UNIFIED_COUNTER`"]
71 #[inline(always)]
72 pub fn is_unified_counter(&self) -> bool {
73 **self == UNIFY_A::UNIFIED_COUNTER
74 }
75}
76impl core::ops::Deref for UNIFY_R {
77 type Target = crate::FieldReader<bool, UNIFY_A>;
78 #[inline(always)]
79 fn deref(&self) -> &Self::Target {
80 &self.0
81 }
82}
83#[doc = "Field `UNIFY` writer - SCT operation"]
84pub struct UNIFY_W<'a> {
85 w: &'a mut W,
86}
87impl<'a> UNIFY_W<'a> {
88 #[doc = r"Writes `variant` to the field"]
89 #[inline(always)]
90 pub fn variant(self, variant: UNIFY_A) -> &'a mut W {
91 self.bit(variant.into())
92 }
93 #[doc = "The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H."]
94 #[inline(always)]
95 pub fn dual_counter(self) -> &'a mut W {
96 self.variant(UNIFY_A::DUAL_COUNTER)
97 }
98 #[doc = "The SCT operates as a unified 32-bit counter."]
99 #[inline(always)]
100 pub fn unified_counter(self) -> &'a mut W {
101 self.variant(UNIFY_A::UNIFIED_COUNTER)
102 }
103 #[doc = r"Sets the field bit"]
104 #[inline(always)]
105 pub fn set_bit(self) -> &'a mut W {
106 self.bit(true)
107 }
108 #[doc = r"Clears the field bit"]
109 #[inline(always)]
110 pub fn clear_bit(self) -> &'a mut W {
111 self.bit(false)
112 }
113 #[doc = r"Writes raw bits to the field"]
114 #[inline(always)]
115 pub fn bit(self, value: bool) -> &'a mut W {
116 self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
117 self.w
118 }
119}
120#[doc = "SCT clock mode\n\nValue on reset: 0"]
121#[derive(Clone, Copy, Debug, PartialEq)]
122#[repr(u8)]
123pub enum CLKMODE_A {
124 #[doc = "0: System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers."]
125 SYSTEM_CLOCK_MODE = 0,
126 #[doc = "1: Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock mode."]
127 SAMPLED_SYSTEM_CLOCK_MODE = 1,
128 #[doc = "2: SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode."]
129 SCT_INPUT_CLOCK_MODE = 2,
130 #[doc = "3: Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock."]
131 ASYNCHRONOUS_MODE = 3,
132}
133impl From<CLKMODE_A> for u8 {
134 #[inline(always)]
135 fn from(variant: CLKMODE_A) -> Self {
136 variant as _
137 }
138}
139#[doc = "Field `CLKMODE` reader - SCT clock mode"]
140pub struct CLKMODE_R(crate::FieldReader<u8, CLKMODE_A>);
141impl CLKMODE_R {
142 pub(crate) fn new(bits: u8) -> Self {
143 CLKMODE_R(crate::FieldReader::new(bits))
144 }
145 #[doc = r"Get enumerated values variant"]
146 #[inline(always)]
147 pub fn variant(&self) -> CLKMODE_A {
148 match self.bits {
149 0 => CLKMODE_A::SYSTEM_CLOCK_MODE,
150 1 => CLKMODE_A::SAMPLED_SYSTEM_CLOCK_MODE,
151 2 => CLKMODE_A::SCT_INPUT_CLOCK_MODE,
152 3 => CLKMODE_A::ASYNCHRONOUS_MODE,
153 _ => unreachable!(),
154 }
155 }
156 #[doc = "Checks if the value of the field is `SYSTEM_CLOCK_MODE`"]
157 #[inline(always)]
158 pub fn is_system_clock_mode(&self) -> bool {
159 **self == CLKMODE_A::SYSTEM_CLOCK_MODE
160 }
161 #[doc = "Checks if the value of the field is `SAMPLED_SYSTEM_CLOCK_MODE`"]
162 #[inline(always)]
163 pub fn is_sampled_system_clock_mode(&self) -> bool {
164 **self == CLKMODE_A::SAMPLED_SYSTEM_CLOCK_MODE
165 }
166 #[doc = "Checks if the value of the field is `SCT_INPUT_CLOCK_MODE`"]
167 #[inline(always)]
168 pub fn is_sct_input_clock_mode(&self) -> bool {
169 **self == CLKMODE_A::SCT_INPUT_CLOCK_MODE
170 }
171 #[doc = "Checks if the value of the field is `ASYNCHRONOUS_MODE`"]
172 #[inline(always)]
173 pub fn is_asynchronous_mode(&self) -> bool {
174 **self == CLKMODE_A::ASYNCHRONOUS_MODE
175 }
176}
177impl core::ops::Deref for CLKMODE_R {
178 type Target = crate::FieldReader<u8, CLKMODE_A>;
179 #[inline(always)]
180 fn deref(&self) -> &Self::Target {
181 &self.0
182 }
183}
184#[doc = "Field `CLKMODE` writer - SCT clock mode"]
185pub struct CLKMODE_W<'a> {
186 w: &'a mut W,
187}
188impl<'a> CLKMODE_W<'a> {
189 #[doc = r"Writes `variant` to the field"]
190 #[inline(always)]
191 pub fn variant(self, variant: CLKMODE_A) -> &'a mut W {
192 self.bits(variant.into())
193 }
194 #[doc = "System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers."]
195 #[inline(always)]
196 pub fn system_clock_mode(self) -> &'a mut W {
197 self.variant(CLKMODE_A::SYSTEM_CLOCK_MODE)
198 }
199 #[doc = "Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock mode."]
200 #[inline(always)]
201 pub fn sampled_system_clock_mode(self) -> &'a mut W {
202 self.variant(CLKMODE_A::SAMPLED_SYSTEM_CLOCK_MODE)
203 }
204 #[doc = "SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode."]
205 #[inline(always)]
206 pub fn sct_input_clock_mode(self) -> &'a mut W {
207 self.variant(CLKMODE_A::SCT_INPUT_CLOCK_MODE)
208 }
209 #[doc = "Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock."]
210 #[inline(always)]
211 pub fn asynchronous_mode(self) -> &'a mut W {
212 self.variant(CLKMODE_A::ASYNCHRONOUS_MODE)
213 }
214 #[doc = r"Writes raw bits to the field"]
215 #[inline(always)]
216 pub fn bits(self, value: u8) -> &'a mut W {
217 self.w.bits = (self.w.bits & !(0x03 << 1)) | ((value as u32 & 0x03) << 1);
218 self.w
219 }
220}
221#[doc = "SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register.\n\nValue on reset: 0"]
222#[derive(Clone, Copy, Debug, PartialEq)]
223#[repr(u8)]
224pub enum CKSEL_A {
225 #[doc = "0: Rising edges on input 0."]
226 INPUT_0_RISING_EDGES = 0,
227 #[doc = "1: Falling edges on input 0."]
228 INPUT_0_FALLING_EDGE = 1,
229 #[doc = "2: Rising edges on input 1."]
230 INPUT_1_RISING_EDGES = 2,
231 #[doc = "3: Falling edges on input 1."]
232 INPUT_1_FALLING_EDGE = 3,
233 #[doc = "4: Rising edges on input 2."]
234 INPUT_2_RISING_EDGES = 4,
235 #[doc = "5: Falling edges on input 2."]
236 INPUT_2_FALLING_EDGE = 5,
237 #[doc = "6: Rising edges on input 3."]
238 INPUT_3_RISING_EDGES = 6,
239 #[doc = "7: Falling edges on input 3."]
240 INPUT_3_FALLING_EDGE = 7,
241}
242impl From<CKSEL_A> for u8 {
243 #[inline(always)]
244 fn from(variant: CKSEL_A) -> Self {
245 variant as _
246 }
247}
248#[doc = "Field `CKSEL` reader - SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register."]
249pub struct CKSEL_R(crate::FieldReader<u8, CKSEL_A>);
250impl CKSEL_R {
251 pub(crate) fn new(bits: u8) -> Self {
252 CKSEL_R(crate::FieldReader::new(bits))
253 }
254 #[doc = r"Get enumerated values variant"]
255 #[inline(always)]
256 pub fn variant(&self) -> Option<CKSEL_A> {
257 match self.bits {
258 0 => Some(CKSEL_A::INPUT_0_RISING_EDGES),
259 1 => Some(CKSEL_A::INPUT_0_FALLING_EDGE),
260 2 => Some(CKSEL_A::INPUT_1_RISING_EDGES),
261 3 => Some(CKSEL_A::INPUT_1_FALLING_EDGE),
262 4 => Some(CKSEL_A::INPUT_2_RISING_EDGES),
263 5 => Some(CKSEL_A::INPUT_2_FALLING_EDGE),
264 6 => Some(CKSEL_A::INPUT_3_RISING_EDGES),
265 7 => Some(CKSEL_A::INPUT_3_FALLING_EDGE),
266 _ => None,
267 }
268 }
269 #[doc = "Checks if the value of the field is `INPUT_0_RISING_EDGES`"]
270 #[inline(always)]
271 pub fn is_input_0_rising_edges(&self) -> bool {
272 **self == CKSEL_A::INPUT_0_RISING_EDGES
273 }
274 #[doc = "Checks if the value of the field is `INPUT_0_FALLING_EDGE`"]
275 #[inline(always)]
276 pub fn is_input_0_falling_edge(&self) -> bool {
277 **self == CKSEL_A::INPUT_0_FALLING_EDGE
278 }
279 #[doc = "Checks if the value of the field is `INPUT_1_RISING_EDGES`"]
280 #[inline(always)]
281 pub fn is_input_1_rising_edges(&self) -> bool {
282 **self == CKSEL_A::INPUT_1_RISING_EDGES
283 }
284 #[doc = "Checks if the value of the field is `INPUT_1_FALLING_EDGE`"]
285 #[inline(always)]
286 pub fn is_input_1_falling_edge(&self) -> bool {
287 **self == CKSEL_A::INPUT_1_FALLING_EDGE
288 }
289 #[doc = "Checks if the value of the field is `INPUT_2_RISING_EDGES`"]
290 #[inline(always)]
291 pub fn is_input_2_rising_edges(&self) -> bool {
292 **self == CKSEL_A::INPUT_2_RISING_EDGES
293 }
294 #[doc = "Checks if the value of the field is `INPUT_2_FALLING_EDGE`"]
295 #[inline(always)]
296 pub fn is_input_2_falling_edge(&self) -> bool {
297 **self == CKSEL_A::INPUT_2_FALLING_EDGE
298 }
299 #[doc = "Checks if the value of the field is `INPUT_3_RISING_EDGES`"]
300 #[inline(always)]
301 pub fn is_input_3_rising_edges(&self) -> bool {
302 **self == CKSEL_A::INPUT_3_RISING_EDGES
303 }
304 #[doc = "Checks if the value of the field is `INPUT_3_FALLING_EDGE`"]
305 #[inline(always)]
306 pub fn is_input_3_falling_edge(&self) -> bool {
307 **self == CKSEL_A::INPUT_3_FALLING_EDGE
308 }
309}
310impl core::ops::Deref for CKSEL_R {
311 type Target = crate::FieldReader<u8, CKSEL_A>;
312 #[inline(always)]
313 fn deref(&self) -> &Self::Target {
314 &self.0
315 }
316}
317#[doc = "Field `CKSEL` writer - SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register."]
318pub struct CKSEL_W<'a> {
319 w: &'a mut W,
320}
321impl<'a> CKSEL_W<'a> {
322 #[doc = r"Writes `variant` to the field"]
323 #[inline(always)]
324 pub fn variant(self, variant: CKSEL_A) -> &'a mut W {
325 unsafe { self.bits(variant.into()) }
326 }
327 #[doc = "Rising edges on input 0."]
328 #[inline(always)]
329 pub fn input_0_rising_edges(self) -> &'a mut W {
330 self.variant(CKSEL_A::INPUT_0_RISING_EDGES)
331 }
332 #[doc = "Falling edges on input 0."]
333 #[inline(always)]
334 pub fn input_0_falling_edge(self) -> &'a mut W {
335 self.variant(CKSEL_A::INPUT_0_FALLING_EDGE)
336 }
337 #[doc = "Rising edges on input 1."]
338 #[inline(always)]
339 pub fn input_1_rising_edges(self) -> &'a mut W {
340 self.variant(CKSEL_A::INPUT_1_RISING_EDGES)
341 }
342 #[doc = "Falling edges on input 1."]
343 #[inline(always)]
344 pub fn input_1_falling_edge(self) -> &'a mut W {
345 self.variant(CKSEL_A::INPUT_1_FALLING_EDGE)
346 }
347 #[doc = "Rising edges on input 2."]
348 #[inline(always)]
349 pub fn input_2_rising_edges(self) -> &'a mut W {
350 self.variant(CKSEL_A::INPUT_2_RISING_EDGES)
351 }
352 #[doc = "Falling edges on input 2."]
353 #[inline(always)]
354 pub fn input_2_falling_edge(self) -> &'a mut W {
355 self.variant(CKSEL_A::INPUT_2_FALLING_EDGE)
356 }
357 #[doc = "Rising edges on input 3."]
358 #[inline(always)]
359 pub fn input_3_rising_edges(self) -> &'a mut W {
360 self.variant(CKSEL_A::INPUT_3_RISING_EDGES)
361 }
362 #[doc = "Falling edges on input 3."]
363 #[inline(always)]
364 pub fn input_3_falling_edge(self) -> &'a mut W {
365 self.variant(CKSEL_A::INPUT_3_FALLING_EDGE)
366 }
367 #[doc = r"Writes raw bits to the field"]
368 #[inline(always)]
369 pub unsafe fn bits(self, value: u8) -> &'a mut W {
370 self.w.bits = (self.w.bits & !(0x0f << 3)) | ((value as u32 & 0x0f) << 3);
371 self.w
372 }
373}
374#[doc = "Field `NORELAOD_L` reader - A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set."]
375pub struct NORELAOD_L_R(crate::FieldReader<bool, bool>);
376impl NORELAOD_L_R {
377 pub(crate) fn new(bits: bool) -> Self {
378 NORELAOD_L_R(crate::FieldReader::new(bits))
379 }
380}
381impl core::ops::Deref for NORELAOD_L_R {
382 type Target = crate::FieldReader<bool, bool>;
383 #[inline(always)]
384 fn deref(&self) -> &Self::Target {
385 &self.0
386 }
387}
388#[doc = "Field `NORELAOD_L` writer - A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set."]
389pub struct NORELAOD_L_W<'a> {
390 w: &'a mut W,
391}
392impl<'a> NORELAOD_L_W<'a> {
393 #[doc = r"Sets the field bit"]
394 #[inline(always)]
395 pub fn set_bit(self) -> &'a mut W {
396 self.bit(true)
397 }
398 #[doc = r"Clears the field bit"]
399 #[inline(always)]
400 pub fn clear_bit(self) -> &'a mut W {
401 self.bit(false)
402 }
403 #[doc = r"Writes raw bits to the field"]
404 #[inline(always)]
405 pub fn bit(self, value: bool) -> &'a mut W {
406 self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
407 self.w
408 }
409}
410#[doc = "Field `NORELOAD_H` reader - A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set."]
411pub struct NORELOAD_H_R(crate::FieldReader<bool, bool>);
412impl NORELOAD_H_R {
413 pub(crate) fn new(bits: bool) -> Self {
414 NORELOAD_H_R(crate::FieldReader::new(bits))
415 }
416}
417impl core::ops::Deref for NORELOAD_H_R {
418 type Target = crate::FieldReader<bool, bool>;
419 #[inline(always)]
420 fn deref(&self) -> &Self::Target {
421 &self.0
422 }
423}
424#[doc = "Field `NORELOAD_H` writer - A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set."]
425pub struct NORELOAD_H_W<'a> {
426 w: &'a mut W,
427}
428impl<'a> NORELOAD_H_W<'a> {
429 #[doc = r"Sets the field bit"]
430 #[inline(always)]
431 pub fn set_bit(self) -> &'a mut W {
432 self.bit(true)
433 }
434 #[doc = r"Clears the field bit"]
435 #[inline(always)]
436 pub fn clear_bit(self) -> &'a mut W {
437 self.bit(false)
438 }
439 #[doc = r"Writes raw bits to the field"]
440 #[inline(always)]
441 pub fn bit(self, value: bool) -> &'a mut W {
442 self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
443 self.w
444 }
445}
446#[doc = "Field `INSYNC` reader - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field."]
447pub struct INSYNC_R(crate::FieldReader<u8, u8>);
448impl INSYNC_R {
449 pub(crate) fn new(bits: u8) -> Self {
450 INSYNC_R(crate::FieldReader::new(bits))
451 }
452}
453impl core::ops::Deref for INSYNC_R {
454 type Target = crate::FieldReader<u8, u8>;
455 #[inline(always)]
456 fn deref(&self) -> &Self::Target {
457 &self.0
458 }
459}
460#[doc = "Field `INSYNC` writer - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field."]
461pub struct INSYNC_W<'a> {
462 w: &'a mut W,
463}
464impl<'a> INSYNC_W<'a> {
465 #[doc = r"Writes raw bits to the field"]
466 #[inline(always)]
467 pub unsafe fn bits(self, value: u8) -> &'a mut W {
468 self.w.bits = (self.w.bits & !(0x0f << 9)) | ((value as u32 & 0x0f) << 9);
469 self.w
470 }
471}
472#[doc = "Field `AUTOLIMIT_L` reader - A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set."]
473pub struct AUTOLIMIT_L_R(crate::FieldReader<bool, bool>);
474impl AUTOLIMIT_L_R {
475 pub(crate) fn new(bits: bool) -> Self {
476 AUTOLIMIT_L_R(crate::FieldReader::new(bits))
477 }
478}
479impl core::ops::Deref for AUTOLIMIT_L_R {
480 type Target = crate::FieldReader<bool, bool>;
481 #[inline(always)]
482 fn deref(&self) -> &Self::Target {
483 &self.0
484 }
485}
486#[doc = "Field `AUTOLIMIT_L` writer - A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set."]
487pub struct AUTOLIMIT_L_W<'a> {
488 w: &'a mut W,
489}
490impl<'a> AUTOLIMIT_L_W<'a> {
491 #[doc = r"Sets the field bit"]
492 #[inline(always)]
493 pub fn set_bit(self) -> &'a mut W {
494 self.bit(true)
495 }
496 #[doc = r"Clears the field bit"]
497 #[inline(always)]
498 pub fn clear_bit(self) -> &'a mut W {
499 self.bit(false)
500 }
501 #[doc = r"Writes raw bits to the field"]
502 #[inline(always)]
503 pub fn bit(self, value: bool) -> &'a mut W {
504 self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17);
505 self.w
506 }
507}
508#[doc = "Field `AUTOLIMIT_H` reader - A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set."]
509pub struct AUTOLIMIT_H_R(crate::FieldReader<bool, bool>);
510impl AUTOLIMIT_H_R {
511 pub(crate) fn new(bits: bool) -> Self {
512 AUTOLIMIT_H_R(crate::FieldReader::new(bits))
513 }
514}
515impl core::ops::Deref for AUTOLIMIT_H_R {
516 type Target = crate::FieldReader<bool, bool>;
517 #[inline(always)]
518 fn deref(&self) -> &Self::Target {
519 &self.0
520 }
521}
522#[doc = "Field `AUTOLIMIT_H` writer - A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set."]
523pub struct AUTOLIMIT_H_W<'a> {
524 w: &'a mut W,
525}
526impl<'a> AUTOLIMIT_H_W<'a> {
527 #[doc = r"Sets the field bit"]
528 #[inline(always)]
529 pub fn set_bit(self) -> &'a mut W {
530 self.bit(true)
531 }
532 #[doc = r"Clears the field bit"]
533 #[inline(always)]
534 pub fn clear_bit(self) -> &'a mut W {
535 self.bit(false)
536 }
537 #[doc = r"Writes raw bits to the field"]
538 #[inline(always)]
539 pub fn bit(self, value: bool) -> &'a mut W {
540 self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18);
541 self.w
542 }
543}
544impl R {
545 #[doc = "Bit 0 - SCT operation"]
546 #[inline(always)]
547 pub fn unify(&self) -> UNIFY_R {
548 UNIFY_R::new((self.bits & 0x01) != 0)
549 }
550 #[doc = "Bits 1:2 - SCT clock mode"]
551 #[inline(always)]
552 pub fn clkmode(&self) -> CLKMODE_R {
553 CLKMODE_R::new(((self.bits >> 1) & 0x03) as u8)
554 }
555 #[doc = "Bits 3:6 - SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register."]
556 #[inline(always)]
557 pub fn cksel(&self) -> CKSEL_R {
558 CKSEL_R::new(((self.bits >> 3) & 0x0f) as u8)
559 }
560 #[doc = "Bit 7 - A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set."]
561 #[inline(always)]
562 pub fn norelaod_l(&self) -> NORELAOD_L_R {
563 NORELAOD_L_R::new(((self.bits >> 7) & 0x01) != 0)
564 }
565 #[doc = "Bit 8 - A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set."]
566 #[inline(always)]
567 pub fn noreload_h(&self) -> NORELOAD_H_R {
568 NORELOAD_H_R::new(((self.bits >> 8) & 0x01) != 0)
569 }
570 #[doc = "Bits 9:12 - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field."]
571 #[inline(always)]
572 pub fn insync(&self) -> INSYNC_R {
573 INSYNC_R::new(((self.bits >> 9) & 0x0f) as u8)
574 }
575 #[doc = "Bit 17 - A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set."]
576 #[inline(always)]
577 pub fn autolimit_l(&self) -> AUTOLIMIT_L_R {
578 AUTOLIMIT_L_R::new(((self.bits >> 17) & 0x01) != 0)
579 }
580 #[doc = "Bit 18 - A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set."]
581 #[inline(always)]
582 pub fn autolimit_h(&self) -> AUTOLIMIT_H_R {
583 AUTOLIMIT_H_R::new(((self.bits >> 18) & 0x01) != 0)
584 }
585}
586impl W {
587 #[doc = "Bit 0 - SCT operation"]
588 #[inline(always)]
589 pub fn unify(&mut self) -> UNIFY_W {
590 UNIFY_W { w: self }
591 }
592 #[doc = "Bits 1:2 - SCT clock mode"]
593 #[inline(always)]
594 pub fn clkmode(&mut self) -> CLKMODE_W {
595 CLKMODE_W { w: self }
596 }
597 #[doc = "Bits 3:6 - SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register."]
598 #[inline(always)]
599 pub fn cksel(&mut self) -> CKSEL_W {
600 CKSEL_W { w: self }
601 }
602 #[doc = "Bit 7 - A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set."]
603 #[inline(always)]
604 pub fn norelaod_l(&mut self) -> NORELAOD_L_W {
605 NORELAOD_L_W { w: self }
606 }
607 #[doc = "Bit 8 - A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set."]
608 #[inline(always)]
609 pub fn noreload_h(&mut self) -> NORELOAD_H_W {
610 NORELOAD_H_W { w: self }
611 }
612 #[doc = "Bits 9:12 - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is known to already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. It does not apply to the clock input specified in the CKSEL field."]
613 #[inline(always)]
614 pub fn insync(&mut self) -> INSYNC_W {
615 INSYNC_W { w: self }
616 }
617 #[doc = "Bit 17 - A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set."]
618 #[inline(always)]
619 pub fn autolimit_l(&mut self) -> AUTOLIMIT_L_W {
620 AUTOLIMIT_L_W { w: self }
621 }
622 #[doc = "Bit 18 - A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in unidirectional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set."]
623 #[inline(always)]
624 pub fn autolimit_h(&mut self) -> AUTOLIMIT_H_W {
625 AUTOLIMIT_H_W { w: self }
626 }
627 #[doc = "Writes raw bits to the register."]
628 #[inline(always)]
629 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
630 self.0.bits(bits);
631 self
632 }
633}
634#[doc = "SCT configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"]
635pub struct CONFIG_SPEC;
636impl crate::RegisterSpec for CONFIG_SPEC {
637 type Ux = u32;
638}
639#[doc = "`read()` method returns [config::R](R) reader structure"]
640impl crate::Readable for CONFIG_SPEC {
641 type Reader = R;
642}
643#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"]
644impl crate::Writable for CONFIG_SPEC {
645 type Writer = W;
646}
647#[doc = "`reset()` method sets CONFIG to value 0x1e00"]
648impl crate::Resettable for CONFIG_SPEC {
649 #[inline(always)]
650 fn reset_value() -> Self::Ux {
651 0x1e00
652 }
653}