lpc82x_pac/mtb_sfr/
master.rs

1#[doc = "Register `MASTER` reader"]
2pub struct R(crate::R<MASTER_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<MASTER_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<MASTER_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<MASTER_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `MASTER` writer"]
17pub struct W(crate::W<MASTER_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<MASTER_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<MASTER_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<MASTER_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `MASK` reader - This value determines the maximum size of the trace buffer in SRAM. It specifies the most-significant bit of the POSITION.POINTER field that can be updated by automatic increment. If the trace tries to advance past this power of two, the POSITION.WRAP bit is set to 1, the POSITION.POINTER\\[MASK:0\\]
38bits are set to zero, and the POSITION.POINTER\\[AWIDTH-4:MASK+1\\]
39bits remain unchanged. This field causes the trace packet information to be stored in a circular buffer of size 2(MASK+4) bytes, that can be positioned in memory at multiples of this size. Valid values of this field are zero to AWIDTH-4. Values greater than the maximum have the same effect as the maximum."]
40pub struct MASK_R(crate::FieldReader<u8, u8>);
41impl MASK_R {
42    pub(crate) fn new(bits: u8) -> Self {
43        MASK_R(crate::FieldReader::new(bits))
44    }
45}
46impl core::ops::Deref for MASK_R {
47    type Target = crate::FieldReader<u8, u8>;
48    #[inline(always)]
49    fn deref(&self) -> &Self::Target {
50        &self.0
51    }
52}
53#[doc = "Field `MASK` writer - This value determines the maximum size of the trace buffer in SRAM. It specifies the most-significant bit of the POSITION.POINTER field that can be updated by automatic increment. If the trace tries to advance past this power of two, the POSITION.WRAP bit is set to 1, the POSITION.POINTER\\[MASK:0\\]
54bits are set to zero, and the POSITION.POINTER\\[AWIDTH-4:MASK+1\\]
55bits remain unchanged. This field causes the trace packet information to be stored in a circular buffer of size 2(MASK+4) bytes, that can be positioned in memory at multiples of this size. Valid values of this field are zero to AWIDTH-4. Values greater than the maximum have the same effect as the maximum."]
56pub struct MASK_W<'a> {
57    w: &'a mut W,
58}
59impl<'a> MASK_W<'a> {
60    #[doc = r"Writes raw bits to the field"]
61    #[inline(always)]
62    pub unsafe fn bits(self, value: u8) -> &'a mut W {
63        self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f);
64        self.w
65    }
66}
67#[doc = "Field `TSTARTEN` reader - Trace start input enable. If this bit is 1 and the TSTART signal is HIGH, then the EN bit is set to 1. Tracing continues until a stop condition occurs."]
68pub struct TSTARTEN_R(crate::FieldReader<bool, bool>);
69impl TSTARTEN_R {
70    pub(crate) fn new(bits: bool) -> Self {
71        TSTARTEN_R(crate::FieldReader::new(bits))
72    }
73}
74impl core::ops::Deref for TSTARTEN_R {
75    type Target = crate::FieldReader<bool, bool>;
76    #[inline(always)]
77    fn deref(&self) -> &Self::Target {
78        &self.0
79    }
80}
81#[doc = "Field `TSTARTEN` writer - Trace start input enable. If this bit is 1 and the TSTART signal is HIGH, then the EN bit is set to 1. Tracing continues until a stop condition occurs."]
82pub struct TSTARTEN_W<'a> {
83    w: &'a mut W,
84}
85impl<'a> TSTARTEN_W<'a> {
86    #[doc = r"Sets the field bit"]
87    #[inline(always)]
88    pub fn set_bit(self) -> &'a mut W {
89        self.bit(true)
90    }
91    #[doc = r"Clears the field bit"]
92    #[inline(always)]
93    pub fn clear_bit(self) -> &'a mut W {
94        self.bit(false)
95    }
96    #[doc = r"Writes raw bits to the field"]
97    #[inline(always)]
98    pub fn bit(self, value: bool) -> &'a mut W {
99        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
100        self.w
101    }
102}
103#[doc = "Field `TSTOPEN` reader - Trace stop input enable. If this bit is 1 and the TSTOP signal is HIGH, then the EN bit is set to 0. If a trace packet is being written to memory, the write is completed before tracing is stopped."]
104pub struct TSTOPEN_R(crate::FieldReader<bool, bool>);
105impl TSTOPEN_R {
106    pub(crate) fn new(bits: bool) -> Self {
107        TSTOPEN_R(crate::FieldReader::new(bits))
108    }
109}
110impl core::ops::Deref for TSTOPEN_R {
111    type Target = crate::FieldReader<bool, bool>;
112    #[inline(always)]
113    fn deref(&self) -> &Self::Target {
114        &self.0
115    }
116}
117#[doc = "Field `TSTOPEN` writer - Trace stop input enable. If this bit is 1 and the TSTOP signal is HIGH, then the EN bit is set to 0. If a trace packet is being written to memory, the write is completed before tracing is stopped."]
118pub struct TSTOPEN_W<'a> {
119    w: &'a mut W,
120}
121impl<'a> TSTOPEN_W<'a> {
122    #[doc = r"Sets the field bit"]
123    #[inline(always)]
124    pub fn set_bit(self) -> &'a mut W {
125        self.bit(true)
126    }
127    #[doc = r"Clears the field bit"]
128    #[inline(always)]
129    pub fn clear_bit(self) -> &'a mut W {
130        self.bit(false)
131    }
132    #[doc = r"Writes raw bits to the field"]
133    #[inline(always)]
134    pub fn bit(self, value: bool) -> &'a mut W {
135        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
136        self.w
137    }
138}
139#[doc = "Field `SFRWPRIV` reader - Special Function Register Write Privilege bit. If this bit is 0, then User or Privileged AHB-Lite read and write accesses to the Special Function Registers are permitted. If this bit is 1, then only Privileged write accesses are permitted and User write accesses are ignored. The HPROT\\[1\\]
140signal determines if an access is User or Privileged."]
141pub struct SFRWPRIV_R(crate::FieldReader<bool, bool>);
142impl SFRWPRIV_R {
143    pub(crate) fn new(bits: bool) -> Self {
144        SFRWPRIV_R(crate::FieldReader::new(bits))
145    }
146}
147impl core::ops::Deref for SFRWPRIV_R {
148    type Target = crate::FieldReader<bool, bool>;
149    #[inline(always)]
150    fn deref(&self) -> &Self::Target {
151        &self.0
152    }
153}
154#[doc = "Field `SFRWPRIV` writer - Special Function Register Write Privilege bit. If this bit is 0, then User or Privileged AHB-Lite read and write accesses to the Special Function Registers are permitted. If this bit is 1, then only Privileged write accesses are permitted and User write accesses are ignored. The HPROT\\[1\\]
155signal determines if an access is User or Privileged."]
156pub struct SFRWPRIV_W<'a> {
157    w: &'a mut W,
158}
159impl<'a> SFRWPRIV_W<'a> {
160    #[doc = r"Sets the field bit"]
161    #[inline(always)]
162    pub fn set_bit(self) -> &'a mut W {
163        self.bit(true)
164    }
165    #[doc = r"Clears the field bit"]
166    #[inline(always)]
167    pub fn clear_bit(self) -> &'a mut W {
168        self.bit(false)
169    }
170    #[doc = r"Writes raw bits to the field"]
171    #[inline(always)]
172    pub fn bit(self, value: bool) -> &'a mut W {
173        self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
174        self.w
175    }
176}
177#[doc = "Field `RAMPRIV` reader - SRAM Privilege bit. If this bit is 0, then User or Privileged AHB-Lite read and write accesses to the SRAM are permitted. If this bit is 1, then only Privileged AHB-Lite read and write accesses to the SRAM are permitted and User accesses are RAZ/WI. The HPROT\\[1\\]
178signal determines if an access is User or Privileged."]
179pub struct RAMPRIV_R(crate::FieldReader<bool, bool>);
180impl RAMPRIV_R {
181    pub(crate) fn new(bits: bool) -> Self {
182        RAMPRIV_R(crate::FieldReader::new(bits))
183    }
184}
185impl core::ops::Deref for RAMPRIV_R {
186    type Target = crate::FieldReader<bool, bool>;
187    #[inline(always)]
188    fn deref(&self) -> &Self::Target {
189        &self.0
190    }
191}
192#[doc = "Field `RAMPRIV` writer - SRAM Privilege bit. If this bit is 0, then User or Privileged AHB-Lite read and write accesses to the SRAM are permitted. If this bit is 1, then only Privileged AHB-Lite read and write accesses to the SRAM are permitted and User accesses are RAZ/WI. The HPROT\\[1\\]
193signal determines if an access is User or Privileged."]
194pub struct RAMPRIV_W<'a> {
195    w: &'a mut W,
196}
197impl<'a> RAMPRIV_W<'a> {
198    #[doc = r"Sets the field bit"]
199    #[inline(always)]
200    pub fn set_bit(self) -> &'a mut W {
201        self.bit(true)
202    }
203    #[doc = r"Clears the field bit"]
204    #[inline(always)]
205    pub fn clear_bit(self) -> &'a mut W {
206        self.bit(false)
207    }
208    #[doc = r"Writes raw bits to the field"]
209    #[inline(always)]
210    pub fn bit(self, value: bool) -> &'a mut W {
211        self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
212        self.w
213    }
214}
215#[doc = "Field `HALTREQ` reader - Halt request bit. This bit is connected to the halt request signal of the trace logic, EDBGRQ. When HALTREQ is set to 1, EDBGRQ is asserted if DBGEN is also HIGH. The HALTREQ bit can be automatically set to 1 using the FLOW.WATERMARK field."]
216pub struct HALTREQ_R(crate::FieldReader<bool, bool>);
217impl HALTREQ_R {
218    pub(crate) fn new(bits: bool) -> Self {
219        HALTREQ_R(crate::FieldReader::new(bits))
220    }
221}
222impl core::ops::Deref for HALTREQ_R {
223    type Target = crate::FieldReader<bool, bool>;
224    #[inline(always)]
225    fn deref(&self) -> &Self::Target {
226        &self.0
227    }
228}
229#[doc = "Field `HALTREQ` writer - Halt request bit. This bit is connected to the halt request signal of the trace logic, EDBGRQ. When HALTREQ is set to 1, EDBGRQ is asserted if DBGEN is also HIGH. The HALTREQ bit can be automatically set to 1 using the FLOW.WATERMARK field."]
230pub struct HALTREQ_W<'a> {
231    w: &'a mut W,
232}
233impl<'a> HALTREQ_W<'a> {
234    #[doc = r"Sets the field bit"]
235    #[inline(always)]
236    pub fn set_bit(self) -> &'a mut W {
237        self.bit(true)
238    }
239    #[doc = r"Clears the field bit"]
240    #[inline(always)]
241    pub fn clear_bit(self) -> &'a mut W {
242        self.bit(false)
243    }
244    #[doc = r"Writes raw bits to the field"]
245    #[inline(always)]
246    pub fn bit(self, value: bool) -> &'a mut W {
247        self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
248        self.w
249    }
250}
251#[doc = "Field `EN` reader - Main trace enable bit. When this bit is 1 trace data is written into the SRAM memory location addressed by POSITION.POINTER. The POSITION.POINTER value auto increments after the trace data packet is written. The EN bit can be automatically set to 0 using the FLOW.WATERMARK field and the FLOW.AUTOSTOP bit. The EN bit is automatically set to 1 if the TSTARTEN bit is 1 and the TSTART signal is HIGH. The EN bit is automatically set to 0 if TSTOPEN bit is 1 and the TSTOP signal is HIGH."]
252pub struct EN_R(crate::FieldReader<bool, bool>);
253impl EN_R {
254    pub(crate) fn new(bits: bool) -> Self {
255        EN_R(crate::FieldReader::new(bits))
256    }
257}
258impl core::ops::Deref for EN_R {
259    type Target = crate::FieldReader<bool, bool>;
260    #[inline(always)]
261    fn deref(&self) -> &Self::Target {
262        &self.0
263    }
264}
265#[doc = "Field `EN` writer - Main trace enable bit. When this bit is 1 trace data is written into the SRAM memory location addressed by POSITION.POINTER. The POSITION.POINTER value auto increments after the trace data packet is written. The EN bit can be automatically set to 0 using the FLOW.WATERMARK field and the FLOW.AUTOSTOP bit. The EN bit is automatically set to 1 if the TSTARTEN bit is 1 and the TSTART signal is HIGH. The EN bit is automatically set to 0 if TSTOPEN bit is 1 and the TSTOP signal is HIGH."]
266pub struct EN_W<'a> {
267    w: &'a mut W,
268}
269impl<'a> EN_W<'a> {
270    #[doc = r"Sets the field bit"]
271    #[inline(always)]
272    pub fn set_bit(self) -> &'a mut W {
273        self.bit(true)
274    }
275    #[doc = r"Clears the field bit"]
276    #[inline(always)]
277    pub fn clear_bit(self) -> &'a mut W {
278        self.bit(false)
279    }
280    #[doc = r"Writes raw bits to the field"]
281    #[inline(always)]
282    pub fn bit(self, value: bool) -> &'a mut W {
283        self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
284        self.w
285    }
286}
287impl R {
288    #[doc = "Bits 0:4 - This value determines the maximum size of the trace buffer in SRAM. It specifies the most-significant bit of the POSITION.POINTER field that can be updated by automatic increment. If the trace tries to advance past this power of two, the POSITION.WRAP bit is set to 1, the POSITION.POINTER\\[MASK:0\\]
289bits are set to zero, and the POSITION.POINTER\\[AWIDTH-4:MASK+1\\]
290bits remain unchanged. This field causes the trace packet information to be stored in a circular buffer of size 2(MASK+4) bytes, that can be positioned in memory at multiples of this size. Valid values of this field are zero to AWIDTH-4. Values greater than the maximum have the same effect as the maximum."]
291    #[inline(always)]
292    pub fn mask(&self) -> MASK_R {
293        MASK_R::new((self.bits & 0x1f) as u8)
294    }
295    #[doc = "Bit 5 - Trace start input enable. If this bit is 1 and the TSTART signal is HIGH, then the EN bit is set to 1. Tracing continues until a stop condition occurs."]
296    #[inline(always)]
297    pub fn tstarten(&self) -> TSTARTEN_R {
298        TSTARTEN_R::new(((self.bits >> 5) & 0x01) != 0)
299    }
300    #[doc = "Bit 6 - Trace stop input enable. If this bit is 1 and the TSTOP signal is HIGH, then the EN bit is set to 0. If a trace packet is being written to memory, the write is completed before tracing is stopped."]
301    #[inline(always)]
302    pub fn tstopen(&self) -> TSTOPEN_R {
303        TSTOPEN_R::new(((self.bits >> 6) & 0x01) != 0)
304    }
305    #[doc = "Bit 7 - Special Function Register Write Privilege bit. If this bit is 0, then User or Privileged AHB-Lite read and write accesses to the Special Function Registers are permitted. If this bit is 1, then only Privileged write accesses are permitted and User write accesses are ignored. The HPROT\\[1\\]
306signal determines if an access is User or Privileged."]
307    #[inline(always)]
308    pub fn sfrwpriv(&self) -> SFRWPRIV_R {
309        SFRWPRIV_R::new(((self.bits >> 7) & 0x01) != 0)
310    }
311    #[doc = "Bit 8 - SRAM Privilege bit. If this bit is 0, then User or Privileged AHB-Lite read and write accesses to the SRAM are permitted. If this bit is 1, then only Privileged AHB-Lite read and write accesses to the SRAM are permitted and User accesses are RAZ/WI. The HPROT\\[1\\]
312signal determines if an access is User or Privileged."]
313    #[inline(always)]
314    pub fn rampriv(&self) -> RAMPRIV_R {
315        RAMPRIV_R::new(((self.bits >> 8) & 0x01) != 0)
316    }
317    #[doc = "Bit 9 - Halt request bit. This bit is connected to the halt request signal of the trace logic, EDBGRQ. When HALTREQ is set to 1, EDBGRQ is asserted if DBGEN is also HIGH. The HALTREQ bit can be automatically set to 1 using the FLOW.WATERMARK field."]
318    #[inline(always)]
319    pub fn haltreq(&self) -> HALTREQ_R {
320        HALTREQ_R::new(((self.bits >> 9) & 0x01) != 0)
321    }
322    #[doc = "Bit 31 - Main trace enable bit. When this bit is 1 trace data is written into the SRAM memory location addressed by POSITION.POINTER. The POSITION.POINTER value auto increments after the trace data packet is written. The EN bit can be automatically set to 0 using the FLOW.WATERMARK field and the FLOW.AUTOSTOP bit. The EN bit is automatically set to 1 if the TSTARTEN bit is 1 and the TSTART signal is HIGH. The EN bit is automatically set to 0 if TSTOPEN bit is 1 and the TSTOP signal is HIGH."]
323    #[inline(always)]
324    pub fn en(&self) -> EN_R {
325        EN_R::new(((self.bits >> 31) & 0x01) != 0)
326    }
327}
328impl W {
329    #[doc = "Bits 0:4 - This value determines the maximum size of the trace buffer in SRAM. It specifies the most-significant bit of the POSITION.POINTER field that can be updated by automatic increment. If the trace tries to advance past this power of two, the POSITION.WRAP bit is set to 1, the POSITION.POINTER\\[MASK:0\\]
330bits are set to zero, and the POSITION.POINTER\\[AWIDTH-4:MASK+1\\]
331bits remain unchanged. This field causes the trace packet information to be stored in a circular buffer of size 2(MASK+4) bytes, that can be positioned in memory at multiples of this size. Valid values of this field are zero to AWIDTH-4. Values greater than the maximum have the same effect as the maximum."]
332    #[inline(always)]
333    pub fn mask(&mut self) -> MASK_W {
334        MASK_W { w: self }
335    }
336    #[doc = "Bit 5 - Trace start input enable. If this bit is 1 and the TSTART signal is HIGH, then the EN bit is set to 1. Tracing continues until a stop condition occurs."]
337    #[inline(always)]
338    pub fn tstarten(&mut self) -> TSTARTEN_W {
339        TSTARTEN_W { w: self }
340    }
341    #[doc = "Bit 6 - Trace stop input enable. If this bit is 1 and the TSTOP signal is HIGH, then the EN bit is set to 0. If a trace packet is being written to memory, the write is completed before tracing is stopped."]
342    #[inline(always)]
343    pub fn tstopen(&mut self) -> TSTOPEN_W {
344        TSTOPEN_W { w: self }
345    }
346    #[doc = "Bit 7 - Special Function Register Write Privilege bit. If this bit is 0, then User or Privileged AHB-Lite read and write accesses to the Special Function Registers are permitted. If this bit is 1, then only Privileged write accesses are permitted and User write accesses are ignored. The HPROT\\[1\\]
347signal determines if an access is User or Privileged."]
348    #[inline(always)]
349    pub fn sfrwpriv(&mut self) -> SFRWPRIV_W {
350        SFRWPRIV_W { w: self }
351    }
352    #[doc = "Bit 8 - SRAM Privilege bit. If this bit is 0, then User or Privileged AHB-Lite read and write accesses to the SRAM are permitted. If this bit is 1, then only Privileged AHB-Lite read and write accesses to the SRAM are permitted and User accesses are RAZ/WI. The HPROT\\[1\\]
353signal determines if an access is User or Privileged."]
354    #[inline(always)]
355    pub fn rampriv(&mut self) -> RAMPRIV_W {
356        RAMPRIV_W { w: self }
357    }
358    #[doc = "Bit 9 - Halt request bit. This bit is connected to the halt request signal of the trace logic, EDBGRQ. When HALTREQ is set to 1, EDBGRQ is asserted if DBGEN is also HIGH. The HALTREQ bit can be automatically set to 1 using the FLOW.WATERMARK field."]
359    #[inline(always)]
360    pub fn haltreq(&mut self) -> HALTREQ_W {
361        HALTREQ_W { w: self }
362    }
363    #[doc = "Bit 31 - Main trace enable bit. When this bit is 1 trace data is written into the SRAM memory location addressed by POSITION.POINTER. The POSITION.POINTER value auto increments after the trace data packet is written. The EN bit can be automatically set to 0 using the FLOW.WATERMARK field and the FLOW.AUTOSTOP bit. The EN bit is automatically set to 1 if the TSTARTEN bit is 1 and the TSTART signal is HIGH. The EN bit is automatically set to 0 if TSTOPEN bit is 1 and the TSTOP signal is HIGH."]
364    #[inline(always)]
365    pub fn en(&mut self) -> EN_W {
366        EN_W { w: self }
367    }
368    #[doc = "Writes raw bits to the register."]
369    #[inline(always)]
370    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
371        self.0.bits(bits);
372        self
373    }
374}
375#[doc = "MASTER Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [master](index.html) module"]
376pub struct MASTER_SPEC;
377impl crate::RegisterSpec for MASTER_SPEC {
378    type Ux = u32;
379}
380#[doc = "`read()` method returns [master::R](R) reader structure"]
381impl crate::Readable for MASTER_SPEC {
382    type Reader = R;
383}
384#[doc = "`write(|w| ..)` method takes [master::W](W) writer structure"]
385impl crate::Writable for MASTER_SPEC {
386    type Writer = W;
387}
388#[doc = "`reset()` method sets MASTER to value 0x80"]
389impl crate::Resettable for MASTER_SPEC {
390    #[inline(always)]
391    fn reset_value() -> Self::Ux {
392        0x80
393    }
394}
lpc82x_pac/mtb_sfr/master.rs

lpc82x_pac/mtb_sfr/
master.rs
