lpc82x_pac/inputmux/
sct0_inmux.rs

1#[doc = "Register `SCT0_INMUX[%s]` reader"]
2pub struct R(crate::R<SCT0_INMUX_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SCT0_INMUX_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SCT0_INMUX_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SCT0_INMUX_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SCT0_INMUX[%s]` writer"]
17pub struct W(crate::W<SCT0_INMUX_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SCT0_INMUX_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SCT0_INMUX_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SCT0_INMUX_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Input mux register for SCT input n (n = 0 to 3). 0 = sct input 0 1=sct input 1 2= sct input 2 3= sct input 3 4= adc_thcmp_irq 5 = comparator out 6=arm_txev 7=debug_halted\n\nValue on reset: 15"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum INP_N_A {
41    #[doc = "0: SCT_PIN0"]
42    SCT_PIN0 = 0,
43    #[doc = "1: SCT_PIN1"]
44    SCT_PIN1 = 1,
45    #[doc = "2: SCT_PIN2"]
46    SCT_PIN2 = 2,
47    #[doc = "3: SCT_PIN3"]
48    SCT_PIN3 = 3,
49    #[doc = "4: ADC_THCMP_IRQ"]
50    ADC_THCMP_IRQ = 4,
51    #[doc = "5: ACMP_O"]
52    ACMP_O = 5,
53    #[doc = "6: ARM_TXEV"]
54    ARM_TXEV = 6,
55    #[doc = "7: DEBUG_HALTED"]
56    DEBUG_HALTED = 7,
57}
58impl From<INP_N_A> for u8 {
59    #[inline(always)]
60    fn from(variant: INP_N_A) -> Self {
61        variant as _
62    }
63}
64#[doc = "Field `INP_N` reader - Input mux register for SCT input n (n = 0 to 3). 0 = sct input 0 1=sct input 1 2= sct input 2 3= sct input 3 4= adc_thcmp_irq 5 = comparator out 6=arm_txev 7=debug_halted"]
65pub struct INP_N_R(crate::FieldReader<u8, INP_N_A>);
66impl INP_N_R {
67    pub(crate) fn new(bits: u8) -> Self {
68        INP_N_R(crate::FieldReader::new(bits))
69    }
70    #[doc = r"Get enumerated values variant"]
71    #[inline(always)]
72    pub fn variant(&self) -> Option<INP_N_A> {
73        match self.bits {
74            0 => Some(INP_N_A::SCT_PIN0),
75            1 => Some(INP_N_A::SCT_PIN1),
76            2 => Some(INP_N_A::SCT_PIN2),
77            3 => Some(INP_N_A::SCT_PIN3),
78            4 => Some(INP_N_A::ADC_THCMP_IRQ),
79            5 => Some(INP_N_A::ACMP_O),
80            6 => Some(INP_N_A::ARM_TXEV),
81            7 => Some(INP_N_A::DEBUG_HALTED),
82            _ => None,
83        }
84    }
85    #[doc = "Checks if the value of the field is `SCT_PIN0`"]
86    #[inline(always)]
87    pub fn is_sct_pin0(&self) -> bool {
88        **self == INP_N_A::SCT_PIN0
89    }
90    #[doc = "Checks if the value of the field is `SCT_PIN1`"]
91    #[inline(always)]
92    pub fn is_sct_pin1(&self) -> bool {
93        **self == INP_N_A::SCT_PIN1
94    }
95    #[doc = "Checks if the value of the field is `SCT_PIN2`"]
96    #[inline(always)]
97    pub fn is_sct_pin2(&self) -> bool {
98        **self == INP_N_A::SCT_PIN2
99    }
100    #[doc = "Checks if the value of the field is `SCT_PIN3`"]
101    #[inline(always)]
102    pub fn is_sct_pin3(&self) -> bool {
103        **self == INP_N_A::SCT_PIN3
104    }
105    #[doc = "Checks if the value of the field is `ADC_THCMP_IRQ`"]
106    #[inline(always)]
107    pub fn is_adc_thcmp_irq(&self) -> bool {
108        **self == INP_N_A::ADC_THCMP_IRQ
109    }
110    #[doc = "Checks if the value of the field is `ACMP_O`"]
111    #[inline(always)]
112    pub fn is_acmp_o(&self) -> bool {
113        **self == INP_N_A::ACMP_O
114    }
115    #[doc = "Checks if the value of the field is `ARM_TXEV`"]
116    #[inline(always)]
117    pub fn is_arm_txev(&self) -> bool {
118        **self == INP_N_A::ARM_TXEV
119    }
120    #[doc = "Checks if the value of the field is `DEBUG_HALTED`"]
121    #[inline(always)]
122    pub fn is_debug_halted(&self) -> bool {
123        **self == INP_N_A::DEBUG_HALTED
124    }
125}
126impl core::ops::Deref for INP_N_R {
127    type Target = crate::FieldReader<u8, INP_N_A>;
128    #[inline(always)]
129    fn deref(&self) -> &Self::Target {
130        &self.0
131    }
132}
133#[doc = "Field `INP_N` writer - Input mux register for SCT input n (n = 0 to 3). 0 = sct input 0 1=sct input 1 2= sct input 2 3= sct input 3 4= adc_thcmp_irq 5 = comparator out 6=arm_txev 7=debug_halted"]
134pub struct INP_N_W<'a> {
135    w: &'a mut W,
136}
137impl<'a> INP_N_W<'a> {
138    #[doc = r"Writes `variant` to the field"]
139    #[inline(always)]
140    pub fn variant(self, variant: INP_N_A) -> &'a mut W {
141        unsafe { self.bits(variant.into()) }
142    }
143    #[doc = "SCT_PIN0"]
144    #[inline(always)]
145    pub fn sct_pin0(self) -> &'a mut W {
146        self.variant(INP_N_A::SCT_PIN0)
147    }
148    #[doc = "SCT_PIN1"]
149    #[inline(always)]
150    pub fn sct_pin1(self) -> &'a mut W {
151        self.variant(INP_N_A::SCT_PIN1)
152    }
153    #[doc = "SCT_PIN2"]
154    #[inline(always)]
155    pub fn sct_pin2(self) -> &'a mut W {
156        self.variant(INP_N_A::SCT_PIN2)
157    }
158    #[doc = "SCT_PIN3"]
159    #[inline(always)]
160    pub fn sct_pin3(self) -> &'a mut W {
161        self.variant(INP_N_A::SCT_PIN3)
162    }
163    #[doc = "ADC_THCMP_IRQ"]
164    #[inline(always)]
165    pub fn adc_thcmp_irq(self) -> &'a mut W {
166        self.variant(INP_N_A::ADC_THCMP_IRQ)
167    }
168    #[doc = "ACMP_O"]
169    #[inline(always)]
170    pub fn acmp_o(self) -> &'a mut W {
171        self.variant(INP_N_A::ACMP_O)
172    }
173    #[doc = "ARM_TXEV"]
174    #[inline(always)]
175    pub fn arm_txev(self) -> &'a mut W {
176        self.variant(INP_N_A::ARM_TXEV)
177    }
178    #[doc = "DEBUG_HALTED"]
179    #[inline(always)]
180    pub fn debug_halted(self) -> &'a mut W {
181        self.variant(INP_N_A::DEBUG_HALTED)
182    }
183    #[doc = r"Writes raw bits to the field"]
184    #[inline(always)]
185    pub unsafe fn bits(self, value: u8) -> &'a mut W {
186        self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f);
187        self.w
188    }
189}
190impl R {
191    #[doc = "Bits 0:3 - Input mux register for SCT input n (n = 0 to 3). 0 = sct input 0 1=sct input 1 2= sct input 2 3= sct input 3 4= adc_thcmp_irq 5 = comparator out 6=arm_txev 7=debug_halted"]
192    #[inline(always)]
193    pub fn inp_n(&self) -> INP_N_R {
194        INP_N_R::new((self.bits & 0x0f) as u8)
195    }
196}
197impl W {
198    #[doc = "Bits 0:3 - Input mux register for SCT input n (n = 0 to 3). 0 = sct input 0 1=sct input 1 2= sct input 2 3= sct input 3 4= adc_thcmp_irq 5 = comparator out 6=arm_txev 7=debug_halted"]
199    #[inline(always)]
200    pub fn inp_n(&mut self) -> INP_N_W {
201        INP_N_W { w: self }
202    }
203    #[doc = "Writes raw bits to the register."]
204    #[inline(always)]
205    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
206        self.0.bits(bits);
207        self
208    }
209}
210#[doc = "input select register for SCT\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sct0_inmux](index.html) module"]
211pub struct SCT0_INMUX_SPEC;
212impl crate::RegisterSpec for SCT0_INMUX_SPEC {
213    type Ux = u32;
214}
215#[doc = "`read()` method returns [sct0_inmux::R](R) reader structure"]
216impl crate::Readable for SCT0_INMUX_SPEC {
217    type Reader = R;
218}
219#[doc = "`write(|w| ..)` method takes [sct0_inmux::W](W) writer structure"]
220impl crate::Writable for SCT0_INMUX_SPEC {
221    type Writer = W;
222}
223#[doc = "`reset()` method sets SCT0_INMUX[%s]
224to value 0x0f"]
225impl crate::Resettable for SCT0_INMUX_SPEC {
226    #[inline(always)]
227    fn reset_value() -> Self::Ux {
228        0x0f
229    }
230}
lpc82x_pac/inputmux/sct0_inmux.rs

lpc82x_pac/inputmux/
sct0_inmux.rs
