lpc82x_pac/inputmux/
dma_itrig_inmux.rs

1#[doc = "Register `DMA_ITRIG_INMUX[%s]` reader"]
2pub struct R(crate::R<DMA_ITRIG_INMUX_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DMA_ITRIG_INMUX_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DMA_ITRIG_INMUX_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DMA_ITRIG_INMUX_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DMA_ITRIG_INMUX[%s]` writer"]
17pub struct W(crate::W<DMA_ITRIG_INMUX_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DMA_ITRIG_INMUX_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DMA_ITRIG_INMUX_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DMA_ITRIG_INMUX_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Input mux register for trigger inputs 0 to 23 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin interrupts, and DMA requests.\n\nValue on reset: 15"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum INP_A {
41    #[doc = "0: ADC_SEQA_IRQ"]
42    ADC_SEQA_IRQ = 0,
43    #[doc = "1: ADC_SEQB_IRQ"]
44    ADC_SEQB_IRQ = 1,
45    #[doc = "2: SCT_DMA0"]
46    SCT_DMA0 = 2,
47    #[doc = "3: SCT_DMA1"]
48    SCT_DMA1 = 3,
49    #[doc = "4: ACMP_O"]
50    ACMP_O = 4,
51    #[doc = "5: PININT0"]
52    PININT0 = 5,
53    #[doc = "6: PININT1"]
54    PININT1 = 6,
55    #[doc = "7: DMA trigger mux 0"]
56    DMA_INMUX_INMUX0 = 7,
57    #[doc = "8: DMA trigger mux 1"]
58    DMA_INMUX_INMUX1 = 8,
59}
60impl From<INP_A> for u8 {
61    #[inline(always)]
62    fn from(variant: INP_A) -> Self {
63        variant as _
64    }
65}
66#[doc = "Field `INP` reader - Input mux register for trigger inputs 0 to 23 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin interrupts, and DMA requests."]
67pub struct INP_R(crate::FieldReader<u8, INP_A>);
68impl INP_R {
69    pub(crate) fn new(bits: u8) -> Self {
70        INP_R(crate::FieldReader::new(bits))
71    }
72    #[doc = r"Get enumerated values variant"]
73    #[inline(always)]
74    pub fn variant(&self) -> Option<INP_A> {
75        match self.bits {
76            0 => Some(INP_A::ADC_SEQA_IRQ),
77            1 => Some(INP_A::ADC_SEQB_IRQ),
78            2 => Some(INP_A::SCT_DMA0),
79            3 => Some(INP_A::SCT_DMA1),
80            4 => Some(INP_A::ACMP_O),
81            5 => Some(INP_A::PININT0),
82            6 => Some(INP_A::PININT1),
83            7 => Some(INP_A::DMA_INMUX_INMUX0),
84            8 => Some(INP_A::DMA_INMUX_INMUX1),
85            _ => None,
86        }
87    }
88    #[doc = "Checks if the value of the field is `ADC_SEQA_IRQ`"]
89    #[inline(always)]
90    pub fn is_adc_seqa_irq(&self) -> bool {
91        **self == INP_A::ADC_SEQA_IRQ
92    }
93    #[doc = "Checks if the value of the field is `ADC_SEQB_IRQ`"]
94    #[inline(always)]
95    pub fn is_adc_seqb_irq(&self) -> bool {
96        **self == INP_A::ADC_SEQB_IRQ
97    }
98    #[doc = "Checks if the value of the field is `SCT_DMA0`"]
99    #[inline(always)]
100    pub fn is_sct_dma0(&self) -> bool {
101        **self == INP_A::SCT_DMA0
102    }
103    #[doc = "Checks if the value of the field is `SCT_DMA1`"]
104    #[inline(always)]
105    pub fn is_sct_dma1(&self) -> bool {
106        **self == INP_A::SCT_DMA1
107    }
108    #[doc = "Checks if the value of the field is `ACMP_O`"]
109    #[inline(always)]
110    pub fn is_acmp_o(&self) -> bool {
111        **self == INP_A::ACMP_O
112    }
113    #[doc = "Checks if the value of the field is `PININT0`"]
114    #[inline(always)]
115    pub fn is_pinint0(&self) -> bool {
116        **self == INP_A::PININT0
117    }
118    #[doc = "Checks if the value of the field is `PININT1`"]
119    #[inline(always)]
120    pub fn is_pinint1(&self) -> bool {
121        **self == INP_A::PININT1
122    }
123    #[doc = "Checks if the value of the field is `DMA_INMUX_INMUX0`"]
124    #[inline(always)]
125    pub fn is_dma_inmux_inmux0(&self) -> bool {
126        **self == INP_A::DMA_INMUX_INMUX0
127    }
128    #[doc = "Checks if the value of the field is `DMA_INMUX_INMUX1`"]
129    #[inline(always)]
130    pub fn is_dma_inmux_inmux1(&self) -> bool {
131        **self == INP_A::DMA_INMUX_INMUX1
132    }
133}
134impl core::ops::Deref for INP_R {
135    type Target = crate::FieldReader<u8, INP_A>;
136    #[inline(always)]
137    fn deref(&self) -> &Self::Target {
138        &self.0
139    }
140}
141#[doc = "Field `INP` writer - Input mux register for trigger inputs 0 to 23 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin interrupts, and DMA requests."]
142pub struct INP_W<'a> {
143    w: &'a mut W,
144}
145impl<'a> INP_W<'a> {
146    #[doc = r"Writes `variant` to the field"]
147    #[inline(always)]
148    pub fn variant(self, variant: INP_A) -> &'a mut W {
149        unsafe { self.bits(variant.into()) }
150    }
151    #[doc = "ADC_SEQA_IRQ"]
152    #[inline(always)]
153    pub fn adc_seqa_irq(self) -> &'a mut W {
154        self.variant(INP_A::ADC_SEQA_IRQ)
155    }
156    #[doc = "ADC_SEQB_IRQ"]
157    #[inline(always)]
158    pub fn adc_seqb_irq(self) -> &'a mut W {
159        self.variant(INP_A::ADC_SEQB_IRQ)
160    }
161    #[doc = "SCT_DMA0"]
162    #[inline(always)]
163    pub fn sct_dma0(self) -> &'a mut W {
164        self.variant(INP_A::SCT_DMA0)
165    }
166    #[doc = "SCT_DMA1"]
167    #[inline(always)]
168    pub fn sct_dma1(self) -> &'a mut W {
169        self.variant(INP_A::SCT_DMA1)
170    }
171    #[doc = "ACMP_O"]
172    #[inline(always)]
173    pub fn acmp_o(self) -> &'a mut W {
174        self.variant(INP_A::ACMP_O)
175    }
176    #[doc = "PININT0"]
177    #[inline(always)]
178    pub fn pinint0(self) -> &'a mut W {
179        self.variant(INP_A::PININT0)
180    }
181    #[doc = "PININT1"]
182    #[inline(always)]
183    pub fn pinint1(self) -> &'a mut W {
184        self.variant(INP_A::PININT1)
185    }
186    #[doc = "DMA trigger mux 0"]
187    #[inline(always)]
188    pub fn dma_inmux_inmux0(self) -> &'a mut W {
189        self.variant(INP_A::DMA_INMUX_INMUX0)
190    }
191    #[doc = "DMA trigger mux 1"]
192    #[inline(always)]
193    pub fn dma_inmux_inmux1(self) -> &'a mut W {
194        self.variant(INP_A::DMA_INMUX_INMUX1)
195    }
196    #[doc = r"Writes raw bits to the field"]
197    #[inline(always)]
198    pub unsafe fn bits(self, value: u8) -> &'a mut W {
199        self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f);
200        self.w
201    }
202}
203impl R {
204    #[doc = "Bits 0:3 - Input mux register for trigger inputs 0 to 23 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin interrupts, and DMA requests."]
205    #[inline(always)]
206    pub fn inp(&self) -> INP_R {
207        INP_R::new((self.bits & 0x0f) as u8)
208    }
209}
210impl W {
211    #[doc = "Bits 0:3 - Input mux register for trigger inputs 0 to 23 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin interrupts, and DMA requests."]
212    #[inline(always)]
213    pub fn inp(&mut self) -> INP_W {
214        INP_W { w: self }
215    }
216    #[doc = "Writes raw bits to the register."]
217    #[inline(always)]
218    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
219        self.0.bits(bits);
220        self
221    }
222}
223#[doc = "Trigger select register for DMA channel\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_itrig_inmux](index.html) module"]
224pub struct DMA_ITRIG_INMUX_SPEC;
225impl crate::RegisterSpec for DMA_ITRIG_INMUX_SPEC {
226    type Ux = u32;
227}
228#[doc = "`read()` method returns [dma_itrig_inmux::R](R) reader structure"]
229impl crate::Readable for DMA_ITRIG_INMUX_SPEC {
230    type Reader = R;
231}
232#[doc = "`write(|w| ..)` method takes [dma_itrig_inmux::W](W) writer structure"]
233impl crate::Writable for DMA_ITRIG_INMUX_SPEC {
234    type Writer = W;
235}
236#[doc = "`reset()` method sets DMA_ITRIG_INMUX[%s]
237to value 0x0f"]
238impl crate::Resettable for DMA_ITRIG_INMUX_SPEC {
239    #[inline(always)]
240    fn reset_value() -> Self::Ux {
241        0x0f
242    }
243}
lpc82x_pac/inputmux/dma_itrig_inmux.rs

lpc82x_pac/inputmux/
dma_itrig_inmux.rs
