lpc82x_pac/i2c0/
intenclr.rs

1#[doc = "Register `INTENCLR` writer"]
2pub struct W(crate::W<INTENCLR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<INTENCLR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<INTENCLR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<INTENCLR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `MSTPENDINGCLR` writer - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented."]
23pub struct MSTPENDINGCLR_W<'a> {
24    w: &'a mut W,
25}
26impl<'a> MSTPENDINGCLR_W<'a> {
27    #[doc = r"Sets the field bit"]
28    #[inline(always)]
29    pub fn set_bit(self) -> &'a mut W {
30        self.bit(true)
31    }
32    #[doc = r"Clears the field bit"]
33    #[inline(always)]
34    pub fn clear_bit(self) -> &'a mut W {
35        self.bit(false)
36    }
37    #[doc = r"Writes raw bits to the field"]
38    #[inline(always)]
39    pub fn bit(self, value: bool) -> &'a mut W {
40        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
41        self.w
42    }
43}
44#[doc = "Field `MSTARBLOSSCLR` writer - Master Arbitration Loss interrupt clear."]
45pub struct MSTARBLOSSCLR_W<'a> {
46    w: &'a mut W,
47}
48impl<'a> MSTARBLOSSCLR_W<'a> {
49    #[doc = r"Sets the field bit"]
50    #[inline(always)]
51    pub fn set_bit(self) -> &'a mut W {
52        self.bit(true)
53    }
54    #[doc = r"Clears the field bit"]
55    #[inline(always)]
56    pub fn clear_bit(self) -> &'a mut W {
57        self.bit(false)
58    }
59    #[doc = r"Writes raw bits to the field"]
60    #[inline(always)]
61    pub fn bit(self, value: bool) -> &'a mut W {
62        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
63        self.w
64    }
65}
66#[doc = "Field `MSTSTSTPERRCLR` writer - Master Start/Stop Error interrupt clear."]
67pub struct MSTSTSTPERRCLR_W<'a> {
68    w: &'a mut W,
69}
70impl<'a> MSTSTSTPERRCLR_W<'a> {
71    #[doc = r"Sets the field bit"]
72    #[inline(always)]
73    pub fn set_bit(self) -> &'a mut W {
74        self.bit(true)
75    }
76    #[doc = r"Clears the field bit"]
77    #[inline(always)]
78    pub fn clear_bit(self) -> &'a mut W {
79        self.bit(false)
80    }
81    #[doc = r"Writes raw bits to the field"]
82    #[inline(always)]
83    pub fn bit(self, value: bool) -> &'a mut W {
84        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
85        self.w
86    }
87}
88#[doc = "Field `SLVPENDINGCLR` writer - Slave Pending interrupt clear."]
89pub struct SLVPENDINGCLR_W<'a> {
90    w: &'a mut W,
91}
92impl<'a> SLVPENDINGCLR_W<'a> {
93    #[doc = r"Sets the field bit"]
94    #[inline(always)]
95    pub fn set_bit(self) -> &'a mut W {
96        self.bit(true)
97    }
98    #[doc = r"Clears the field bit"]
99    #[inline(always)]
100    pub fn clear_bit(self) -> &'a mut W {
101        self.bit(false)
102    }
103    #[doc = r"Writes raw bits to the field"]
104    #[inline(always)]
105    pub fn bit(self, value: bool) -> &'a mut W {
106        self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
107        self.w
108    }
109}
110#[doc = "Field `SLVNOTSTRCLR` writer - Slave Not Stretching interrupt clear."]
111pub struct SLVNOTSTRCLR_W<'a> {
112    w: &'a mut W,
113}
114impl<'a> SLVNOTSTRCLR_W<'a> {
115    #[doc = r"Sets the field bit"]
116    #[inline(always)]
117    pub fn set_bit(self) -> &'a mut W {
118        self.bit(true)
119    }
120    #[doc = r"Clears the field bit"]
121    #[inline(always)]
122    pub fn clear_bit(self) -> &'a mut W {
123        self.bit(false)
124    }
125    #[doc = r"Writes raw bits to the field"]
126    #[inline(always)]
127    pub fn bit(self, value: bool) -> &'a mut W {
128        self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
129        self.w
130    }
131}
132#[doc = "Field `SLVDESELCLR` writer - Slave Deselect interrupt clear."]
133pub struct SLVDESELCLR_W<'a> {
134    w: &'a mut W,
135}
136impl<'a> SLVDESELCLR_W<'a> {
137    #[doc = r"Sets the field bit"]
138    #[inline(always)]
139    pub fn set_bit(self) -> &'a mut W {
140        self.bit(true)
141    }
142    #[doc = r"Clears the field bit"]
143    #[inline(always)]
144    pub fn clear_bit(self) -> &'a mut W {
145        self.bit(false)
146    }
147    #[doc = r"Writes raw bits to the field"]
148    #[inline(always)]
149    pub fn bit(self, value: bool) -> &'a mut W {
150        self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15);
151        self.w
152    }
153}
154#[doc = "Field `MONRDYCLR` writer - Monitor data Ready interrupt clear."]
155pub struct MONRDYCLR_W<'a> {
156    w: &'a mut W,
157}
158impl<'a> MONRDYCLR_W<'a> {
159    #[doc = r"Sets the field bit"]
160    #[inline(always)]
161    pub fn set_bit(self) -> &'a mut W {
162        self.bit(true)
163    }
164    #[doc = r"Clears the field bit"]
165    #[inline(always)]
166    pub fn clear_bit(self) -> &'a mut W {
167        self.bit(false)
168    }
169    #[doc = r"Writes raw bits to the field"]
170    #[inline(always)]
171    pub fn bit(self, value: bool) -> &'a mut W {
172        self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
173        self.w
174    }
175}
176#[doc = "Field `MONOVCLR` writer - Monitor Overrun interrupt clear."]
177pub struct MONOVCLR_W<'a> {
178    w: &'a mut W,
179}
180impl<'a> MONOVCLR_W<'a> {
181    #[doc = r"Sets the field bit"]
182    #[inline(always)]
183    pub fn set_bit(self) -> &'a mut W {
184        self.bit(true)
185    }
186    #[doc = r"Clears the field bit"]
187    #[inline(always)]
188    pub fn clear_bit(self) -> &'a mut W {
189        self.bit(false)
190    }
191    #[doc = r"Writes raw bits to the field"]
192    #[inline(always)]
193    pub fn bit(self, value: bool) -> &'a mut W {
194        self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17);
195        self.w
196    }
197}
198#[doc = "Field `MONIDLECLR` writer - Monitor Idle interrupt clear."]
199pub struct MONIDLECLR_W<'a> {
200    w: &'a mut W,
201}
202impl<'a> MONIDLECLR_W<'a> {
203    #[doc = r"Sets the field bit"]
204    #[inline(always)]
205    pub fn set_bit(self) -> &'a mut W {
206        self.bit(true)
207    }
208    #[doc = r"Clears the field bit"]
209    #[inline(always)]
210    pub fn clear_bit(self) -> &'a mut W {
211        self.bit(false)
212    }
213    #[doc = r"Writes raw bits to the field"]
214    #[inline(always)]
215    pub fn bit(self, value: bool) -> &'a mut W {
216        self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19);
217        self.w
218    }
219}
220#[doc = "Field `EVENTTIMEOUTCLR` writer - Event time-out interrupt clear."]
221pub struct EVENTTIMEOUTCLR_W<'a> {
222    w: &'a mut W,
223}
224impl<'a> EVENTTIMEOUTCLR_W<'a> {
225    #[doc = r"Sets the field bit"]
226    #[inline(always)]
227    pub fn set_bit(self) -> &'a mut W {
228        self.bit(true)
229    }
230    #[doc = r"Clears the field bit"]
231    #[inline(always)]
232    pub fn clear_bit(self) -> &'a mut W {
233        self.bit(false)
234    }
235    #[doc = r"Writes raw bits to the field"]
236    #[inline(always)]
237    pub fn bit(self, value: bool) -> &'a mut W {
238        self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24);
239        self.w
240    }
241}
242#[doc = "Field `SCLTIMEOUTCLR` writer - SCL time-out interrupt clear."]
243pub struct SCLTIMEOUTCLR_W<'a> {
244    w: &'a mut W,
245}
246impl<'a> SCLTIMEOUTCLR_W<'a> {
247    #[doc = r"Sets the field bit"]
248    #[inline(always)]
249    pub fn set_bit(self) -> &'a mut W {
250        self.bit(true)
251    }
252    #[doc = r"Clears the field bit"]
253    #[inline(always)]
254    pub fn clear_bit(self) -> &'a mut W {
255        self.bit(false)
256    }
257    #[doc = r"Writes raw bits to the field"]
258    #[inline(always)]
259    pub fn bit(self, value: bool) -> &'a mut W {
260        self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25);
261        self.w
262    }
263}
264impl W {
265    #[doc = "Bit 0 - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding bit in the INTENSET register if implemented."]
266    #[inline(always)]
267    pub fn mstpendingclr(&mut self) -> MSTPENDINGCLR_W {
268        MSTPENDINGCLR_W { w: self }
269    }
270    #[doc = "Bit 4 - Master Arbitration Loss interrupt clear."]
271    #[inline(always)]
272    pub fn mstarblossclr(&mut self) -> MSTARBLOSSCLR_W {
273        MSTARBLOSSCLR_W { w: self }
274    }
275    #[doc = "Bit 6 - Master Start/Stop Error interrupt clear."]
276    #[inline(always)]
277    pub fn mstststperrclr(&mut self) -> MSTSTSTPERRCLR_W {
278        MSTSTSTPERRCLR_W { w: self }
279    }
280    #[doc = "Bit 8 - Slave Pending interrupt clear."]
281    #[inline(always)]
282    pub fn slvpendingclr(&mut self) -> SLVPENDINGCLR_W {
283        SLVPENDINGCLR_W { w: self }
284    }
285    #[doc = "Bit 11 - Slave Not Stretching interrupt clear."]
286    #[inline(always)]
287    pub fn slvnotstrclr(&mut self) -> SLVNOTSTRCLR_W {
288        SLVNOTSTRCLR_W { w: self }
289    }
290    #[doc = "Bit 15 - Slave Deselect interrupt clear."]
291    #[inline(always)]
292    pub fn slvdeselclr(&mut self) -> SLVDESELCLR_W {
293        SLVDESELCLR_W { w: self }
294    }
295    #[doc = "Bit 16 - Monitor data Ready interrupt clear."]
296    #[inline(always)]
297    pub fn monrdyclr(&mut self) -> MONRDYCLR_W {
298        MONRDYCLR_W { w: self }
299    }
300    #[doc = "Bit 17 - Monitor Overrun interrupt clear."]
301    #[inline(always)]
302    pub fn monovclr(&mut self) -> MONOVCLR_W {
303        MONOVCLR_W { w: self }
304    }
305    #[doc = "Bit 19 - Monitor Idle interrupt clear."]
306    #[inline(always)]
307    pub fn monidleclr(&mut self) -> MONIDLECLR_W {
308        MONIDLECLR_W { w: self }
309    }
310    #[doc = "Bit 24 - Event time-out interrupt clear."]
311    #[inline(always)]
312    pub fn eventtimeoutclr(&mut self) -> EVENTTIMEOUTCLR_W {
313        EVENTTIMEOUTCLR_W { w: self }
314    }
315    #[doc = "Bit 25 - SCL time-out interrupt clear."]
316    #[inline(always)]
317    pub fn scltimeoutclr(&mut self) -> SCLTIMEOUTCLR_W {
318        SCLTIMEOUTCLR_W { w: self }
319    }
320    #[doc = "Writes raw bits to the register."]
321    #[inline(always)]
322    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
323        self.0.bits(bits);
324        self
325    }
326}
327#[doc = "Interrupt Enable Clear register.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"]
328pub struct INTENCLR_SPEC;
329impl crate::RegisterSpec for INTENCLR_SPEC {
330    type Ux = u32;
331}
332#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"]
333impl crate::Writable for INTENCLR_SPEC {
334    type Writer = W;
335}
336#[doc = "`reset()` method sets INTENCLR to value 0"]
337impl crate::Resettable for INTENCLR_SPEC {
338    #[inline(always)]
339    fn reset_value() -> Self::Ux {
340        0
341    }
342}
lpc82x_pac/i2c0/intenclr.rs

lpc82x_pac/i2c0/
intenclr.rs
