lpc82x_pac/dma0/channel/
xfercfg.rs

1#[doc = "Register `XFERCFG` reader"]
2pub struct R(crate::R<XFERCFG_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<XFERCFG_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<XFERCFG_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<XFERCFG_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `XFERCFG` writer"]
17pub struct W(crate::W<XFERCFG_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<XFERCFG_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<XFERCFG_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<XFERCFG_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum CFGVALID_A {
40    #[doc = "0: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting."]
41    NOT_VALID = 0,
42    #[doc = "1: Valid. The current channel descriptor is considered valid."]
43    VALID = 1,
44}
45impl From<CFGVALID_A> for bool {
46    #[inline(always)]
47    fn from(variant: CFGVALID_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `CFGVALID` reader - Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled."]
52pub struct CFGVALID_R(crate::FieldReader<bool, CFGVALID_A>);
53impl CFGVALID_R {
54    pub(crate) fn new(bits: bool) -> Self {
55        CFGVALID_R(crate::FieldReader::new(bits))
56    }
57    #[doc = r"Get enumerated values variant"]
58    #[inline(always)]
59    pub fn variant(&self) -> CFGVALID_A {
60        match self.bits {
61            false => CFGVALID_A::NOT_VALID,
62            true => CFGVALID_A::VALID,
63        }
64    }
65    #[doc = "Checks if the value of the field is `NOT_VALID`"]
66    #[inline(always)]
67    pub fn is_not_valid(&self) -> bool {
68        **self == CFGVALID_A::NOT_VALID
69    }
70    #[doc = "Checks if the value of the field is `VALID`"]
71    #[inline(always)]
72    pub fn is_valid(&self) -> bool {
73        **self == CFGVALID_A::VALID
74    }
75}
76impl core::ops::Deref for CFGVALID_R {
77    type Target = crate::FieldReader<bool, CFGVALID_A>;
78    #[inline(always)]
79    fn deref(&self) -> &Self::Target {
80        &self.0
81    }
82}
83#[doc = "Field `CFGVALID` writer - Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled."]
84pub struct CFGVALID_W<'a> {
85    w: &'a mut W,
86}
87impl<'a> CFGVALID_W<'a> {
88    #[doc = r"Writes `variant` to the field"]
89    #[inline(always)]
90    pub fn variant(self, variant: CFGVALID_A) -> &'a mut W {
91        self.bit(variant.into())
92    }
93    #[doc = "Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting."]
94    #[inline(always)]
95    pub fn not_valid(self) -> &'a mut W {
96        self.variant(CFGVALID_A::NOT_VALID)
97    }
98    #[doc = "Valid. The current channel descriptor is considered valid."]
99    #[inline(always)]
100    pub fn valid(self) -> &'a mut W {
101        self.variant(CFGVALID_A::VALID)
102    }
103    #[doc = r"Sets the field bit"]
104    #[inline(always)]
105    pub fn set_bit(self) -> &'a mut W {
106        self.bit(true)
107    }
108    #[doc = r"Clears the field bit"]
109    #[inline(always)]
110    pub fn clear_bit(self) -> &'a mut W {
111        self.bit(false)
112    }
113    #[doc = r"Writes raw bits to the field"]
114    #[inline(always)]
115    pub fn bit(self, value: bool) -> &'a mut W {
116        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
117        self.w
118    }
119}
120#[doc = "Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.\n\nValue on reset: 0"]
121#[derive(Clone, Copy, Debug, PartialEq)]
122pub enum RELOAD_A {
123    #[doc = "0: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted."]
124    DISABLED = 0,
125    #[doc = "1: Enabled. Reload the channels' control structure when the current descriptor is exhausted."]
126    ENABLED = 1,
127}
128impl From<RELOAD_A> for bool {
129    #[inline(always)]
130    fn from(variant: RELOAD_A) -> Self {
131        variant as u8 != 0
132    }
133}
134#[doc = "Field `RELOAD` reader - Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers."]
135pub struct RELOAD_R(crate::FieldReader<bool, RELOAD_A>);
136impl RELOAD_R {
137    pub(crate) fn new(bits: bool) -> Self {
138        RELOAD_R(crate::FieldReader::new(bits))
139    }
140    #[doc = r"Get enumerated values variant"]
141    #[inline(always)]
142    pub fn variant(&self) -> RELOAD_A {
143        match self.bits {
144            false => RELOAD_A::DISABLED,
145            true => RELOAD_A::ENABLED,
146        }
147    }
148    #[doc = "Checks if the value of the field is `DISABLED`"]
149    #[inline(always)]
150    pub fn is_disabled(&self) -> bool {
151        **self == RELOAD_A::DISABLED
152    }
153    #[doc = "Checks if the value of the field is `ENABLED`"]
154    #[inline(always)]
155    pub fn is_enabled(&self) -> bool {
156        **self == RELOAD_A::ENABLED
157    }
158}
159impl core::ops::Deref for RELOAD_R {
160    type Target = crate::FieldReader<bool, RELOAD_A>;
161    #[inline(always)]
162    fn deref(&self) -> &Self::Target {
163        &self.0
164    }
165}
166#[doc = "Field `RELOAD` writer - Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers."]
167pub struct RELOAD_W<'a> {
168    w: &'a mut W,
169}
170impl<'a> RELOAD_W<'a> {
171    #[doc = r"Writes `variant` to the field"]
172    #[inline(always)]
173    pub fn variant(self, variant: RELOAD_A) -> &'a mut W {
174        self.bit(variant.into())
175    }
176    #[doc = "Disabled. Do not reload the channels' control structure when the current descriptor is exhausted."]
177    #[inline(always)]
178    pub fn disabled(self) -> &'a mut W {
179        self.variant(RELOAD_A::DISABLED)
180    }
181    #[doc = "Enabled. Reload the channels' control structure when the current descriptor is exhausted."]
182    #[inline(always)]
183    pub fn enabled(self) -> &'a mut W {
184        self.variant(RELOAD_A::ENABLED)
185    }
186    #[doc = r"Sets the field bit"]
187    #[inline(always)]
188    pub fn set_bit(self) -> &'a mut W {
189        self.bit(true)
190    }
191    #[doc = r"Clears the field bit"]
192    #[inline(always)]
193    pub fn clear_bit(self) -> &'a mut W {
194        self.bit(false)
195    }
196    #[doc = r"Writes raw bits to the field"]
197    #[inline(always)]
198    pub fn bit(self, value: bool) -> &'a mut W {
199        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
200        self.w
201    }
202}
203#[doc = "Software Trigger.\n\nValue on reset: 0"]
204#[derive(Clone, Copy, Debug, PartialEq)]
205pub enum SWTRIG_A {
206    #[doc = "0: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel."]
207    NOT_SET = 0,
208    #[doc = "1: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0."]
209    SET = 1,
210}
211impl From<SWTRIG_A> for bool {
212    #[inline(always)]
213    fn from(variant: SWTRIG_A) -> Self {
214        variant as u8 != 0
215    }
216}
217#[doc = "Field `SWTRIG` reader - Software Trigger."]
218pub struct SWTRIG_R(crate::FieldReader<bool, SWTRIG_A>);
219impl SWTRIG_R {
220    pub(crate) fn new(bits: bool) -> Self {
221        SWTRIG_R(crate::FieldReader::new(bits))
222    }
223    #[doc = r"Get enumerated values variant"]
224    #[inline(always)]
225    pub fn variant(&self) -> SWTRIG_A {
226        match self.bits {
227            false => SWTRIG_A::NOT_SET,
228            true => SWTRIG_A::SET,
229        }
230    }
231    #[doc = "Checks if the value of the field is `NOT_SET`"]
232    #[inline(always)]
233    pub fn is_not_set(&self) -> bool {
234        **self == SWTRIG_A::NOT_SET
235    }
236    #[doc = "Checks if the value of the field is `SET`"]
237    #[inline(always)]
238    pub fn is_set(&self) -> bool {
239        **self == SWTRIG_A::SET
240    }
241}
242impl core::ops::Deref for SWTRIG_R {
243    type Target = crate::FieldReader<bool, SWTRIG_A>;
244    #[inline(always)]
245    fn deref(&self) -> &Self::Target {
246        &self.0
247    }
248}
249#[doc = "Field `SWTRIG` writer - Software Trigger."]
250pub struct SWTRIG_W<'a> {
251    w: &'a mut W,
252}
253impl<'a> SWTRIG_W<'a> {
254    #[doc = r"Writes `variant` to the field"]
255    #[inline(always)]
256    pub fn variant(self, variant: SWTRIG_A) -> &'a mut W {
257        self.bit(variant.into())
258    }
259    #[doc = "Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel."]
260    #[inline(always)]
261    pub fn not_set(self) -> &'a mut W {
262        self.variant(SWTRIG_A::NOT_SET)
263    }
264    #[doc = "Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0."]
265    #[inline(always)]
266    pub fn set(self) -> &'a mut W {
267        self.variant(SWTRIG_A::SET)
268    }
269    #[doc = r"Sets the field bit"]
270    #[inline(always)]
271    pub fn set_bit(self) -> &'a mut W {
272        self.bit(true)
273    }
274    #[doc = r"Clears the field bit"]
275    #[inline(always)]
276    pub fn clear_bit(self) -> &'a mut W {
277        self.bit(false)
278    }
279    #[doc = r"Writes raw bits to the field"]
280    #[inline(always)]
281    pub fn bit(self, value: bool) -> &'a mut W {
282        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
283        self.w
284    }
285}
286#[doc = "Clear Trigger.\n\nValue on reset: 0"]
287#[derive(Clone, Copy, Debug, PartialEq)]
288pub enum CLRTRIG_A {
289    #[doc = "0: Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started."]
290    NOT_CLEARED = 0,
291    #[doc = "1: Cleared. The trigger is cleared when this descriptor is exhausted"]
292    CLEARED = 1,
293}
294impl From<CLRTRIG_A> for bool {
295    #[inline(always)]
296    fn from(variant: CLRTRIG_A) -> Self {
297        variant as u8 != 0
298    }
299}
300#[doc = "Field `CLRTRIG` reader - Clear Trigger."]
301pub struct CLRTRIG_R(crate::FieldReader<bool, CLRTRIG_A>);
302impl CLRTRIG_R {
303    pub(crate) fn new(bits: bool) -> Self {
304        CLRTRIG_R(crate::FieldReader::new(bits))
305    }
306    #[doc = r"Get enumerated values variant"]
307    #[inline(always)]
308    pub fn variant(&self) -> CLRTRIG_A {
309        match self.bits {
310            false => CLRTRIG_A::NOT_CLEARED,
311            true => CLRTRIG_A::CLEARED,
312        }
313    }
314    #[doc = "Checks if the value of the field is `NOT_CLEARED`"]
315    #[inline(always)]
316    pub fn is_not_cleared(&self) -> bool {
317        **self == CLRTRIG_A::NOT_CLEARED
318    }
319    #[doc = "Checks if the value of the field is `CLEARED`"]
320    #[inline(always)]
321    pub fn is_cleared(&self) -> bool {
322        **self == CLRTRIG_A::CLEARED
323    }
324}
325impl core::ops::Deref for CLRTRIG_R {
326    type Target = crate::FieldReader<bool, CLRTRIG_A>;
327    #[inline(always)]
328    fn deref(&self) -> &Self::Target {
329        &self.0
330    }
331}
332#[doc = "Field `CLRTRIG` writer - Clear Trigger."]
333pub struct CLRTRIG_W<'a> {
334    w: &'a mut W,
335}
336impl<'a> CLRTRIG_W<'a> {
337    #[doc = r"Writes `variant` to the field"]
338    #[inline(always)]
339    pub fn variant(self, variant: CLRTRIG_A) -> &'a mut W {
340        self.bit(variant.into())
341    }
342    #[doc = "Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started."]
343    #[inline(always)]
344    pub fn not_cleared(self) -> &'a mut W {
345        self.variant(CLRTRIG_A::NOT_CLEARED)
346    }
347    #[doc = "Cleared. The trigger is cleared when this descriptor is exhausted"]
348    #[inline(always)]
349    pub fn cleared(self) -> &'a mut W {
350        self.variant(CLRTRIG_A::CLEARED)
351    }
352    #[doc = r"Sets the field bit"]
353    #[inline(always)]
354    pub fn set_bit(self) -> &'a mut W {
355        self.bit(true)
356    }
357    #[doc = r"Clears the field bit"]
358    #[inline(always)]
359    pub fn clear_bit(self) -> &'a mut W {
360        self.bit(false)
361    }
362    #[doc = r"Writes raw bits to the field"]
363    #[inline(always)]
364    pub fn bit(self, value: bool) -> &'a mut W {
365        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
366        self.w
367    }
368}
369#[doc = "Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.\n\nValue on reset: 0"]
370#[derive(Clone, Copy, Debug, PartialEq)]
371pub enum SETINTA_A {
372    #[doc = "0: No effect."]
373    NO_EFFECT = 0,
374    #[doc = "1: Set. The INTA flag for this channel will be set when the current descriptor is exhausted."]
375    SET = 1,
376}
377impl From<SETINTA_A> for bool {
378    #[inline(always)]
379    fn from(variant: SETINTA_A) -> Self {
380        variant as u8 != 0
381    }
382}
383#[doc = "Field `SETINTA` reader - Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."]
384pub struct SETINTA_R(crate::FieldReader<bool, SETINTA_A>);
385impl SETINTA_R {
386    pub(crate) fn new(bits: bool) -> Self {
387        SETINTA_R(crate::FieldReader::new(bits))
388    }
389    #[doc = r"Get enumerated values variant"]
390    #[inline(always)]
391    pub fn variant(&self) -> SETINTA_A {
392        match self.bits {
393            false => SETINTA_A::NO_EFFECT,
394            true => SETINTA_A::SET,
395        }
396    }
397    #[doc = "Checks if the value of the field is `NO_EFFECT`"]
398    #[inline(always)]
399    pub fn is_no_effect(&self) -> bool {
400        **self == SETINTA_A::NO_EFFECT
401    }
402    #[doc = "Checks if the value of the field is `SET`"]
403    #[inline(always)]
404    pub fn is_set(&self) -> bool {
405        **self == SETINTA_A::SET
406    }
407}
408impl core::ops::Deref for SETINTA_R {
409    type Target = crate::FieldReader<bool, SETINTA_A>;
410    #[inline(always)]
411    fn deref(&self) -> &Self::Target {
412        &self.0
413    }
414}
415#[doc = "Field `SETINTA` writer - Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."]
416pub struct SETINTA_W<'a> {
417    w: &'a mut W,
418}
419impl<'a> SETINTA_W<'a> {
420    #[doc = r"Writes `variant` to the field"]
421    #[inline(always)]
422    pub fn variant(self, variant: SETINTA_A) -> &'a mut W {
423        self.bit(variant.into())
424    }
425    #[doc = "No effect."]
426    #[inline(always)]
427    pub fn no_effect(self) -> &'a mut W {
428        self.variant(SETINTA_A::NO_EFFECT)
429    }
430    #[doc = "Set. The INTA flag for this channel will be set when the current descriptor is exhausted."]
431    #[inline(always)]
432    pub fn set(self) -> &'a mut W {
433        self.variant(SETINTA_A::SET)
434    }
435    #[doc = r"Sets the field bit"]
436    #[inline(always)]
437    pub fn set_bit(self) -> &'a mut W {
438        self.bit(true)
439    }
440    #[doc = r"Clears the field bit"]
441    #[inline(always)]
442    pub fn clear_bit(self) -> &'a mut W {
443        self.bit(false)
444    }
445    #[doc = r"Writes raw bits to the field"]
446    #[inline(always)]
447    pub fn bit(self, value: bool) -> &'a mut W {
448        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
449        self.w
450    }
451}
452#[doc = "Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.\n\nValue on reset: 0"]
453#[derive(Clone, Copy, Debug, PartialEq)]
454pub enum SETINTB_A {
455    #[doc = "0: No effect."]
456    NO_EFFECT = 0,
457    #[doc = "1: Set. The INTB flag for this channel will be set when the current descriptor is exhausted."]
458    SET = 1,
459}
460impl From<SETINTB_A> for bool {
461    #[inline(always)]
462    fn from(variant: SETINTB_A) -> Self {
463        variant as u8 != 0
464    }
465}
466#[doc = "Field `SETINTB` reader - Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."]
467pub struct SETINTB_R(crate::FieldReader<bool, SETINTB_A>);
468impl SETINTB_R {
469    pub(crate) fn new(bits: bool) -> Self {
470        SETINTB_R(crate::FieldReader::new(bits))
471    }
472    #[doc = r"Get enumerated values variant"]
473    #[inline(always)]
474    pub fn variant(&self) -> SETINTB_A {
475        match self.bits {
476            false => SETINTB_A::NO_EFFECT,
477            true => SETINTB_A::SET,
478        }
479    }
480    #[doc = "Checks if the value of the field is `NO_EFFECT`"]
481    #[inline(always)]
482    pub fn is_no_effect(&self) -> bool {
483        **self == SETINTB_A::NO_EFFECT
484    }
485    #[doc = "Checks if the value of the field is `SET`"]
486    #[inline(always)]
487    pub fn is_set(&self) -> bool {
488        **self == SETINTB_A::SET
489    }
490}
491impl core::ops::Deref for SETINTB_R {
492    type Target = crate::FieldReader<bool, SETINTB_A>;
493    #[inline(always)]
494    fn deref(&self) -> &Self::Target {
495        &self.0
496    }
497}
498#[doc = "Field `SETINTB` writer - Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."]
499pub struct SETINTB_W<'a> {
500    w: &'a mut W,
501}
502impl<'a> SETINTB_W<'a> {
503    #[doc = r"Writes `variant` to the field"]
504    #[inline(always)]
505    pub fn variant(self, variant: SETINTB_A) -> &'a mut W {
506        self.bit(variant.into())
507    }
508    #[doc = "No effect."]
509    #[inline(always)]
510    pub fn no_effect(self) -> &'a mut W {
511        self.variant(SETINTB_A::NO_EFFECT)
512    }
513    #[doc = "Set. The INTB flag for this channel will be set when the current descriptor is exhausted."]
514    #[inline(always)]
515    pub fn set(self) -> &'a mut W {
516        self.variant(SETINTB_A::SET)
517    }
518    #[doc = r"Sets the field bit"]
519    #[inline(always)]
520    pub fn set_bit(self) -> &'a mut W {
521        self.bit(true)
522    }
523    #[doc = r"Clears the field bit"]
524    #[inline(always)]
525    pub fn clear_bit(self) -> &'a mut W {
526        self.bit(false)
527    }
528    #[doc = r"Writes raw bits to the field"]
529    #[inline(always)]
530    pub fn bit(self, value: bool) -> &'a mut W {
531        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
532        self.w
533    }
534}
535#[doc = "Transfer width used for this DMA channel.\n\nValue on reset: 0"]
536#[derive(Clone, Copy, Debug, PartialEq)]
537#[repr(u8)]
538pub enum WIDTH_A {
539    #[doc = "0: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes)."]
540    BIT_8 = 0,
541    #[doc = "1: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes)."]
542    BIT_16 = 1,
543    #[doc = "2: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes)."]
544    BIT_32 = 2,
545}
546impl From<WIDTH_A> for u8 {
547    #[inline(always)]
548    fn from(variant: WIDTH_A) -> Self {
549        variant as _
550    }
551}
552#[doc = "Field `WIDTH` reader - Transfer width used for this DMA channel."]
553pub struct WIDTH_R(crate::FieldReader<u8, WIDTH_A>);
554impl WIDTH_R {
555    pub(crate) fn new(bits: u8) -> Self {
556        WIDTH_R(crate::FieldReader::new(bits))
557    }
558    #[doc = r"Get enumerated values variant"]
559    #[inline(always)]
560    pub fn variant(&self) -> Option<WIDTH_A> {
561        match self.bits {
562            0 => Some(WIDTH_A::BIT_8),
563            1 => Some(WIDTH_A::BIT_16),
564            2 => Some(WIDTH_A::BIT_32),
565            _ => None,
566        }
567    }
568    #[doc = "Checks if the value of the field is `BIT_8`"]
569    #[inline(always)]
570    pub fn is_bit_8(&self) -> bool {
571        **self == WIDTH_A::BIT_8
572    }
573    #[doc = "Checks if the value of the field is `BIT_16`"]
574    #[inline(always)]
575    pub fn is_bit_16(&self) -> bool {
576        **self == WIDTH_A::BIT_16
577    }
578    #[doc = "Checks if the value of the field is `BIT_32`"]
579    #[inline(always)]
580    pub fn is_bit_32(&self) -> bool {
581        **self == WIDTH_A::BIT_32
582    }
583}
584impl core::ops::Deref for WIDTH_R {
585    type Target = crate::FieldReader<u8, WIDTH_A>;
586    #[inline(always)]
587    fn deref(&self) -> &Self::Target {
588        &self.0
589    }
590}
591#[doc = "Field `WIDTH` writer - Transfer width used for this DMA channel."]
592pub struct WIDTH_W<'a> {
593    w: &'a mut W,
594}
595impl<'a> WIDTH_W<'a> {
596    #[doc = r"Writes `variant` to the field"]
597    #[inline(always)]
598    pub fn variant(self, variant: WIDTH_A) -> &'a mut W {
599        unsafe { self.bits(variant.into()) }
600    }
601    #[doc = "8-bit. 8-bit transfers are performed (8-bit source reads and destination writes)."]
602    #[inline(always)]
603    pub fn bit_8(self) -> &'a mut W {
604        self.variant(WIDTH_A::BIT_8)
605    }
606    #[doc = "16-bit. 6-bit transfers are performed (16-bit source reads and destination writes)."]
607    #[inline(always)]
608    pub fn bit_16(self) -> &'a mut W {
609        self.variant(WIDTH_A::BIT_16)
610    }
611    #[doc = "32-bit. 32-bit transfers are performed (32-bit source reads and destination writes)."]
612    #[inline(always)]
613    pub fn bit_32(self) -> &'a mut W {
614        self.variant(WIDTH_A::BIT_32)
615    }
616    #[doc = r"Writes raw bits to the field"]
617    #[inline(always)]
618    pub unsafe fn bits(self, value: u8) -> &'a mut W {
619        self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8);
620        self.w
621    }
622}
623#[doc = "Determines whether the source address is incremented for each DMA transfer.\n\nValue on reset: 0"]
624#[derive(Clone, Copy, Debug, PartialEq)]
625#[repr(u8)]
626pub enum SRCINC_A {
627    #[doc = "0: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device."]
628    NO_INCREMENT = 0,
629    #[doc = "1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory."]
630    WIDTH_X_1 = 1,
631    #[doc = "2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer."]
632    WIDTH_X_2 = 2,
633    #[doc = "3: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer."]
634    WIDTH_X_4 = 3,
635}
636impl From<SRCINC_A> for u8 {
637    #[inline(always)]
638    fn from(variant: SRCINC_A) -> Self {
639        variant as _
640    }
641}
642#[doc = "Field `SRCINC` reader - Determines whether the source address is incremented for each DMA transfer."]
643pub struct SRCINC_R(crate::FieldReader<u8, SRCINC_A>);
644impl SRCINC_R {
645    pub(crate) fn new(bits: u8) -> Self {
646        SRCINC_R(crate::FieldReader::new(bits))
647    }
648    #[doc = r"Get enumerated values variant"]
649    #[inline(always)]
650    pub fn variant(&self) -> SRCINC_A {
651        match self.bits {
652            0 => SRCINC_A::NO_INCREMENT,
653            1 => SRCINC_A::WIDTH_X_1,
654            2 => SRCINC_A::WIDTH_X_2,
655            3 => SRCINC_A::WIDTH_X_4,
656            _ => unreachable!(),
657        }
658    }
659    #[doc = "Checks if the value of the field is `NO_INCREMENT`"]
660    #[inline(always)]
661    pub fn is_no_increment(&self) -> bool {
662        **self == SRCINC_A::NO_INCREMENT
663    }
664    #[doc = "Checks if the value of the field is `WIDTH_X_1`"]
665    #[inline(always)]
666    pub fn is_width_x_1(&self) -> bool {
667        **self == SRCINC_A::WIDTH_X_1
668    }
669    #[doc = "Checks if the value of the field is `WIDTH_X_2`"]
670    #[inline(always)]
671    pub fn is_width_x_2(&self) -> bool {
672        **self == SRCINC_A::WIDTH_X_2
673    }
674    #[doc = "Checks if the value of the field is `WIDTH_X_4`"]
675    #[inline(always)]
676    pub fn is_width_x_4(&self) -> bool {
677        **self == SRCINC_A::WIDTH_X_4
678    }
679}
680impl core::ops::Deref for SRCINC_R {
681    type Target = crate::FieldReader<u8, SRCINC_A>;
682    #[inline(always)]
683    fn deref(&self) -> &Self::Target {
684        &self.0
685    }
686}
687#[doc = "Field `SRCINC` writer - Determines whether the source address is incremented for each DMA transfer."]
688pub struct SRCINC_W<'a> {
689    w: &'a mut W,
690}
691impl<'a> SRCINC_W<'a> {
692    #[doc = r"Writes `variant` to the field"]
693    #[inline(always)]
694    pub fn variant(self, variant: SRCINC_A) -> &'a mut W {
695        self.bits(variant.into())
696    }
697    #[doc = "No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device."]
698    #[inline(always)]
699    pub fn no_increment(self) -> &'a mut W {
700        self.variant(SRCINC_A::NO_INCREMENT)
701    }
702    #[doc = "1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory."]
703    #[inline(always)]
704    pub fn width_x_1(self) -> &'a mut W {
705        self.variant(SRCINC_A::WIDTH_X_1)
706    }
707    #[doc = "2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer."]
708    #[inline(always)]
709    pub fn width_x_2(self) -> &'a mut W {
710        self.variant(SRCINC_A::WIDTH_X_2)
711    }
712    #[doc = "4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer."]
713    #[inline(always)]
714    pub fn width_x_4(self) -> &'a mut W {
715        self.variant(SRCINC_A::WIDTH_X_4)
716    }
717    #[doc = r"Writes raw bits to the field"]
718    #[inline(always)]
719    pub fn bits(self, value: u8) -> &'a mut W {
720        self.w.bits = (self.w.bits & !(0x03 << 12)) | ((value as u32 & 0x03) << 12);
721        self.w
722    }
723}
724#[doc = "Determines whether the destination address is incremented for each DMA transfer.\n\nValue on reset: 0"]
725#[derive(Clone, Copy, Debug, PartialEq)]
726#[repr(u8)]
727pub enum DSTINC_A {
728    #[doc = "0: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device."]
729    NO_INCREMENT = 0,
730    #[doc = "1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory."]
731    WIDTH_X_1 = 1,
732    #[doc = "2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer."]
733    WIDTH_X_2 = 2,
734    #[doc = "3: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer."]
735    WIDTH_X_4 = 3,
736}
737impl From<DSTINC_A> for u8 {
738    #[inline(always)]
739    fn from(variant: DSTINC_A) -> Self {
740        variant as _
741    }
742}
743#[doc = "Field `DSTINC` reader - Determines whether the destination address is incremented for each DMA transfer."]
744pub struct DSTINC_R(crate::FieldReader<u8, DSTINC_A>);
745impl DSTINC_R {
746    pub(crate) fn new(bits: u8) -> Self {
747        DSTINC_R(crate::FieldReader::new(bits))
748    }
749    #[doc = r"Get enumerated values variant"]
750    #[inline(always)]
751    pub fn variant(&self) -> DSTINC_A {
752        match self.bits {
753            0 => DSTINC_A::NO_INCREMENT,
754            1 => DSTINC_A::WIDTH_X_1,
755            2 => DSTINC_A::WIDTH_X_2,
756            3 => DSTINC_A::WIDTH_X_4,
757            _ => unreachable!(),
758        }
759    }
760    #[doc = "Checks if the value of the field is `NO_INCREMENT`"]
761    #[inline(always)]
762    pub fn is_no_increment(&self) -> bool {
763        **self == DSTINC_A::NO_INCREMENT
764    }
765    #[doc = "Checks if the value of the field is `WIDTH_X_1`"]
766    #[inline(always)]
767    pub fn is_width_x_1(&self) -> bool {
768        **self == DSTINC_A::WIDTH_X_1
769    }
770    #[doc = "Checks if the value of the field is `WIDTH_X_2`"]
771    #[inline(always)]
772    pub fn is_width_x_2(&self) -> bool {
773        **self == DSTINC_A::WIDTH_X_2
774    }
775    #[doc = "Checks if the value of the field is `WIDTH_X_4`"]
776    #[inline(always)]
777    pub fn is_width_x_4(&self) -> bool {
778        **self == DSTINC_A::WIDTH_X_4
779    }
780}
781impl core::ops::Deref for DSTINC_R {
782    type Target = crate::FieldReader<u8, DSTINC_A>;
783    #[inline(always)]
784    fn deref(&self) -> &Self::Target {
785        &self.0
786    }
787}
788#[doc = "Field `DSTINC` writer - Determines whether the destination address is incremented for each DMA transfer."]
789pub struct DSTINC_W<'a> {
790    w: &'a mut W,
791}
792impl<'a> DSTINC_W<'a> {
793    #[doc = r"Writes `variant` to the field"]
794    #[inline(always)]
795    pub fn variant(self, variant: DSTINC_A) -> &'a mut W {
796        self.bits(variant.into())
797    }
798    #[doc = "No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device."]
799    #[inline(always)]
800    pub fn no_increment(self) -> &'a mut W {
801        self.variant(DSTINC_A::NO_INCREMENT)
802    }
803    #[doc = "1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory."]
804    #[inline(always)]
805    pub fn width_x_1(self) -> &'a mut W {
806        self.variant(DSTINC_A::WIDTH_X_1)
807    }
808    #[doc = "2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer."]
809    #[inline(always)]
810    pub fn width_x_2(self) -> &'a mut W {
811        self.variant(DSTINC_A::WIDTH_X_2)
812    }
813    #[doc = "4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer."]
814    #[inline(always)]
815    pub fn width_x_4(self) -> &'a mut W {
816        self.variant(DSTINC_A::WIDTH_X_4)
817    }
818    #[doc = r"Writes raw bits to the field"]
819    #[inline(always)]
820    pub fn bits(self, value: u8) -> &'a mut W {
821        self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14);
822        self.w
823    }
824}
825#[doc = "Field `XFERCOUNT` reader - Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed."]
826pub struct XFERCOUNT_R(crate::FieldReader<u16, u16>);
827impl XFERCOUNT_R {
828    pub(crate) fn new(bits: u16) -> Self {
829        XFERCOUNT_R(crate::FieldReader::new(bits))
830    }
831}
832impl core::ops::Deref for XFERCOUNT_R {
833    type Target = crate::FieldReader<u16, u16>;
834    #[inline(always)]
835    fn deref(&self) -> &Self::Target {
836        &self.0
837    }
838}
839#[doc = "Field `XFERCOUNT` writer - Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed."]
840pub struct XFERCOUNT_W<'a> {
841    w: &'a mut W,
842}
843impl<'a> XFERCOUNT_W<'a> {
844    #[doc = r"Writes raw bits to the field"]
845    #[inline(always)]
846    pub unsafe fn bits(self, value: u16) -> &'a mut W {
847        self.w.bits = (self.w.bits & !(0x03ff << 16)) | ((value as u32 & 0x03ff) << 16);
848        self.w
849    }
850}
851impl R {
852    #[doc = "Bit 0 - Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled."]
853    #[inline(always)]
854    pub fn cfgvalid(&self) -> CFGVALID_R {
855        CFGVALID_R::new((self.bits & 0x01) != 0)
856    }
857    #[doc = "Bit 1 - Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers."]
858    #[inline(always)]
859    pub fn reload(&self) -> RELOAD_R {
860        RELOAD_R::new(((self.bits >> 1) & 0x01) != 0)
861    }
862    #[doc = "Bit 2 - Software Trigger."]
863    #[inline(always)]
864    pub fn swtrig(&self) -> SWTRIG_R {
865        SWTRIG_R::new(((self.bits >> 2) & 0x01) != 0)
866    }
867    #[doc = "Bit 3 - Clear Trigger."]
868    #[inline(always)]
869    pub fn clrtrig(&self) -> CLRTRIG_R {
870        CLRTRIG_R::new(((self.bits >> 3) & 0x01) != 0)
871    }
872    #[doc = "Bit 4 - Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."]
873    #[inline(always)]
874    pub fn setinta(&self) -> SETINTA_R {
875        SETINTA_R::new(((self.bits >> 4) & 0x01) != 0)
876    }
877    #[doc = "Bit 5 - Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."]
878    #[inline(always)]
879    pub fn setintb(&self) -> SETINTB_R {
880        SETINTB_R::new(((self.bits >> 5) & 0x01) != 0)
881    }
882    #[doc = "Bits 8:9 - Transfer width used for this DMA channel."]
883    #[inline(always)]
884    pub fn width(&self) -> WIDTH_R {
885        WIDTH_R::new(((self.bits >> 8) & 0x03) as u8)
886    }
887    #[doc = "Bits 12:13 - Determines whether the source address is incremented for each DMA transfer."]
888    #[inline(always)]
889    pub fn srcinc(&self) -> SRCINC_R {
890        SRCINC_R::new(((self.bits >> 12) & 0x03) as u8)
891    }
892    #[doc = "Bits 14:15 - Determines whether the destination address is incremented for each DMA transfer."]
893    #[inline(always)]
894    pub fn dstinc(&self) -> DSTINC_R {
895        DSTINC_R::new(((self.bits >> 14) & 0x03) as u8)
896    }
897    #[doc = "Bits 16:25 - Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed."]
898    #[inline(always)]
899    pub fn xfercount(&self) -> XFERCOUNT_R {
900        XFERCOUNT_R::new(((self.bits >> 16) & 0x03ff) as u16)
901    }
902}
903impl W {
904    #[doc = "Bit 0 - Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled."]
905    #[inline(always)]
906    pub fn cfgvalid(&mut self) -> CFGVALID_W {
907        CFGVALID_W { w: self }
908    }
909    #[doc = "Bit 1 - Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers."]
910    #[inline(always)]
911    pub fn reload(&mut self) -> RELOAD_W {
912        RELOAD_W { w: self }
913    }
914    #[doc = "Bit 2 - Software Trigger."]
915    #[inline(always)]
916    pub fn swtrig(&mut self) -> SWTRIG_W {
917        SWTRIG_W { w: self }
918    }
919    #[doc = "Bit 3 - Clear Trigger."]
920    #[inline(always)]
921    pub fn clrtrig(&mut self) -> CLRTRIG_W {
922        CLRTRIG_W { w: self }
923    }
924    #[doc = "Bit 4 - Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."]
925    #[inline(always)]
926    pub fn setinta(&mut self) -> SETINTA_W {
927        SETINTA_W { w: self }
928    }
929    #[doc = "Bit 5 - Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."]
930    #[inline(always)]
931    pub fn setintb(&mut self) -> SETINTB_W {
932        SETINTB_W { w: self }
933    }
934    #[doc = "Bits 8:9 - Transfer width used for this DMA channel."]
935    #[inline(always)]
936    pub fn width(&mut self) -> WIDTH_W {
937        WIDTH_W { w: self }
938    }
939    #[doc = "Bits 12:13 - Determines whether the source address is incremented for each DMA transfer."]
940    #[inline(always)]
941    pub fn srcinc(&mut self) -> SRCINC_W {
942        SRCINC_W { w: self }
943    }
944    #[doc = "Bits 14:15 - Determines whether the destination address is incremented for each DMA transfer."]
945    #[inline(always)]
946    pub fn dstinc(&mut self) -> DSTINC_W {
947        DSTINC_W { w: self }
948    }
949    #[doc = "Bits 16:25 - Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed."]
950    #[inline(always)]
951    pub fn xfercount(&mut self) -> XFERCOUNT_W {
952        XFERCOUNT_W { w: self }
953    }
954    #[doc = "Writes raw bits to the register."]
955    #[inline(always)]
956    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
957        self.0.bits(bits);
958        self
959    }
960}
961#[doc = "Transfer configuration register for DMA channel .\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xfercfg](index.html) module"]
962pub struct XFERCFG_SPEC;
963impl crate::RegisterSpec for XFERCFG_SPEC {
964    type Ux = u32;
965}
966#[doc = "`read()` method returns [xfercfg::R](R) reader structure"]
967impl crate::Readable for XFERCFG_SPEC {
968    type Reader = R;
969}
970#[doc = "`write(|w| ..)` method takes [xfercfg::W](W) writer structure"]
971impl crate::Writable for XFERCFG_SPEC {
972    type Writer = W;
973}
974#[doc = "`reset()` method sets XFERCFG to value 0"]
975impl crate::Resettable for XFERCFG_SPEC {
976    #[inline(always)]
977    fn reset_value() -> Self::Ux {
978        0
979    }
980}
lpc82x_pac/dma0/channel/xfercfg.rs

lpc82x_pac/dma0/channel/
xfercfg.rs
