1#[doc = "Register `CFG` reader"]
2pub struct R(crate::R<CFG_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CFG_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CFG_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CFG_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CFG` writer"]
17pub struct W(crate::W<CFG_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CFG_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CFG_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CFG_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum PERIPHREQEN_A {
40 #[doc = "0: Disabled. Peripheral DMA requests are disabled."]
41 DISABLED = 0,
42 #[doc = "1: Enabled. Peripheral DMA requests are enabled."]
43 ENABLED = 1,
44}
45impl From<PERIPHREQEN_A> for bool {
46 #[inline(always)]
47 fn from(variant: PERIPHREQEN_A) -> Self {
48 variant as u8 != 0
49 }
50}
51#[doc = "Field `PERIPHREQEN` reader - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller."]
52pub struct PERIPHREQEN_R(crate::FieldReader<bool, PERIPHREQEN_A>);
53impl PERIPHREQEN_R {
54 pub(crate) fn new(bits: bool) -> Self {
55 PERIPHREQEN_R(crate::FieldReader::new(bits))
56 }
57 #[doc = r"Get enumerated values variant"]
58 #[inline(always)]
59 pub fn variant(&self) -> PERIPHREQEN_A {
60 match self.bits {
61 false => PERIPHREQEN_A::DISABLED,
62 true => PERIPHREQEN_A::ENABLED,
63 }
64 }
65 #[doc = "Checks if the value of the field is `DISABLED`"]
66 #[inline(always)]
67 pub fn is_disabled(&self) -> bool {
68 **self == PERIPHREQEN_A::DISABLED
69 }
70 #[doc = "Checks if the value of the field is `ENABLED`"]
71 #[inline(always)]
72 pub fn is_enabled(&self) -> bool {
73 **self == PERIPHREQEN_A::ENABLED
74 }
75}
76impl core::ops::Deref for PERIPHREQEN_R {
77 type Target = crate::FieldReader<bool, PERIPHREQEN_A>;
78 #[inline(always)]
79 fn deref(&self) -> &Self::Target {
80 &self.0
81 }
82}
83#[doc = "Field `PERIPHREQEN` writer - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller."]
84pub struct PERIPHREQEN_W<'a> {
85 w: &'a mut W,
86}
87impl<'a> PERIPHREQEN_W<'a> {
88 #[doc = r"Writes `variant` to the field"]
89 #[inline(always)]
90 pub fn variant(self, variant: PERIPHREQEN_A) -> &'a mut W {
91 self.bit(variant.into())
92 }
93 #[doc = "Disabled. Peripheral DMA requests are disabled."]
94 #[inline(always)]
95 pub fn disabled(self) -> &'a mut W {
96 self.variant(PERIPHREQEN_A::DISABLED)
97 }
98 #[doc = "Enabled. Peripheral DMA requests are enabled."]
99 #[inline(always)]
100 pub fn enabled(self) -> &'a mut W {
101 self.variant(PERIPHREQEN_A::ENABLED)
102 }
103 #[doc = r"Sets the field bit"]
104 #[inline(always)]
105 pub fn set_bit(self) -> &'a mut W {
106 self.bit(true)
107 }
108 #[doc = r"Clears the field bit"]
109 #[inline(always)]
110 pub fn clear_bit(self) -> &'a mut W {
111 self.bit(false)
112 }
113 #[doc = r"Writes raw bits to the field"]
114 #[inline(always)]
115 pub fn bit(self, value: bool) -> &'a mut W {
116 self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
117 self.w
118 }
119}
120#[doc = "Hardware Triggering Enable for this channel.\n\nValue on reset: 0"]
121#[derive(Clone, Copy, Debug, PartialEq)]
122pub enum HWTRIGEN_A {
123 #[doc = "0: Disabled. Hardware triggering is not used."]
124 DISABLED = 0,
125 #[doc = "1: Enabled. Use hardware triggering."]
126 ENABLED = 1,
127}
128impl From<HWTRIGEN_A> for bool {
129 #[inline(always)]
130 fn from(variant: HWTRIGEN_A) -> Self {
131 variant as u8 != 0
132 }
133}
134#[doc = "Field `HWTRIGEN` reader - Hardware Triggering Enable for this channel."]
135pub struct HWTRIGEN_R(crate::FieldReader<bool, HWTRIGEN_A>);
136impl HWTRIGEN_R {
137 pub(crate) fn new(bits: bool) -> Self {
138 HWTRIGEN_R(crate::FieldReader::new(bits))
139 }
140 #[doc = r"Get enumerated values variant"]
141 #[inline(always)]
142 pub fn variant(&self) -> HWTRIGEN_A {
143 match self.bits {
144 false => HWTRIGEN_A::DISABLED,
145 true => HWTRIGEN_A::ENABLED,
146 }
147 }
148 #[doc = "Checks if the value of the field is `DISABLED`"]
149 #[inline(always)]
150 pub fn is_disabled(&self) -> bool {
151 **self == HWTRIGEN_A::DISABLED
152 }
153 #[doc = "Checks if the value of the field is `ENABLED`"]
154 #[inline(always)]
155 pub fn is_enabled(&self) -> bool {
156 **self == HWTRIGEN_A::ENABLED
157 }
158}
159impl core::ops::Deref for HWTRIGEN_R {
160 type Target = crate::FieldReader<bool, HWTRIGEN_A>;
161 #[inline(always)]
162 fn deref(&self) -> &Self::Target {
163 &self.0
164 }
165}
166#[doc = "Field `HWTRIGEN` writer - Hardware Triggering Enable for this channel."]
167pub struct HWTRIGEN_W<'a> {
168 w: &'a mut W,
169}
170impl<'a> HWTRIGEN_W<'a> {
171 #[doc = r"Writes `variant` to the field"]
172 #[inline(always)]
173 pub fn variant(self, variant: HWTRIGEN_A) -> &'a mut W {
174 self.bit(variant.into())
175 }
176 #[doc = "Disabled. Hardware triggering is not used."]
177 #[inline(always)]
178 pub fn disabled(self) -> &'a mut W {
179 self.variant(HWTRIGEN_A::DISABLED)
180 }
181 #[doc = "Enabled. Use hardware triggering."]
182 #[inline(always)]
183 pub fn enabled(self) -> &'a mut W {
184 self.variant(HWTRIGEN_A::ENABLED)
185 }
186 #[doc = r"Sets the field bit"]
187 #[inline(always)]
188 pub fn set_bit(self) -> &'a mut W {
189 self.bit(true)
190 }
191 #[doc = r"Clears the field bit"]
192 #[inline(always)]
193 pub fn clear_bit(self) -> &'a mut W {
194 self.bit(false)
195 }
196 #[doc = r"Writes raw bits to the field"]
197 #[inline(always)]
198 pub fn bit(self, value: bool) -> &'a mut W {
199 self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
200 self.w
201 }
202}
203#[doc = "Trigger Polarity. Selects the polarity of a hardware trigger for this channel.\n\nValue on reset: 0"]
204#[derive(Clone, Copy, Debug, PartialEq)]
205pub enum TRIGPOL_A {
206 #[doc = "0: Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE."]
207 ACTIVE_LOW_FALLING = 0,
208 #[doc = "1: Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE."]
209 ACTIVE_HIGH_RISING = 1,
210}
211impl From<TRIGPOL_A> for bool {
212 #[inline(always)]
213 fn from(variant: TRIGPOL_A) -> Self {
214 variant as u8 != 0
215 }
216}
217#[doc = "Field `TRIGPOL` reader - Trigger Polarity. Selects the polarity of a hardware trigger for this channel."]
218pub struct TRIGPOL_R(crate::FieldReader<bool, TRIGPOL_A>);
219impl TRIGPOL_R {
220 pub(crate) fn new(bits: bool) -> Self {
221 TRIGPOL_R(crate::FieldReader::new(bits))
222 }
223 #[doc = r"Get enumerated values variant"]
224 #[inline(always)]
225 pub fn variant(&self) -> TRIGPOL_A {
226 match self.bits {
227 false => TRIGPOL_A::ACTIVE_LOW_FALLING,
228 true => TRIGPOL_A::ACTIVE_HIGH_RISING,
229 }
230 }
231 #[doc = "Checks if the value of the field is `ACTIVE_LOW_FALLING`"]
232 #[inline(always)]
233 pub fn is_active_low_falling(&self) -> bool {
234 **self == TRIGPOL_A::ACTIVE_LOW_FALLING
235 }
236 #[doc = "Checks if the value of the field is `ACTIVE_HIGH_RISING`"]
237 #[inline(always)]
238 pub fn is_active_high_rising(&self) -> bool {
239 **self == TRIGPOL_A::ACTIVE_HIGH_RISING
240 }
241}
242impl core::ops::Deref for TRIGPOL_R {
243 type Target = crate::FieldReader<bool, TRIGPOL_A>;
244 #[inline(always)]
245 fn deref(&self) -> &Self::Target {
246 &self.0
247 }
248}
249#[doc = "Field `TRIGPOL` writer - Trigger Polarity. Selects the polarity of a hardware trigger for this channel."]
250pub struct TRIGPOL_W<'a> {
251 w: &'a mut W,
252}
253impl<'a> TRIGPOL_W<'a> {
254 #[doc = r"Writes `variant` to the field"]
255 #[inline(always)]
256 pub fn variant(self, variant: TRIGPOL_A) -> &'a mut W {
257 self.bit(variant.into())
258 }
259 #[doc = "Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE."]
260 #[inline(always)]
261 pub fn active_low_falling(self) -> &'a mut W {
262 self.variant(TRIGPOL_A::ACTIVE_LOW_FALLING)
263 }
264 #[doc = "Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE."]
265 #[inline(always)]
266 pub fn active_high_rising(self) -> &'a mut W {
267 self.variant(TRIGPOL_A::ACTIVE_HIGH_RISING)
268 }
269 #[doc = r"Sets the field bit"]
270 #[inline(always)]
271 pub fn set_bit(self) -> &'a mut W {
272 self.bit(true)
273 }
274 #[doc = r"Clears the field bit"]
275 #[inline(always)]
276 pub fn clear_bit(self) -> &'a mut W {
277 self.bit(false)
278 }
279 #[doc = r"Writes raw bits to the field"]
280 #[inline(always)]
281 pub fn bit(self, value: bool) -> &'a mut W {
282 self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
283 self.w
284 }
285}
286#[doc = "Trigger Type. Selects hardware trigger as edge triggered or level triggered.\n\nValue on reset: 0"]
287#[derive(Clone, Copy, Debug, PartialEq)]
288pub enum TRIGTYPE_A {
289 #[doc = "0: Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger."]
290 EDGE = 0,
291 #[doc = "1: Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed."]
292 LEVEL = 1,
293}
294impl From<TRIGTYPE_A> for bool {
295 #[inline(always)]
296 fn from(variant: TRIGTYPE_A) -> Self {
297 variant as u8 != 0
298 }
299}
300#[doc = "Field `TRIGTYPE` reader - Trigger Type. Selects hardware trigger as edge triggered or level triggered."]
301pub struct TRIGTYPE_R(crate::FieldReader<bool, TRIGTYPE_A>);
302impl TRIGTYPE_R {
303 pub(crate) fn new(bits: bool) -> Self {
304 TRIGTYPE_R(crate::FieldReader::new(bits))
305 }
306 #[doc = r"Get enumerated values variant"]
307 #[inline(always)]
308 pub fn variant(&self) -> TRIGTYPE_A {
309 match self.bits {
310 false => TRIGTYPE_A::EDGE,
311 true => TRIGTYPE_A::LEVEL,
312 }
313 }
314 #[doc = "Checks if the value of the field is `EDGE`"]
315 #[inline(always)]
316 pub fn is_edge(&self) -> bool {
317 **self == TRIGTYPE_A::EDGE
318 }
319 #[doc = "Checks if the value of the field is `LEVEL`"]
320 #[inline(always)]
321 pub fn is_level(&self) -> bool {
322 **self == TRIGTYPE_A::LEVEL
323 }
324}
325impl core::ops::Deref for TRIGTYPE_R {
326 type Target = crate::FieldReader<bool, TRIGTYPE_A>;
327 #[inline(always)]
328 fn deref(&self) -> &Self::Target {
329 &self.0
330 }
331}
332#[doc = "Field `TRIGTYPE` writer - Trigger Type. Selects hardware trigger as edge triggered or level triggered."]
333pub struct TRIGTYPE_W<'a> {
334 w: &'a mut W,
335}
336impl<'a> TRIGTYPE_W<'a> {
337 #[doc = r"Writes `variant` to the field"]
338 #[inline(always)]
339 pub fn variant(self, variant: TRIGTYPE_A) -> &'a mut W {
340 self.bit(variant.into())
341 }
342 #[doc = "Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger."]
343 #[inline(always)]
344 pub fn edge(self) -> &'a mut W {
345 self.variant(TRIGTYPE_A::EDGE)
346 }
347 #[doc = "Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed."]
348 #[inline(always)]
349 pub fn level(self) -> &'a mut W {
350 self.variant(TRIGTYPE_A::LEVEL)
351 }
352 #[doc = r"Sets the field bit"]
353 #[inline(always)]
354 pub fn set_bit(self) -> &'a mut W {
355 self.bit(true)
356 }
357 #[doc = r"Clears the field bit"]
358 #[inline(always)]
359 pub fn clear_bit(self) -> &'a mut W {
360 self.bit(false)
361 }
362 #[doc = r"Writes raw bits to the field"]
363 #[inline(always)]
364 pub fn bit(self, value: bool) -> &'a mut W {
365 self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
366 self.w
367 }
368}
369#[doc = "Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.\n\nValue on reset: 0"]
370#[derive(Clone, Copy, Debug, PartialEq)]
371pub enum TRIGBURST_A {
372 #[doc = "0: Single transfer. Hardware trigger causes a single transfer."]
373 SINGLE = 0,
374 #[doc = "1: Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete."]
375 BURST = 1,
376}
377impl From<TRIGBURST_A> for bool {
378 #[inline(always)]
379 fn from(variant: TRIGBURST_A) -> Self {
380 variant as u8 != 0
381 }
382}
383#[doc = "Field `TRIGBURST` reader - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer."]
384pub struct TRIGBURST_R(crate::FieldReader<bool, TRIGBURST_A>);
385impl TRIGBURST_R {
386 pub(crate) fn new(bits: bool) -> Self {
387 TRIGBURST_R(crate::FieldReader::new(bits))
388 }
389 #[doc = r"Get enumerated values variant"]
390 #[inline(always)]
391 pub fn variant(&self) -> TRIGBURST_A {
392 match self.bits {
393 false => TRIGBURST_A::SINGLE,
394 true => TRIGBURST_A::BURST,
395 }
396 }
397 #[doc = "Checks if the value of the field is `SINGLE`"]
398 #[inline(always)]
399 pub fn is_single(&self) -> bool {
400 **self == TRIGBURST_A::SINGLE
401 }
402 #[doc = "Checks if the value of the field is `BURST`"]
403 #[inline(always)]
404 pub fn is_burst(&self) -> bool {
405 **self == TRIGBURST_A::BURST
406 }
407}
408impl core::ops::Deref for TRIGBURST_R {
409 type Target = crate::FieldReader<bool, TRIGBURST_A>;
410 #[inline(always)]
411 fn deref(&self) -> &Self::Target {
412 &self.0
413 }
414}
415#[doc = "Field `TRIGBURST` writer - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer."]
416pub struct TRIGBURST_W<'a> {
417 w: &'a mut W,
418}
419impl<'a> TRIGBURST_W<'a> {
420 #[doc = r"Writes `variant` to the field"]
421 #[inline(always)]
422 pub fn variant(self, variant: TRIGBURST_A) -> &'a mut W {
423 self.bit(variant.into())
424 }
425 #[doc = "Single transfer. Hardware trigger causes a single transfer."]
426 #[inline(always)]
427 pub fn single(self) -> &'a mut W {
428 self.variant(TRIGBURST_A::SINGLE)
429 }
430 #[doc = "Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete."]
431 #[inline(always)]
432 pub fn burst(self) -> &'a mut W {
433 self.variant(TRIGBURST_A::BURST)
434 }
435 #[doc = r"Sets the field bit"]
436 #[inline(always)]
437 pub fn set_bit(self) -> &'a mut W {
438 self.bit(true)
439 }
440 #[doc = r"Clears the field bit"]
441 #[inline(always)]
442 pub fn clear_bit(self) -> &'a mut W {
443 self.bit(false)
444 }
445 #[doc = r"Writes raw bits to the field"]
446 #[inline(always)]
447 pub fn bit(self, value: bool) -> &'a mut W {
448 self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
449 self.w
450 }
451}
452#[doc = "Field `BURSTPOWER` reader - Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size."]
453pub struct BURSTPOWER_R(crate::FieldReader<u8, u8>);
454impl BURSTPOWER_R {
455 pub(crate) fn new(bits: u8) -> Self {
456 BURSTPOWER_R(crate::FieldReader::new(bits))
457 }
458}
459impl core::ops::Deref for BURSTPOWER_R {
460 type Target = crate::FieldReader<u8, u8>;
461 #[inline(always)]
462 fn deref(&self) -> &Self::Target {
463 &self.0
464 }
465}
466#[doc = "Field `BURSTPOWER` writer - Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size."]
467pub struct BURSTPOWER_W<'a> {
468 w: &'a mut W,
469}
470impl<'a> BURSTPOWER_W<'a> {
471 #[doc = r"Writes raw bits to the field"]
472 #[inline(always)]
473 pub unsafe fn bits(self, value: u8) -> &'a mut W {
474 self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8);
475 self.w
476 }
477}
478#[doc = "Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.\n\nValue on reset: 0"]
479#[derive(Clone, Copy, Debug, PartialEq)]
480pub enum SRCBURSTWRAP_A {
481 #[doc = "0: Disabled. Source burst wrapping is not enabled for this DMA channel."]
482 DISABLED = 0,
483 #[doc = "1: Enabled. Source burst wrapping is enabled for this DMA channel."]
484 ENABLED = 1,
485}
486impl From<SRCBURSTWRAP_A> for bool {
487 #[inline(always)]
488 fn from(variant: SRCBURSTWRAP_A) -> Self {
489 variant as u8 != 0
490 }
491}
492#[doc = "Field `SRCBURSTWRAP` reader - Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst."]
493pub struct SRCBURSTWRAP_R(crate::FieldReader<bool, SRCBURSTWRAP_A>);
494impl SRCBURSTWRAP_R {
495 pub(crate) fn new(bits: bool) -> Self {
496 SRCBURSTWRAP_R(crate::FieldReader::new(bits))
497 }
498 #[doc = r"Get enumerated values variant"]
499 #[inline(always)]
500 pub fn variant(&self) -> SRCBURSTWRAP_A {
501 match self.bits {
502 false => SRCBURSTWRAP_A::DISABLED,
503 true => SRCBURSTWRAP_A::ENABLED,
504 }
505 }
506 #[doc = "Checks if the value of the field is `DISABLED`"]
507 #[inline(always)]
508 pub fn is_disabled(&self) -> bool {
509 **self == SRCBURSTWRAP_A::DISABLED
510 }
511 #[doc = "Checks if the value of the field is `ENABLED`"]
512 #[inline(always)]
513 pub fn is_enabled(&self) -> bool {
514 **self == SRCBURSTWRAP_A::ENABLED
515 }
516}
517impl core::ops::Deref for SRCBURSTWRAP_R {
518 type Target = crate::FieldReader<bool, SRCBURSTWRAP_A>;
519 #[inline(always)]
520 fn deref(&self) -> &Self::Target {
521 &self.0
522 }
523}
524#[doc = "Field `SRCBURSTWRAP` writer - Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst."]
525pub struct SRCBURSTWRAP_W<'a> {
526 w: &'a mut W,
527}
528impl<'a> SRCBURSTWRAP_W<'a> {
529 #[doc = r"Writes `variant` to the field"]
530 #[inline(always)]
531 pub fn variant(self, variant: SRCBURSTWRAP_A) -> &'a mut W {
532 self.bit(variant.into())
533 }
534 #[doc = "Disabled. Source burst wrapping is not enabled for this DMA channel."]
535 #[inline(always)]
536 pub fn disabled(self) -> &'a mut W {
537 self.variant(SRCBURSTWRAP_A::DISABLED)
538 }
539 #[doc = "Enabled. Source burst wrapping is enabled for this DMA channel."]
540 #[inline(always)]
541 pub fn enabled(self) -> &'a mut W {
542 self.variant(SRCBURSTWRAP_A::ENABLED)
543 }
544 #[doc = r"Sets the field bit"]
545 #[inline(always)]
546 pub fn set_bit(self) -> &'a mut W {
547 self.bit(true)
548 }
549 #[doc = r"Clears the field bit"]
550 #[inline(always)]
551 pub fn clear_bit(self) -> &'a mut W {
552 self.bit(false)
553 }
554 #[doc = r"Writes raw bits to the field"]
555 #[inline(always)]
556 pub fn bit(self, value: bool) -> &'a mut W {
557 self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14);
558 self.w
559 }
560}
561#[doc = "Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.\n\nValue on reset: 0"]
562#[derive(Clone, Copy, Debug, PartialEq)]
563pub enum DSTBURSTWRAP_A {
564 #[doc = "0: Disabled. Destination burst wrapping is not enabled for this DMA channel."]
565 DISABLED = 0,
566 #[doc = "1: Enabled. Destination burst wrapping is enabled for this DMA channel."]
567 ENABLED = 1,
568}
569impl From<DSTBURSTWRAP_A> for bool {
570 #[inline(always)]
571 fn from(variant: DSTBURSTWRAP_A) -> Self {
572 variant as u8 != 0
573 }
574}
575#[doc = "Field `DSTBURSTWRAP` reader - Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst."]
576pub struct DSTBURSTWRAP_R(crate::FieldReader<bool, DSTBURSTWRAP_A>);
577impl DSTBURSTWRAP_R {
578 pub(crate) fn new(bits: bool) -> Self {
579 DSTBURSTWRAP_R(crate::FieldReader::new(bits))
580 }
581 #[doc = r"Get enumerated values variant"]
582 #[inline(always)]
583 pub fn variant(&self) -> DSTBURSTWRAP_A {
584 match self.bits {
585 false => DSTBURSTWRAP_A::DISABLED,
586 true => DSTBURSTWRAP_A::ENABLED,
587 }
588 }
589 #[doc = "Checks if the value of the field is `DISABLED`"]
590 #[inline(always)]
591 pub fn is_disabled(&self) -> bool {
592 **self == DSTBURSTWRAP_A::DISABLED
593 }
594 #[doc = "Checks if the value of the field is `ENABLED`"]
595 #[inline(always)]
596 pub fn is_enabled(&self) -> bool {
597 **self == DSTBURSTWRAP_A::ENABLED
598 }
599}
600impl core::ops::Deref for DSTBURSTWRAP_R {
601 type Target = crate::FieldReader<bool, DSTBURSTWRAP_A>;
602 #[inline(always)]
603 fn deref(&self) -> &Self::Target {
604 &self.0
605 }
606}
607#[doc = "Field `DSTBURSTWRAP` writer - Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst."]
608pub struct DSTBURSTWRAP_W<'a> {
609 w: &'a mut W,
610}
611impl<'a> DSTBURSTWRAP_W<'a> {
612 #[doc = r"Writes `variant` to the field"]
613 #[inline(always)]
614 pub fn variant(self, variant: DSTBURSTWRAP_A) -> &'a mut W {
615 self.bit(variant.into())
616 }
617 #[doc = "Disabled. Destination burst wrapping is not enabled for this DMA channel."]
618 #[inline(always)]
619 pub fn disabled(self) -> &'a mut W {
620 self.variant(DSTBURSTWRAP_A::DISABLED)
621 }
622 #[doc = "Enabled. Destination burst wrapping is enabled for this DMA channel."]
623 #[inline(always)]
624 pub fn enabled(self) -> &'a mut W {
625 self.variant(DSTBURSTWRAP_A::ENABLED)
626 }
627 #[doc = r"Sets the field bit"]
628 #[inline(always)]
629 pub fn set_bit(self) -> &'a mut W {
630 self.bit(true)
631 }
632 #[doc = r"Clears the field bit"]
633 #[inline(always)]
634 pub fn clear_bit(self) -> &'a mut W {
635 self.bit(false)
636 }
637 #[doc = r"Writes raw bits to the field"]
638 #[inline(always)]
639 pub fn bit(self, value: bool) -> &'a mut W {
640 self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15);
641 self.w
642 }
643}
644#[doc = "Field `CHPRIORITY` reader - Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority."]
645pub struct CHPRIORITY_R(crate::FieldReader<u8, u8>);
646impl CHPRIORITY_R {
647 pub(crate) fn new(bits: u8) -> Self {
648 CHPRIORITY_R(crate::FieldReader::new(bits))
649 }
650}
651impl core::ops::Deref for CHPRIORITY_R {
652 type Target = crate::FieldReader<u8, u8>;
653 #[inline(always)]
654 fn deref(&self) -> &Self::Target {
655 &self.0
656 }
657}
658#[doc = "Field `CHPRIORITY` writer - Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority."]
659pub struct CHPRIORITY_W<'a> {
660 w: &'a mut W,
661}
662impl<'a> CHPRIORITY_W<'a> {
663 #[doc = r"Writes raw bits to the field"]
664 #[inline(always)]
665 pub unsafe fn bits(self, value: u8) -> &'a mut W {
666 self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16);
667 self.w
668 }
669}
670impl R {
671 #[doc = "Bit 0 - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller."]
672 #[inline(always)]
673 pub fn periphreqen(&self) -> PERIPHREQEN_R {
674 PERIPHREQEN_R::new((self.bits & 0x01) != 0)
675 }
676 #[doc = "Bit 1 - Hardware Triggering Enable for this channel."]
677 #[inline(always)]
678 pub fn hwtrigen(&self) -> HWTRIGEN_R {
679 HWTRIGEN_R::new(((self.bits >> 1) & 0x01) != 0)
680 }
681 #[doc = "Bit 4 - Trigger Polarity. Selects the polarity of a hardware trigger for this channel."]
682 #[inline(always)]
683 pub fn trigpol(&self) -> TRIGPOL_R {
684 TRIGPOL_R::new(((self.bits >> 4) & 0x01) != 0)
685 }
686 #[doc = "Bit 5 - Trigger Type. Selects hardware trigger as edge triggered or level triggered."]
687 #[inline(always)]
688 pub fn trigtype(&self) -> TRIGTYPE_R {
689 TRIGTYPE_R::new(((self.bits >> 5) & 0x01) != 0)
690 }
691 #[doc = "Bit 6 - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer."]
692 #[inline(always)]
693 pub fn trigburst(&self) -> TRIGBURST_R {
694 TRIGBURST_R::new(((self.bits >> 6) & 0x01) != 0)
695 }
696 #[doc = "Bits 8:11 - Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size."]
697 #[inline(always)]
698 pub fn burstpower(&self) -> BURSTPOWER_R {
699 BURSTPOWER_R::new(((self.bits >> 8) & 0x0f) as u8)
700 }
701 #[doc = "Bit 14 - Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst."]
702 #[inline(always)]
703 pub fn srcburstwrap(&self) -> SRCBURSTWRAP_R {
704 SRCBURSTWRAP_R::new(((self.bits >> 14) & 0x01) != 0)
705 }
706 #[doc = "Bit 15 - Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst."]
707 #[inline(always)]
708 pub fn dstburstwrap(&self) -> DSTBURSTWRAP_R {
709 DSTBURSTWRAP_R::new(((self.bits >> 15) & 0x01) != 0)
710 }
711 #[doc = "Bits 16:18 - Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority."]
712 #[inline(always)]
713 pub fn chpriority(&self) -> CHPRIORITY_R {
714 CHPRIORITY_R::new(((self.bits >> 16) & 0x07) as u8)
715 }
716}
717impl W {
718 #[doc = "Bit 0 - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller."]
719 #[inline(always)]
720 pub fn periphreqen(&mut self) -> PERIPHREQEN_W {
721 PERIPHREQEN_W { w: self }
722 }
723 #[doc = "Bit 1 - Hardware Triggering Enable for this channel."]
724 #[inline(always)]
725 pub fn hwtrigen(&mut self) -> HWTRIGEN_W {
726 HWTRIGEN_W { w: self }
727 }
728 #[doc = "Bit 4 - Trigger Polarity. Selects the polarity of a hardware trigger for this channel."]
729 #[inline(always)]
730 pub fn trigpol(&mut self) -> TRIGPOL_W {
731 TRIGPOL_W { w: self }
732 }
733 #[doc = "Bit 5 - Trigger Type. Selects hardware trigger as edge triggered or level triggered."]
734 #[inline(always)]
735 pub fn trigtype(&mut self) -> TRIGTYPE_W {
736 TRIGTYPE_W { w: self }
737 }
738 #[doc = "Bit 6 - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer."]
739 #[inline(always)]
740 pub fn trigburst(&mut self) -> TRIGBURST_W {
741 TRIGBURST_W { w: self }
742 }
743 #[doc = "Bits 8:11 - Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many transfers are performed for each DMA trigger. This can be used, for example, with peripherals that contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even multiple of the burst size."]
744 #[inline(always)]
745 pub fn burstpower(&mut self) -> BURSTPOWER_W {
746 BURSTPOWER_W { w: self }
747 }
748 #[doc = "Bit 14 - Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst."]
749 #[inline(always)]
750 pub fn srcburstwrap(&mut self) -> SRCBURSTWRAP_W {
751 SRCBURSTWRAP_W { w: self }
752 }
753 #[doc = "Bit 15 - Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst."]
754 #[inline(always)]
755 pub fn dstburstwrap(&mut self) -> DSTBURSTWRAP_W {
756 DSTBURSTWRAP_W { w: self }
757 }
758 #[doc = "Bits 16:18 - Priority of this channel when multiple DMA requests are pending. Eight priority levels are supported: 0x0 = highest priority. 0x7 = lowest priority."]
759 #[inline(always)]
760 pub fn chpriority(&mut self) -> CHPRIORITY_W {
761 CHPRIORITY_W { w: self }
762 }
763 #[doc = "Writes raw bits to the register."]
764 #[inline(always)]
765 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
766 self.0.bits(bits);
767 self
768 }
769}
770#[doc = "Configuration register for DMA channel .\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
771pub struct CFG_SPEC;
772impl crate::RegisterSpec for CFG_SPEC {
773 type Ux = u32;
774}
775#[doc = "`read()` method returns [cfg::R](R) reader structure"]
776impl crate::Readable for CFG_SPEC {
777 type Reader = R;
778}
779#[doc = "`write(|w| ..)` method takes [cfg::W](W) writer structure"]
780impl crate::Writable for CFG_SPEC {
781 type Writer = W;
782}
783#[doc = "`reset()` method sets CFG to value 0"]
784impl crate::Resettable for CFG_SPEC {
785 #[inline(always)]
786 fn reset_value() -> Self::Ux {
787 0
788 }
789}