lpc82x_pac/dma0/
busy0.rs

1#[doc = "Register `BUSY0` reader"]
2pub struct R(crate::R<BUSY0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<BUSY0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<BUSY0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<BUSY0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `BSY` reader - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy."]
17pub struct BSY_R(crate::FieldReader<u32, u32>);
18impl BSY_R {
19    pub(crate) fn new(bits: u32) -> Self {
20        BSY_R(crate::FieldReader::new(bits))
21    }
22}
23impl core::ops::Deref for BSY_R {
24    type Target = crate::FieldReader<u32, u32>;
25    #[inline(always)]
26    fn deref(&self) -> &Self::Target {
27        &self.0
28    }
29}
30impl R {
31    #[doc = "Bits 0:17 - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy."]
32    #[inline(always)]
33    pub fn bsy(&self) -> BSY_R {
34        BSY_R::new((self.bits & 0x0003_ffff) as u32)
35    }
36}
37#[doc = "Channel Busy status for all DMA channels.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [busy0](index.html) module"]
38pub struct BUSY0_SPEC;
39impl crate::RegisterSpec for BUSY0_SPEC {
40    type Ux = u32;
41}
42#[doc = "`read()` method returns [busy0::R](R) reader structure"]
43impl crate::Readable for BUSY0_SPEC {
44    type Reader = R;
45}
46#[doc = "`reset()` method sets BUSY0 to value 0"]
47impl crate::Resettable for BUSY0_SPEC {
48    #[inline(always)]
49    fn reset_value() -> Self::Ux {
50        0
51    }
52}
lpc82x_pac/dma0/busy0.rs

lpc82x_pac/dma0/
busy0.rs
