1#[doc = "Register `SEQ_CTRL%s` reader"]
2pub struct R(crate::R<SEQ_CTRL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<SEQ_CTRL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<SEQ_CTRL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<SEQ_CTRL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `SEQ_CTRL%s` writer"]
17pub struct W(crate::W<SEQ_CTRL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<SEQ_CTRL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<SEQ_CTRL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<SEQ_CTRL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `CHANNELS` reader - Selects which one or more of the ADC channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, ADC conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31) is LOW. It is allowed to change this field and set bit 31 in the same write."]
38pub struct CHANNELS_R(crate::FieldReader<u16, u16>);
39impl CHANNELS_R {
40 pub(crate) fn new(bits: u16) -> Self {
41 CHANNELS_R(crate::FieldReader::new(bits))
42 }
43}
44impl core::ops::Deref for CHANNELS_R {
45 type Target = crate::FieldReader<u16, u16>;
46 #[inline(always)]
47 fn deref(&self) -> &Self::Target {
48 &self.0
49 }
50}
51#[doc = "Field `CHANNELS` writer - Selects which one or more of the ADC channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, ADC conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31) is LOW. It is allowed to change this field and set bit 31 in the same write."]
52pub struct CHANNELS_W<'a> {
53 w: &'a mut W,
54}
55impl<'a> CHANNELS_W<'a> {
56 #[doc = r"Writes raw bits to the field"]
57 #[inline(always)]
58 pub unsafe fn bits(self, value: u16) -> &'a mut W {
59 self.w.bits = (self.w.bits & !0x0fff) | (value as u32 & 0x0fff);
60 self.w
61 }
62}
63#[doc = "Field `TRIGGER` reader - Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. See Table 476. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write."]
64pub struct TRIGGER_R(crate::FieldReader<u8, u8>);
65impl TRIGGER_R {
66 pub(crate) fn new(bits: u8) -> Self {
67 TRIGGER_R(crate::FieldReader::new(bits))
68 }
69}
70impl core::ops::Deref for TRIGGER_R {
71 type Target = crate::FieldReader<u8, u8>;
72 #[inline(always)]
73 fn deref(&self) -> &Self::Target {
74 &self.0
75 }
76}
77#[doc = "Field `TRIGGER` writer - Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. See Table 476. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write."]
78pub struct TRIGGER_W<'a> {
79 w: &'a mut W,
80}
81impl<'a> TRIGGER_W<'a> {
82 #[doc = r"Writes raw bits to the field"]
83 #[inline(always)]
84 pub unsafe fn bits(self, value: u8) -> &'a mut W {
85 self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u32 & 0x07) << 12);
86 self.w
87 }
88}
89#[doc = "Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.\n\nValue on reset: 0"]
90#[derive(Clone, Copy, Debug, PartialEq)]
91pub enum TRIGPOL_A {
92 #[doc = "0: Negative edge. A negative edge launches the conversion sequence on the selected trigger input."]
93 NEGATIVE_EDGE = 0,
94 #[doc = "1: Positive edge. A positive edge launches the conversion sequence on the selected trigger input."]
95 POSITIVE_EDGE = 1,
96}
97impl From<TRIGPOL_A> for bool {
98 #[inline(always)]
99 fn from(variant: TRIGPOL_A) -> Self {
100 variant as u8 != 0
101 }
102}
103#[doc = "Field `TRIGPOL` reader - Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write."]
104pub struct TRIGPOL_R(crate::FieldReader<bool, TRIGPOL_A>);
105impl TRIGPOL_R {
106 pub(crate) fn new(bits: bool) -> Self {
107 TRIGPOL_R(crate::FieldReader::new(bits))
108 }
109 #[doc = r"Get enumerated values variant"]
110 #[inline(always)]
111 pub fn variant(&self) -> TRIGPOL_A {
112 match self.bits {
113 false => TRIGPOL_A::NEGATIVE_EDGE,
114 true => TRIGPOL_A::POSITIVE_EDGE,
115 }
116 }
117 #[doc = "Checks if the value of the field is `NEGATIVE_EDGE`"]
118 #[inline(always)]
119 pub fn is_negative_edge(&self) -> bool {
120 **self == TRIGPOL_A::NEGATIVE_EDGE
121 }
122 #[doc = "Checks if the value of the field is `POSITIVE_EDGE`"]
123 #[inline(always)]
124 pub fn is_positive_edge(&self) -> bool {
125 **self == TRIGPOL_A::POSITIVE_EDGE
126 }
127}
128impl core::ops::Deref for TRIGPOL_R {
129 type Target = crate::FieldReader<bool, TRIGPOL_A>;
130 #[inline(always)]
131 fn deref(&self) -> &Self::Target {
132 &self.0
133 }
134}
135#[doc = "Field `TRIGPOL` writer - Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write."]
136pub struct TRIGPOL_W<'a> {
137 w: &'a mut W,
138}
139impl<'a> TRIGPOL_W<'a> {
140 #[doc = r"Writes `variant` to the field"]
141 #[inline(always)]
142 pub fn variant(self, variant: TRIGPOL_A) -> &'a mut W {
143 self.bit(variant.into())
144 }
145 #[doc = "Negative edge. A negative edge launches the conversion sequence on the selected trigger input."]
146 #[inline(always)]
147 pub fn negative_edge(self) -> &'a mut W {
148 self.variant(TRIGPOL_A::NEGATIVE_EDGE)
149 }
150 #[doc = "Positive edge. A positive edge launches the conversion sequence on the selected trigger input."]
151 #[inline(always)]
152 pub fn positive_edge(self) -> &'a mut W {
153 self.variant(TRIGPOL_A::POSITIVE_EDGE)
154 }
155 #[doc = r"Sets the field bit"]
156 #[inline(always)]
157 pub fn set_bit(self) -> &'a mut W {
158 self.bit(true)
159 }
160 #[doc = r"Clears the field bit"]
161 #[inline(always)]
162 pub fn clear_bit(self) -> &'a mut W {
163 self.bit(false)
164 }
165 #[doc = r"Writes raw bits to the field"]
166 #[inline(always)]
167 pub fn bit(self, value: bool) -> &'a mut W {
168 self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18);
169 self.w
170 }
171}
172#[doc = "Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period.\n\nValue on reset: 0"]
173#[derive(Clone, Copy, Debug, PartialEq)]
174pub enum SYNCBYPASS_A {
175 #[doc = "0: Enable trigger synchronization. The hardware trigger bypass is not enabled."]
176 ENABLE_TRIGGER_SYNCH = 0,
177 #[doc = "1: Bypass trigger synchronization. The hardware trigger bypass is enabled."]
178 BYPASS_TRIGGER_SYNCH = 1,
179}
180impl From<SYNCBYPASS_A> for bool {
181 #[inline(always)]
182 fn from(variant: SYNCBYPASS_A) -> Self {
183 variant as u8 != 0
184 }
185}
186#[doc = "Field `SYNCBYPASS` reader - Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period."]
187pub struct SYNCBYPASS_R(crate::FieldReader<bool, SYNCBYPASS_A>);
188impl SYNCBYPASS_R {
189 pub(crate) fn new(bits: bool) -> Self {
190 SYNCBYPASS_R(crate::FieldReader::new(bits))
191 }
192 #[doc = r"Get enumerated values variant"]
193 #[inline(always)]
194 pub fn variant(&self) -> SYNCBYPASS_A {
195 match self.bits {
196 false => SYNCBYPASS_A::ENABLE_TRIGGER_SYNCH,
197 true => SYNCBYPASS_A::BYPASS_TRIGGER_SYNCH,
198 }
199 }
200 #[doc = "Checks if the value of the field is `ENABLE_TRIGGER_SYNCH`"]
201 #[inline(always)]
202 pub fn is_enable_trigger_synch(&self) -> bool {
203 **self == SYNCBYPASS_A::ENABLE_TRIGGER_SYNCH
204 }
205 #[doc = "Checks if the value of the field is `BYPASS_TRIGGER_SYNCH`"]
206 #[inline(always)]
207 pub fn is_bypass_trigger_synch(&self) -> bool {
208 **self == SYNCBYPASS_A::BYPASS_TRIGGER_SYNCH
209 }
210}
211impl core::ops::Deref for SYNCBYPASS_R {
212 type Target = crate::FieldReader<bool, SYNCBYPASS_A>;
213 #[inline(always)]
214 fn deref(&self) -> &Self::Target {
215 &self.0
216 }
217}
218#[doc = "Field `SYNCBYPASS` writer - Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period."]
219pub struct SYNCBYPASS_W<'a> {
220 w: &'a mut W,
221}
222impl<'a> SYNCBYPASS_W<'a> {
223 #[doc = r"Writes `variant` to the field"]
224 #[inline(always)]
225 pub fn variant(self, variant: SYNCBYPASS_A) -> &'a mut W {
226 self.bit(variant.into())
227 }
228 #[doc = "Enable trigger synchronization. The hardware trigger bypass is not enabled."]
229 #[inline(always)]
230 pub fn enable_trigger_synch(self) -> &'a mut W {
231 self.variant(SYNCBYPASS_A::ENABLE_TRIGGER_SYNCH)
232 }
233 #[doc = "Bypass trigger synchronization. The hardware trigger bypass is enabled."]
234 #[inline(always)]
235 pub fn bypass_trigger_synch(self) -> &'a mut W {
236 self.variant(SYNCBYPASS_A::BYPASS_TRIGGER_SYNCH)
237 }
238 #[doc = r"Sets the field bit"]
239 #[inline(always)]
240 pub fn set_bit(self) -> &'a mut W {
241 self.bit(true)
242 }
243 #[doc = r"Clears the field bit"]
244 #[inline(always)]
245 pub fn clear_bit(self) -> &'a mut W {
246 self.bit(false)
247 }
248 #[doc = r"Writes raw bits to the field"]
249 #[inline(always)]
250 pub fn bit(self, value: bool) -> &'a mut W {
251 self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19);
252 self.w
253 }
254}
255#[doc = "Field `START` reader - Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a conversion sequence. It will consequently always read back as a zero."]
256pub struct START_R(crate::FieldReader<bool, bool>);
257impl START_R {
258 pub(crate) fn new(bits: bool) -> Self {
259 START_R(crate::FieldReader::new(bits))
260 }
261}
262impl core::ops::Deref for START_R {
263 type Target = crate::FieldReader<bool, bool>;
264 #[inline(always)]
265 fn deref(&self) -> &Self::Target {
266 &self.0
267 }
268}
269#[doc = "Field `START` writer - Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a conversion sequence. It will consequently always read back as a zero."]
270pub struct START_W<'a> {
271 w: &'a mut W,
272}
273impl<'a> START_W<'a> {
274 #[doc = r"Sets the field bit"]
275 #[inline(always)]
276 pub fn set_bit(self) -> &'a mut W {
277 self.bit(true)
278 }
279 #[doc = r"Clears the field bit"]
280 #[inline(always)]
281 pub fn clear_bit(self) -> &'a mut W {
282 self.bit(false)
283 }
284 #[doc = r"Writes raw bits to the field"]
285 #[inline(always)]
286 pub fn bit(self, value: bool) -> &'a mut W {
287 self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26);
288 self.w
289 }
290}
291#[doc = "Field `BURST` reader - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated. Note that a new sequence could begin just before BURST is cleared."]
292pub struct BURST_R(crate::FieldReader<bool, bool>);
293impl BURST_R {
294 pub(crate) fn new(bits: bool) -> Self {
295 BURST_R(crate::FieldReader::new(bits))
296 }
297}
298impl core::ops::Deref for BURST_R {
299 type Target = crate::FieldReader<bool, bool>;
300 #[inline(always)]
301 fn deref(&self) -> &Self::Target {
302 &self.0
303 }
304}
305#[doc = "Field `BURST` writer - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated. Note that a new sequence could begin just before BURST is cleared."]
306pub struct BURST_W<'a> {
307 w: &'a mut W,
308}
309impl<'a> BURST_W<'a> {
310 #[doc = r"Sets the field bit"]
311 #[inline(always)]
312 pub fn set_bit(self) -> &'a mut W {
313 self.bit(true)
314 }
315 #[doc = r"Clears the field bit"]
316 #[inline(always)]
317 pub fn clear_bit(self) -> &'a mut W {
318 self.bit(false)
319 }
320 #[doc = r"Writes raw bits to the field"]
321 #[inline(always)]
322 pub fn bit(self, value: bool) -> &'a mut W {
323 self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27);
324 self.w
325 }
326}
327#[doc = "Field `SINGLESTEP` reader - When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit."]
328pub struct SINGLESTEP_R(crate::FieldReader<bool, bool>);
329impl SINGLESTEP_R {
330 pub(crate) fn new(bits: bool) -> Self {
331 SINGLESTEP_R(crate::FieldReader::new(bits))
332 }
333}
334impl core::ops::Deref for SINGLESTEP_R {
335 type Target = crate::FieldReader<bool, bool>;
336 #[inline(always)]
337 fn deref(&self) -> &Self::Target {
338 &self.0
339 }
340}
341#[doc = "Field `SINGLESTEP` writer - When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit."]
342pub struct SINGLESTEP_W<'a> {
343 w: &'a mut W,
344}
345impl<'a> SINGLESTEP_W<'a> {
346 #[doc = r"Sets the field bit"]
347 #[inline(always)]
348 pub fn set_bit(self) -> &'a mut W {
349 self.bit(true)
350 }
351 #[doc = r"Clears the field bit"]
352 #[inline(always)]
353 pub fn clear_bit(self) -> &'a mut W {
354 self.bit(false)
355 }
356 #[doc = r"Writes raw bits to the field"]
357 #[inline(always)]
358 pub fn bit(self, value: bool) -> &'a mut W {
359 self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28);
360 self.w
361 }
362}
363#[doc = "Set priority for sequence A.\n\nValue on reset: 0"]
364#[derive(Clone, Copy, Debug, PartialEq)]
365pub enum LOWPRIO_A {
366 #[doc = "0: Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost."]
367 LOW_PRIORITY = 0,
368 #[doc = "1: High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion currently in progress will be terminated. The A sequence that was interrupted will automatically resume after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the conversion sequence will resume from that point."]
369 HIGH_PRIORITY = 1,
370}
371impl From<LOWPRIO_A> for bool {
372 #[inline(always)]
373 fn from(variant: LOWPRIO_A) -> Self {
374 variant as u8 != 0
375 }
376}
377#[doc = "Field `LOWPRIO` reader - Set priority for sequence A."]
378pub struct LOWPRIO_R(crate::FieldReader<bool, LOWPRIO_A>);
379impl LOWPRIO_R {
380 pub(crate) fn new(bits: bool) -> Self {
381 LOWPRIO_R(crate::FieldReader::new(bits))
382 }
383 #[doc = r"Get enumerated values variant"]
384 #[inline(always)]
385 pub fn variant(&self) -> LOWPRIO_A {
386 match self.bits {
387 false => LOWPRIO_A::LOW_PRIORITY,
388 true => LOWPRIO_A::HIGH_PRIORITY,
389 }
390 }
391 #[doc = "Checks if the value of the field is `LOW_PRIORITY`"]
392 #[inline(always)]
393 pub fn is_low_priority(&self) -> bool {
394 **self == LOWPRIO_A::LOW_PRIORITY
395 }
396 #[doc = "Checks if the value of the field is `HIGH_PRIORITY`"]
397 #[inline(always)]
398 pub fn is_high_priority(&self) -> bool {
399 **self == LOWPRIO_A::HIGH_PRIORITY
400 }
401}
402impl core::ops::Deref for LOWPRIO_R {
403 type Target = crate::FieldReader<bool, LOWPRIO_A>;
404 #[inline(always)]
405 fn deref(&self) -> &Self::Target {
406 &self.0
407 }
408}
409#[doc = "Field `LOWPRIO` writer - Set priority for sequence A."]
410pub struct LOWPRIO_W<'a> {
411 w: &'a mut W,
412}
413impl<'a> LOWPRIO_W<'a> {
414 #[doc = r"Writes `variant` to the field"]
415 #[inline(always)]
416 pub fn variant(self, variant: LOWPRIO_A) -> &'a mut W {
417 self.bit(variant.into())
418 }
419 #[doc = "Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost."]
420 #[inline(always)]
421 pub fn low_priority(self) -> &'a mut W {
422 self.variant(LOWPRIO_A::LOW_PRIORITY)
423 }
424 #[doc = "High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion currently in progress will be terminated. The A sequence that was interrupted will automatically resume after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the conversion sequence will resume from that point."]
425 #[inline(always)]
426 pub fn high_priority(self) -> &'a mut W {
427 self.variant(LOWPRIO_A::HIGH_PRIORITY)
428 }
429 #[doc = r"Sets the field bit"]
430 #[inline(always)]
431 pub fn set_bit(self) -> &'a mut W {
432 self.bit(true)
433 }
434 #[doc = r"Clears the field bit"]
435 #[inline(always)]
436 pub fn clear_bit(self) -> &'a mut W {
437 self.bit(false)
438 }
439 #[doc = r"Writes raw bits to the field"]
440 #[inline(always)]
441 pub fn bit(self, value: bool) -> &'a mut W {
442 self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29);
443 self.w
444 }
445}
446#[doc = "Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below.\n\nValue on reset: 0"]
447#[derive(Clone, Copy, Debug, PartialEq)]
448pub enum MODE_A {
449 #[doc = "0: End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger if enabled."]
450 END_OF_CONVERSION = 0,
451 #[doc = "1: End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun interrupt/DMA trigger since it is assumed this register may not be utilized in this mode."]
452 END_OF_SEQUENCE = 1,
453}
454impl From<MODE_A> for bool {
455 #[inline(always)]
456 fn from(variant: MODE_A) -> Self {
457 variant as u8 != 0
458 }
459}
460#[doc = "Field `MODE` reader - Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below."]
461pub struct MODE_R(crate::FieldReader<bool, MODE_A>);
462impl MODE_R {
463 pub(crate) fn new(bits: bool) -> Self {
464 MODE_R(crate::FieldReader::new(bits))
465 }
466 #[doc = r"Get enumerated values variant"]
467 #[inline(always)]
468 pub fn variant(&self) -> MODE_A {
469 match self.bits {
470 false => MODE_A::END_OF_CONVERSION,
471 true => MODE_A::END_OF_SEQUENCE,
472 }
473 }
474 #[doc = "Checks if the value of the field is `END_OF_CONVERSION`"]
475 #[inline(always)]
476 pub fn is_end_of_conversion(&self) -> bool {
477 **self == MODE_A::END_OF_CONVERSION
478 }
479 #[doc = "Checks if the value of the field is `END_OF_SEQUENCE`"]
480 #[inline(always)]
481 pub fn is_end_of_sequence(&self) -> bool {
482 **self == MODE_A::END_OF_SEQUENCE
483 }
484}
485impl core::ops::Deref for MODE_R {
486 type Target = crate::FieldReader<bool, MODE_A>;
487 #[inline(always)]
488 fn deref(&self) -> &Self::Target {
489 &self.0
490 }
491}
492#[doc = "Field `MODE` writer - Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below."]
493pub struct MODE_W<'a> {
494 w: &'a mut W,
495}
496impl<'a> MODE_W<'a> {
497 #[doc = r"Writes `variant` to the field"]
498 #[inline(always)]
499 pub fn variant(self, variant: MODE_A) -> &'a mut W {
500 self.bit(variant.into())
501 }
502 #[doc = "End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger if enabled."]
503 #[inline(always)]
504 pub fn end_of_conversion(self) -> &'a mut W {
505 self.variant(MODE_A::END_OF_CONVERSION)
506 }
507 #[doc = "End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun interrupt/DMA trigger since it is assumed this register may not be utilized in this mode."]
508 #[inline(always)]
509 pub fn end_of_sequence(self) -> &'a mut W {
510 self.variant(MODE_A::END_OF_SEQUENCE)
511 }
512 #[doc = r"Sets the field bit"]
513 #[inline(always)]
514 pub fn set_bit(self) -> &'a mut W {
515 self.bit(true)
516 }
517 #[doc = r"Clears the field bit"]
518 #[inline(always)]
519 pub fn clear_bit(self) -> &'a mut W {
520 self.bit(false)
521 }
522 #[doc = r"Writes raw bits to the field"]
523 #[inline(always)]
524 pub fn bit(self, value: bool) -> &'a mut W {
525 self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30);
526 self.w
527 }
528}
529#[doc = "Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled.\n\nValue on reset: 0"]
530#[derive(Clone, Copy, Debug, PartialEq)]
531pub enum SEQ_ENA_A {
532 #[doc = "0: Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel."]
533 DISABLED = 0,
534 #[doc = "1: Enabled. Sequence n is enabled."]
535 ENABLED = 1,
536}
537impl From<SEQ_ENA_A> for bool {
538 #[inline(always)]
539 fn from(variant: SEQ_ENA_A) -> Self {
540 variant as u8 != 0
541 }
542}
543#[doc = "Field `SEQ_ENA` reader - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled."]
544pub struct SEQ_ENA_R(crate::FieldReader<bool, SEQ_ENA_A>);
545impl SEQ_ENA_R {
546 pub(crate) fn new(bits: bool) -> Self {
547 SEQ_ENA_R(crate::FieldReader::new(bits))
548 }
549 #[doc = r"Get enumerated values variant"]
550 #[inline(always)]
551 pub fn variant(&self) -> SEQ_ENA_A {
552 match self.bits {
553 false => SEQ_ENA_A::DISABLED,
554 true => SEQ_ENA_A::ENABLED,
555 }
556 }
557 #[doc = "Checks if the value of the field is `DISABLED`"]
558 #[inline(always)]
559 pub fn is_disabled(&self) -> bool {
560 **self == SEQ_ENA_A::DISABLED
561 }
562 #[doc = "Checks if the value of the field is `ENABLED`"]
563 #[inline(always)]
564 pub fn is_enabled(&self) -> bool {
565 **self == SEQ_ENA_A::ENABLED
566 }
567}
568impl core::ops::Deref for SEQ_ENA_R {
569 type Target = crate::FieldReader<bool, SEQ_ENA_A>;
570 #[inline(always)]
571 fn deref(&self) -> &Self::Target {
572 &self.0
573 }
574}
575#[doc = "Field `SEQ_ENA` writer - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled."]
576pub struct SEQ_ENA_W<'a> {
577 w: &'a mut W,
578}
579impl<'a> SEQ_ENA_W<'a> {
580 #[doc = r"Writes `variant` to the field"]
581 #[inline(always)]
582 pub fn variant(self, variant: SEQ_ENA_A) -> &'a mut W {
583 self.bit(variant.into())
584 }
585 #[doc = "Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel."]
586 #[inline(always)]
587 pub fn disabled(self) -> &'a mut W {
588 self.variant(SEQ_ENA_A::DISABLED)
589 }
590 #[doc = "Enabled. Sequence n is enabled."]
591 #[inline(always)]
592 pub fn enabled(self) -> &'a mut W {
593 self.variant(SEQ_ENA_A::ENABLED)
594 }
595 #[doc = r"Sets the field bit"]
596 #[inline(always)]
597 pub fn set_bit(self) -> &'a mut W {
598 self.bit(true)
599 }
600 #[doc = r"Clears the field bit"]
601 #[inline(always)]
602 pub fn clear_bit(self) -> &'a mut W {
603 self.bit(false)
604 }
605 #[doc = r"Writes raw bits to the field"]
606 #[inline(always)]
607 pub fn bit(self, value: bool) -> &'a mut W {
608 self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
609 self.w
610 }
611}
612impl R {
613 #[doc = "Bits 0:11 - Selects which one or more of the ADC channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, ADC conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31) is LOW. It is allowed to change this field and set bit 31 in the same write."]
614 #[inline(always)]
615 pub fn channels(&self) -> CHANNELS_R {
616 CHANNELS_R::new((self.bits & 0x0fff) as u16)
617 }
618 #[doc = "Bits 12:14 - Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. See Table 476. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write."]
619 #[inline(always)]
620 pub fn trigger(&self) -> TRIGGER_R {
621 TRIGGER_R::new(((self.bits >> 12) & 0x07) as u8)
622 }
623 #[doc = "Bit 18 - Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write."]
624 #[inline(always)]
625 pub fn trigpol(&self) -> TRIGPOL_R {
626 TRIGPOL_R::new(((self.bits >> 18) & 0x01) != 0)
627 }
628 #[doc = "Bit 19 - Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period."]
629 #[inline(always)]
630 pub fn syncbypass(&self) -> SYNCBYPASS_R {
631 SYNCBYPASS_R::new(((self.bits >> 19) & 0x01) != 0)
632 }
633 #[doc = "Bit 26 - Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a conversion sequence. It will consequently always read back as a zero."]
634 #[inline(always)]
635 pub fn start(&self) -> START_R {
636 START_R::new(((self.bits >> 26) & 0x01) != 0)
637 }
638 #[doc = "Bit 27 - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated. Note that a new sequence could begin just before BURST is cleared."]
639 #[inline(always)]
640 pub fn burst(&self) -> BURST_R {
641 BURST_R::new(((self.bits >> 27) & 0x01) != 0)
642 }
643 #[doc = "Bit 28 - When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit."]
644 #[inline(always)]
645 pub fn singlestep(&self) -> SINGLESTEP_R {
646 SINGLESTEP_R::new(((self.bits >> 28) & 0x01) != 0)
647 }
648 #[doc = "Bit 29 - Set priority for sequence A."]
649 #[inline(always)]
650 pub fn lowprio(&self) -> LOWPRIO_R {
651 LOWPRIO_R::new(((self.bits >> 29) & 0x01) != 0)
652 }
653 #[doc = "Bit 30 - Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below."]
654 #[inline(always)]
655 pub fn mode(&self) -> MODE_R {
656 MODE_R::new(((self.bits >> 30) & 0x01) != 0)
657 }
658 #[doc = "Bit 31 - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled."]
659 #[inline(always)]
660 pub fn seq_ena(&self) -> SEQ_ENA_R {
661 SEQ_ENA_R::new(((self.bits >> 31) & 0x01) != 0)
662 }
663}
664impl W {
665 #[doc = "Bits 0:11 - Selects which one or more of the ADC channels will be sampled and converted when this sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 and so forth. When this conversion sequence is triggered, either by a hardware trigger or via software command, ADC conversions will be performed on each enabled channel, in sequence, beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31) is LOW. It is allowed to change this field and set bit 31 in the same write."]
666 #[inline(always)]
667 pub fn channels(&mut self) -> CHANNELS_W {
668 CHANNELS_W { w: self }
669 }
670 #[doc = "Bits 12:14 - Selects which of the available hardware trigger sources will cause this conversion sequence to be initiated. Program the trigger input number in this field. See Table 476. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write."]
671 #[inline(always)]
672 pub fn trigger(&mut self) -> TRIGGER_W {
673 TRIGGER_W { w: self }
674 }
675 #[doc = "Bit 18 - Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write."]
676 #[inline(always)]
677 pub fn trigpol(&mut self) -> TRIGPOL_W {
678 TRIGPOL_W { w: self }
679 }
680 #[doc = "Bit 19 - Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period."]
681 #[inline(always)]
682 pub fn syncbypass(&mut self) -> SYNCBYPASS_W {
683 SYNCBYPASS_W { w: self }
684 }
685 #[doc = "Bit 26 - Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a conversion sequence. It will consequently always read back as a zero."]
686 #[inline(always)]
687 pub fn start(&mut self) -> START_W {
688 START_W { w: self }
689 }
690 #[doc = "Bit 27 - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions can be halted by clearing this bit. The sequence currently in progress will be completed before conversions are terminated. Note that a new sequence could begin just before BURST is cleared."]
691 #[inline(always)]
692 pub fn burst(&mut self) -> BURST_W {
693 BURST_W { w: self }
694 }
695 #[doc = "Bit 28 - When this bit is set, a hardware trigger or a write to the START bit will launch a single conversion on the next channel in the sequence instead of the default response of launching an entire sequence of conversions. Once all of the channels comprising a sequence have been converted, a subsequent trigger will repeat the sequence beginning with the first enabled channel. Interrupt generation will still occur either after each individual conversion or at the end of the entire sequence, depending on the state of the MODE bit."]
696 #[inline(always)]
697 pub fn singlestep(&mut self) -> SINGLESTEP_W {
698 SINGLESTEP_W { w: self }
699 }
700 #[doc = "Bit 29 - Set priority for sequence A."]
701 #[inline(always)]
702 pub fn lowprio(&mut self) -> LOWPRIO_W {
703 LOWPRIO_W { w: self }
704 }
705 #[doc = "Bit 30 - Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below."]
706 #[inline(always)]
707 pub fn mode(&mut self) -> MODE_W {
708 MODE_W { w: self }
709 }
710 #[doc = "Bit 31 - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled."]
711 #[inline(always)]
712 pub fn seq_ena(&mut self) -> SEQ_ENA_W {
713 SEQ_ENA_W { w: self }
714 }
715 #[doc = "Writes raw bits to the register."]
716 #[inline(always)]
717 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
718 self.0.bits(bits);
719 self
720 }
721}
722#[doc = "ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seq_ctrl](index.html) module"]
723pub struct SEQ_CTRL_SPEC;
724impl crate::RegisterSpec for SEQ_CTRL_SPEC {
725 type Ux = u32;
726}
727#[doc = "`read()` method returns [seq_ctrl::R](R) reader structure"]
728impl crate::Readable for SEQ_CTRL_SPEC {
729 type Reader = R;
730}
731#[doc = "`write(|w| ..)` method takes [seq_ctrl::W](W) writer structure"]
732impl crate::Writable for SEQ_CTRL_SPEC {
733 type Writer = W;
734}
735#[doc = "`reset()` method sets SEQ_CTRL%s to value 0"]
736impl crate::Resettable for SEQ_CTRL_SPEC {
737 #[inline(always)]
738 fn reset_value() -> Self::Ux {
739 0
740 }
741}