1#[doc = "Register `DAT[%s]` reader"]
2pub struct R(crate::R<DAT_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<DAT_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<DAT_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<DAT_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Field `RESULT` reader - This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0\\[n\\]
17pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP."]
18pub struct RESULT_R(crate::FieldReader<u16, u16>);
19impl RESULT_R {
20 pub(crate) fn new(bits: u16) -> Self {
21 RESULT_R(crate::FieldReader::new(bits))
22 }
23}
24impl core::ops::Deref for RESULT_R {
25 type Target = crate::FieldReader<u16, u16>;
26 #[inline(always)]
27 fn deref(&self) -> &Self::Target {
28 &self.0
29 }
30}
31#[doc = "Field `THCMPRANGE` reader - Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved."]
32pub struct THCMPRANGE_R(crate::FieldReader<u8, u8>);
33impl THCMPRANGE_R {
34 pub(crate) fn new(bits: u8) -> Self {
35 THCMPRANGE_R(crate::FieldReader::new(bits))
36 }
37}
38impl core::ops::Deref for THCMPRANGE_R {
39 type Target = crate::FieldReader<u8, u8>;
40 #[inline(always)]
41 fn deref(&self) -> &Self::Target {
42 &self.0
43 }
44}
45#[doc = "Field `THCMPCROSS` reader - Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold."]
46pub struct THCMPCROSS_R(crate::FieldReader<u8, u8>);
47impl THCMPCROSS_R {
48 pub(crate) fn new(bits: u8) -> Self {
49 THCMPCROSS_R(crate::FieldReader::new(bits))
50 }
51}
52impl core::ops::Deref for THCMPCROSS_R {
53 type Target = crate::FieldReader<u8, u8>;
54 #[inline(always)]
55 fn deref(&self) -> &Self::Target {
56 &self.0
57 }
58}
59#[doc = "Field `CHANNEL` reader - This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)"]
60pub struct CHANNEL_R(crate::FieldReader<u8, u8>);
61impl CHANNEL_R {
62 pub(crate) fn new(bits: u8) -> Self {
63 CHANNEL_R(crate::FieldReader::new(bits))
64 }
65}
66impl core::ops::Deref for CHANNEL_R {
67 type Target = crate::FieldReader<u8, u8>;
68 #[inline(always)]
69 fn deref(&self) -> &Self::Target {
70 &self.0
71 }
72}
73#[doc = "Field `OVERRUN` reader - This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled."]
74pub struct OVERRUN_R(crate::FieldReader<bool, bool>);
75impl OVERRUN_R {
76 pub(crate) fn new(bits: bool) -> Self {
77 OVERRUN_R(crate::FieldReader::new(bits))
78 }
79}
80impl core::ops::Deref for OVERRUN_R {
81 type Target = crate::FieldReader<bool, bool>;
82 #[inline(always)]
83 fn deref(&self) -> &Self::Target {
84 &self.0
85 }
86}
87#[doc = "Field `DATAVALID` reader - This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled."]
88pub struct DATAVALID_R(crate::FieldReader<bool, bool>);
89impl DATAVALID_R {
90 pub(crate) fn new(bits: bool) -> Self {
91 DATAVALID_R(crate::FieldReader::new(bits))
92 }
93}
94impl core::ops::Deref for DATAVALID_R {
95 type Target = crate::FieldReader<bool, bool>;
96 #[inline(always)]
97 fn deref(&self) -> &Self::Target {
98 &self.0
99 }
100}
101impl R {
102 #[doc = "Bits 4:15 - This field contains the 12-bit ADC conversion result from the last conversion performed on this channel. This will be a binary fraction representing the voltage on the AD0\\[n\\]
103pin, as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP."]
104 #[inline(always)]
105 pub fn result(&self) -> RESULT_R {
106 RESULT_R::new(((self.bits >> 4) & 0x0fff) as u16)
107 }
108 #[doc = "Bits 16:17 - Threshold Range Comparison result. 0x0 = In Range: The last completed conversion was greater than or equal to the value programmed into the designated LOW threshold register (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last completed conversion was greater than the value programmed into the designated HIGH threshold register (THRn_HIGH). 0x3 = Reserved."]
109 #[inline(always)]
110 pub fn thcmprange(&self) -> THCMPRANGE_R {
111 THCMPRANGE_R::new(((self.bits >> 16) & 0x03) as u8)
112 }
113 #[doc = "Bits 18:19 - Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this channel was above the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred - i.e. the previous sample on this channel was below the threshold value established by the designated LOW threshold register (THRn_LOW) and the current sample is above that threshold."]
114 #[inline(always)]
115 pub fn thcmpcross(&self) -> THCMPCROSS_R {
116 THCMPCROSS_R::new(((self.bits >> 18) & 0x03) as u8)
117 }
118 #[doc = "Bits 26:29 - This field is hard-coded to contain the channel number that this particular register relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 register, etc)"]
119 #[inline(always)]
120 pub fn channel(&self) -> CHANNEL_R {
121 CHANNEL_R::new(((self.bits >> 26) & 0x0f) as u8)
122 }
123 #[doc = "Bit 30 - This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set. This bit is cleared, along with the DONE bit, whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. This bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if the overrun interrupt is enabled. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled."]
124 #[inline(always)]
125 pub fn overrun(&self) -> OVERRUN_R {
126 OVERRUN_R::new(((self.bits >> 30) & 0x01) != 0)
127 }
128 #[doc = "Bit 31 - This bit is set to 1 when an ADC conversion on this channel completes. This bit is cleared whenever this register is read or when the data related to this channel is read from either of the global SEQn_GDAT registers. While it is allowed to include the same channels in both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the data registers associated with any of the channels that are shared between the two sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled."]
129 #[inline(always)]
130 pub fn datavalid(&self) -> DATAVALID_R {
131 DATAVALID_R::new(((self.bits >> 31) & 0x01) != 0)
132 }
133}
134#[doc = "ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dat](index.html) module"]
135pub struct DAT_SPEC;
136impl crate::RegisterSpec for DAT_SPEC {
137 type Ux = u32;
138}
139#[doc = "`read()` method returns [dat::R](R) reader structure"]
140impl crate::Readable for DAT_SPEC {
141 type Reader = R;
142}
143#[doc = "`reset()` method sets DAT[%s]
144to value 0"]
145impl crate::Resettable for DAT_SPEC {
146 #[inline(always)]
147 fn reset_value() -> Self::Ux {
148 0
149 }
150}