1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CTRL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CTRL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `CLKDIV` reader - In synchronous mode only, the system clock is divided by this value plus one to produce the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically, software should program the smallest value in this field that yields this maximum clock rate or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. This field is ignored in the asynchronous operating mode."]
38pub struct CLKDIV_R(crate::FieldReader<u8, u8>);
39impl CLKDIV_R {
40 pub(crate) fn new(bits: u8) -> Self {
41 CLKDIV_R(crate::FieldReader::new(bits))
42 }
43}
44impl core::ops::Deref for CLKDIV_R {
45 type Target = crate::FieldReader<u8, u8>;
46 #[inline(always)]
47 fn deref(&self) -> &Self::Target {
48 &self.0
49 }
50}
51#[doc = "Field `CLKDIV` writer - In synchronous mode only, the system clock is divided by this value plus one to produce the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically, software should program the smallest value in this field that yields this maximum clock rate or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. This field is ignored in the asynchronous operating mode."]
52pub struct CLKDIV_W<'a> {
53 w: &'a mut W,
54}
55impl<'a> CLKDIV_W<'a> {
56 #[doc = r"Writes raw bits to the field"]
57 #[inline(always)]
58 pub unsafe fn bits(self, value: u8) -> &'a mut W {
59 self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff);
60 self.w
61 }
62}
63#[doc = "The low-power ADC mode\n\nValue on reset: 0"]
64#[derive(Clone, Copy, Debug, PartialEq)]
65pub enum LPWRMODE_A {
66 #[doc = "0: The low-power ADC mode is disabled. The analog circuitry remains activated even when no conversions are requested."]
67 LPWRMODE_0 = 0,
68 #[doc = "1: The low-power ADC mode is enabled. The analog circuitry is automatically powered-down when no conversions are taking place. When any (hardware or software) triggering event is detected, the analog circuitry is enabled. After the required start-up time, the requested conversion will be launched. Once the conversion completes, the analog-circuitry will again be powered-down provided no further conversions are pending. Using this mode can save an appreciable amount of current (approximately 2.5 mA) when conversions are required relatively infrequently. The penalty for using this mode is an approximately FIFTEEN ADC CLOCK delay (30 clocks in 10-bit mode), based on the frequency specified in the CLKDIV field, from the time the trigger event occurs until sampling of the A/D input commences. Note: This mode will NOT power-up the A/D if the ADC_ENA bit is low."]
69 LPWRMODE_1 = 1,
70}
71impl From<LPWRMODE_A> for bool {
72 #[inline(always)]
73 fn from(variant: LPWRMODE_A) -> Self {
74 variant as u8 != 0
75 }
76}
77#[doc = "Field `LPWRMODE` reader - The low-power ADC mode"]
78pub struct LPWRMODE_R(crate::FieldReader<bool, LPWRMODE_A>);
79impl LPWRMODE_R {
80 pub(crate) fn new(bits: bool) -> Self {
81 LPWRMODE_R(crate::FieldReader::new(bits))
82 }
83 #[doc = r"Get enumerated values variant"]
84 #[inline(always)]
85 pub fn variant(&self) -> LPWRMODE_A {
86 match self.bits {
87 false => LPWRMODE_A::LPWRMODE_0,
88 true => LPWRMODE_A::LPWRMODE_1,
89 }
90 }
91 #[doc = "Checks if the value of the field is `LPWRMODE_0`"]
92 #[inline(always)]
93 pub fn is_lpwrmode_0(&self) -> bool {
94 **self == LPWRMODE_A::LPWRMODE_0
95 }
96 #[doc = "Checks if the value of the field is `LPWRMODE_1`"]
97 #[inline(always)]
98 pub fn is_lpwrmode_1(&self) -> bool {
99 **self == LPWRMODE_A::LPWRMODE_1
100 }
101}
102impl core::ops::Deref for LPWRMODE_R {
103 type Target = crate::FieldReader<bool, LPWRMODE_A>;
104 #[inline(always)]
105 fn deref(&self) -> &Self::Target {
106 &self.0
107 }
108}
109#[doc = "Field `LPWRMODE` writer - The low-power ADC mode"]
110pub struct LPWRMODE_W<'a> {
111 w: &'a mut W,
112}
113impl<'a> LPWRMODE_W<'a> {
114 #[doc = r"Writes `variant` to the field"]
115 #[inline(always)]
116 pub fn variant(self, variant: LPWRMODE_A) -> &'a mut W {
117 self.bit(variant.into())
118 }
119 #[doc = "The low-power ADC mode is disabled. The analog circuitry remains activated even when no conversions are requested."]
120 #[inline(always)]
121 pub fn lpwrmode_0(self) -> &'a mut W {
122 self.variant(LPWRMODE_A::LPWRMODE_0)
123 }
124 #[doc = "The low-power ADC mode is enabled. The analog circuitry is automatically powered-down when no conversions are taking place. When any (hardware or software) triggering event is detected, the analog circuitry is enabled. After the required start-up time, the requested conversion will be launched. Once the conversion completes, the analog-circuitry will again be powered-down provided no further conversions are pending. Using this mode can save an appreciable amount of current (approximately 2.5 mA) when conversions are required relatively infrequently. The penalty for using this mode is an approximately FIFTEEN ADC CLOCK delay (30 clocks in 10-bit mode), based on the frequency specified in the CLKDIV field, from the time the trigger event occurs until sampling of the A/D input commences. Note: This mode will NOT power-up the A/D if the ADC_ENA bit is low."]
125 #[inline(always)]
126 pub fn lpwrmode_1(self) -> &'a mut W {
127 self.variant(LPWRMODE_A::LPWRMODE_1)
128 }
129 #[doc = r"Sets the field bit"]
130 #[inline(always)]
131 pub fn set_bit(self) -> &'a mut W {
132 self.bit(true)
133 }
134 #[doc = r"Clears the field bit"]
135 #[inline(always)]
136 pub fn clear_bit(self) -> &'a mut W {
137 self.bit(false)
138 }
139 #[doc = r"Writes raw bits to the field"]
140 #[inline(always)]
141 pub fn bit(self, value: bool) -> &'a mut W {
142 self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
143 self.w
144 }
145}
146#[doc = "Field `CALMODE` reader - Writing a '1' to this bit will initiate a sef-calibration cycle. This bit will be automatically cleared by hardware after the calibration cycle is complete. Note: Other bits of this register may be written to concurrently with setting this bit, however once this bit has been set no further writes to this register are permitted unitl the full calibration cycle has ended."]
147pub struct CALMODE_R(crate::FieldReader<bool, bool>);
148impl CALMODE_R {
149 pub(crate) fn new(bits: bool) -> Self {
150 CALMODE_R(crate::FieldReader::new(bits))
151 }
152}
153impl core::ops::Deref for CALMODE_R {
154 type Target = crate::FieldReader<bool, bool>;
155 #[inline(always)]
156 fn deref(&self) -> &Self::Target {
157 &self.0
158 }
159}
160#[doc = "Field `CALMODE` writer - Writing a '1' to this bit will initiate a sef-calibration cycle. This bit will be automatically cleared by hardware after the calibration cycle is complete. Note: Other bits of this register may be written to concurrently with setting this bit, however once this bit has been set no further writes to this register are permitted unitl the full calibration cycle has ended."]
161pub struct CALMODE_W<'a> {
162 w: &'a mut W,
163}
164impl<'a> CALMODE_W<'a> {
165 #[doc = r"Sets the field bit"]
166 #[inline(always)]
167 pub fn set_bit(self) -> &'a mut W {
168 self.bit(true)
169 }
170 #[doc = r"Clears the field bit"]
171 #[inline(always)]
172 pub fn clear_bit(self) -> &'a mut W {
173 self.bit(false)
174 }
175 #[doc = r"Writes raw bits to the field"]
176 #[inline(always)]
177 pub fn bit(self, value: bool) -> &'a mut W {
178 self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30);
179 self.w
180 }
181}
182impl R {
183 #[doc = "Bits 0:7 - In synchronous mode only, the system clock is divided by this value plus one to produce the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically, software should program the smallest value in this field that yields this maximum clock rate or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. This field is ignored in the asynchronous operating mode."]
184 #[inline(always)]
185 pub fn clkdiv(&self) -> CLKDIV_R {
186 CLKDIV_R::new((self.bits & 0xff) as u8)
187 }
188 #[doc = "Bit 10 - The low-power ADC mode"]
189 #[inline(always)]
190 pub fn lpwrmode(&self) -> LPWRMODE_R {
191 LPWRMODE_R::new(((self.bits >> 10) & 0x01) != 0)
192 }
193 #[doc = "Bit 30 - Writing a '1' to this bit will initiate a sef-calibration cycle. This bit will be automatically cleared by hardware after the calibration cycle is complete. Note: Other bits of this register may be written to concurrently with setting this bit, however once this bit has been set no further writes to this register are permitted unitl the full calibration cycle has ended."]
194 #[inline(always)]
195 pub fn calmode(&self) -> CALMODE_R {
196 CALMODE_R::new(((self.bits >> 30) & 0x01) != 0)
197 }
198}
199impl W {
200 #[doc = "Bits 0:7 - In synchronous mode only, the system clock is divided by this value plus one to produce the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically, software should program the smallest value in this field that yields this maximum clock rate or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. This field is ignored in the asynchronous operating mode."]
201 #[inline(always)]
202 pub fn clkdiv(&mut self) -> CLKDIV_W {
203 CLKDIV_W { w: self }
204 }
205 #[doc = "Bit 10 - The low-power ADC mode"]
206 #[inline(always)]
207 pub fn lpwrmode(&mut self) -> LPWRMODE_W {
208 LPWRMODE_W { w: self }
209 }
210 #[doc = "Bit 30 - Writing a '1' to this bit will initiate a sef-calibration cycle. This bit will be automatically cleared by hardware after the calibration cycle is complete. Note: Other bits of this register may be written to concurrently with setting this bit, however once this bit has been set no further writes to this register are permitted unitl the full calibration cycle has ended."]
211 #[inline(always)]
212 pub fn calmode(&mut self) -> CALMODE_W {
213 CALMODE_W { w: self }
214 }
215 #[doc = "Writes raw bits to the register."]
216 #[inline(always)]
217 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
218 self.0.bits(bits);
219 self
220 }
221}
222#[doc = "ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
223pub struct CTRL_SPEC;
224impl crate::RegisterSpec for CTRL_SPEC {
225 type Ux = u32;
226}
227#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
228impl crate::Readable for CTRL_SPEC {
229 type Reader = R;
230}
231#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
232impl crate::Writable for CTRL_SPEC {
233 type Writer = W;
234}
235#[doc = "`reset()` method sets CTRL to value 0"]
236impl crate::Resettable for CTRL_SPEC {
237 #[inline(always)]
238 fn reset_value() -> Self::Ux {
239 0
240 }
241}